JPH0140438B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Field of the Invention The present invention relates to electrically programmable non-volatile semiconductor memory devices.

(2) Description of the Prior Art Floating gate MOS type memory cells are generally used as memory elements in electrically programmable nonvolatile semiconductor memory devices (generally referred to as EPROMs).

The cross-sectional structure of a general N-channel cell is shown in the first section.
As shown in the figure. To write to this cell, ground the source electrode 1 and apply a positive voltage to the control gate electrode 2.
A write voltage is applied to the drain electrode 3. At this time, the channel 4 of the cell is in an inverted state, and some of the electrons flowing through the channel are accelerated by the high electric field between the source and drain, become hot, and are injected into the floating gate 6 over the energy barrier of the gate oxide film 5. be done. This is called channel electron injection writing.

FIG. 2 shows a memory cell array in a conventional EPROM, and a method for writing selected bits will be explained. In FIG. 2, a (2×2) cell matrix is shown for simplicity. The control gate electrodes of memory cells arranged horizontally are commonly connected to form a word line
1, form x2. The drain electrodes of the memory cells arranged in the vertical direction are commonly connected to form bit lines Y1 and Y2, and each bit line is connected to a program power supply Vp via switch transistors T1 and T2 for applying a program voltage. The source electrodes of the memory cells are connected to a common ground GND.
For example, when writing to memory cell M1, keep word line ×1 at a positive high voltage, for example, Vp,
A positive high voltage, for example Vp, is applied to the gate W1 of the transistor T1. At this time, bit line Y1
The potential of is raised by the power supply voltage via switch transistor T1, a write current flows through cell M1, and channel electron injection is performed.

As shown in FIG. 3, the drain voltage of the cell M1 during writing, that is, the potential of the bit line Y1, is the intersection point V _D of the current-voltage characteristic I1 of the cell M1 and the load current-voltage characteristic I _L of the switch transistor T1. . Typically, the switch transistor is replaced by a write circuit rather than a single transistor.

Now, when electron injection begins in cell M1, the threshold voltage rises, the current-voltage characteristic of cell M1 moves downward to I1', and the potential of bit line Y1 moves along load line _IL . It rises to V _D ′. Thus, as cell writing progresses, the potential of bit line Y1 increases along load line _IL . As the writing progresses further, the breakdown point BV when writing to cell M1 becomes the load line I _L
When the value is lower than , the current-voltage characteristic shows a negative resistance characteristic, like I2, and a large current flows, causing problems such as cell destruction. Furthermore, when the program voltage applied from the outside is increased, the load line _IL moves to the right, making the above-described breakdown more likely to occur. In order to avoid problems caused by breakdown, the voltage applied to the drain of the memory cell, ie, the bit line, must be kept below the breakdown voltage. Generally, memory cell write voltage (voltage sufficient for writing)
The difference in breakdown voltage, that is, the write voltage margin, is quite small and there is no margin.

(3) Purpose of the invention Since the prior art has the above-mentioned problems,
An object of the present invention is to eliminate these problems and provide an EPROM with a wide write voltage margin when viewed from the outside.

(4) Features of the Invention The present invention is characterized in that floating gate transistor memory cells are arranged in an X-Y matrix as non-volatile memory elements, and the control gate electrodes of the memory cells arranged in the X direction are commonly connected. A word line is formed, and the drain electrodes of the memory cells arranged in the Y direction are commonly connected to form a bit line, and each bit line is connected to a program power source via a switch transistor for applying a program voltage. In the semiconductor memory device, a second switch transistor for applying a program voltage is provided between the switch transistor and the program power supply, a drain is connected to a connection point between the switch transistor and the second switch transistor, and a gate is connected to the connection point between the switch transistor and the second switch transistor. A bypass circuit is connected to the bit line and the source is grounded through a bypass transistor whose source is grounded, or a predetermined number of series-connected transistors whose drains and gates are connected. detects the voltage of
The present invention is characterized in that when the voltage on the bit line becomes higher than a specified voltage, the write power supply current is bypassed to the ground line, thereby suppressing the increase in the voltage on the bit line.

(5) Effects of the Invention According to the present invention, if the above specified voltage is set as the write voltage of the memory cell, the voltage of the bit line can be adjusted to the voltage of the memory cell by adding such a bypass circuit. Regardless of the write state and the rise of the external program power supply, the voltage is almost fixed to the write voltage and no breakdown occurs.

(6) Examples The present invention will be described in detail below using examples and drawings.

FIG. 4 is a circuit diagram of the first embodiment. Fourth
In the figure, only one bit line and one memory cell are shown for simplicity. Memory cell M
The bit line Y1 connected to the drain of
It is connected to a write power supply V _P via write switch transistors T1 and S1. Also, T1
and S1 are connected to write signal lines W1 and W, respectively.
2, the control gate of memory cell M is connected to word line X1. An intermediate point A between the write switch transistors T1 and S1 is connected to the drain of the bypass transistor BT, and the source of BT is connected to the ground line GND. Bit line Y1 is also connected to the gate of bypass transistor BT.

The write voltage of the memory cell M1 used in this example is V6. Since the breakdown voltage is 8V, the threshold voltage of the bypass transistor BT is set to 6V.
The combined load characteristics of the writing transistors T1 and S1 were set as shown in FIG. 5, together with the initial characteristics of the memory cell M1 during writing. Fifth
In the figure, the current-voltage characteristic of the cell at the initial stage of writing when the program voltage V _P is applied to W1, W2, and X1 is shown as I1, the load characteristic is shown as I _L , and the potential at point A in FIG. 4 is shown as V _A. In this case, the voltage at the intersection of both curves, ie, the bit line Y1 potential, is 6V. Now, suppose that the current-voltage characteristics change as shown by I1' as writing to the memory cell progresses over time, then the voltage V _D of the bit line Y1 increases along I _L ,
Higher than 6V. When the voltage on the bit line becomes higher than 6V, the bypass transistor BT becomes conductive, and the bypass current flows from point A to the ground line GND.
, the potential at point A drops to a value determined by the ratio of the conductances of T1 and BT. In FIG. 5, the load line I _L moves to the left to become I _L ', and the injection on bit line B drops to V _D '.
Due to this feedback mechanism, the potential of bit line Y1 is almost fixed without increasing significantly from the write voltage of 6V, so the breakdown voltage
It never reaches 8V.

In the circuit of this embodiment, even if the power supply voltage V _P increases, the voltage increase on the bit line Y1 is suppressed by the same feedback effect as described above.

FIG. 6 shows a circuit diagram of the second embodiment. The meaning of each symbol in this embodiment is the same as that in FIG. 4. In FIG. 6, instead of using the bypass transistor BT alone in FIG. 4,
A bypass circuit is used in which n stages of transistors Q1 to Qn whose drains and gates are commonly connected to the source of the transistor BT are connected in series and grounded.
Thereby, the threshold voltage of the bypass circuit can be increased by n times the threshold voltage of the transistors Q1 to Qn. In the first embodiment, since the bypass circuit was formed by 31 transistors T, special measures were required in the manufacturing process to set the threshold voltage to 6V. For example, this problem was solved by making the BT gate oxide film thicker.

On the other hand, in this embodiment, since the threshold voltage of the bypass circuit can be adjusted by the number of stages of transistors connected in series to the source of BT, as the bypass transistors BT and Q1 to Qn,
The same regular transistors that make up the other circuit parts can be used. Therefore, there is no need to use a special transistor as used in the first embodiment, and the manufacturing process is simplified.

As explained above using the embodiments, when the present invention is used, the voltage applied to the drain of the memory cell during writing can be almost fixed at a voltage slightly higher than the writing voltage, so that breakdown occurs in the memory cell. Stable writing is possible without causing this. Furthermore, a nonvolatile semiconductor memory device with a wide programming voltage margin when viewed from the outside can be easily manufactured.

[Brief explanation of drawings]

Figure 1 shows the cross-sectional structure of a nonvolatile memory cell, Figure 2 shows the cross-sectional structure of a nonvolatile memory cell.
The figure shows a memory cell array in a conventional device, FIG. 3 shows the write current and voltage of the cells in the circuit shown in FIG. 2, and the load current and voltage characteristics of the load transistor, and FIG. FIG. 5 shows the current-voltage characteristics of the cell and load transistor in FIG. 4, and FIG. 6 is a circuit diagram of the second embodiment of the present invention. In the figure, 1...the source of the memory cell, 2
... Control gate of memory cell, 3... Drain of memory cell, 4... Channel region of memory cell, 5... Gate insulating film of memory cell, 6... Floating gate of memory cell, V _P ... Power supply for writing, T1, T2 , S1...
Write switch transistors, M1, M2, M3,
M4...Memory cell, BT...Bypass transistor, Q1~Qn...Threshold voltage adjustment transistor, X1, X2...Word line, Y1, Y2
...Bit line, W1, W2...Write signal line,
I1, I1'...Current-voltage characteristics of memory cell, I2
...Current-voltage characteristics during memory cell breakdown,
I _L , I _L ′...Load current-voltage characteristics, V _D , V _D ′...Drain voltage of the memory cell, BV... Breakdown voltage of the memory cell.

Claims (1)

[Claims] 1. Floating gate transistor memory cells are arranged in an X-Y matrix as non-volatile memory elements, and the control gate electrodes of the memory cells arranged in the X direction are commonly connected to form a word line. The drain electrodes of the memory cells arranged in the Y direction are commonly connected to form a bit line, and each bit line is connected to a program power source via a switch transistor for applying a program voltage. In the device, a second switch transistor for applying a program voltage is provided between the switch transistor and the program power supply, a drain is connected to a connection point between the switch transistor and the second switch transistor, and a gate is connected to the bit line. a bypass transistor connected and whose source is grounded, or
It has a bypass circuit whose source is grounded through a predetermined number of series-connected transistors whose drains and gates are connected, and detects the voltage of the bit line during writing, and detects whether the voltage of the bit line is lower than a specified voltage. 1. A nonvolatile semiconductor memory device characterized in that when the bit line voltage rises, the voltage increase of the bit line can be controlled by bypassing the write power supply current to a ground line. 2. The nonvolatile semiconductor memory device according to claim 1, wherein the specified voltage is set to be lower than a drain breakdown voltage of the memory cell.