JPH0142067B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a playback device for a so-called video format PCM signal which has a signal format similar to that of a normal TV signal and carries PCM modulated audio information, and particularly relates to a playback device for such a The present invention relates to a data section extraction circuit.

Background technology Video format PCM with reference to Figure 1
The signal configuration of the signal will be explained. A video format PCM signal consists of consecutive frames each consisting of a pair of odd and even fields.
Each of the odd field and the even field has a time length of 262.5H, where H represents the horizontal scanning period. In odd-numbered fields, the 3H time from the 4th to 6th H counting from the beginning of the field is a vertical synchronization pulse, and the 10th H is a data cue pulse (hereinafter referred to as "data cue pulse") indicating that a data section will follow.
(referred to as SH pulse), and from the 11th H onwards,
The 255th H is a data interval. Furthermore, in the even field, from immediately after 265.5H to 268.5H is the vertical synchronization pulse, 273H is the SH pulse, and 274H to 518H is the data interval.

Video format with signal configuration as above
The circuit that extracts the data section containing PCM audio information from the PCM signal is the video format.
This is necessary for a PCM signal reproducing device, and is called a data section extraction circuit. This data section extraction circuit first separates and detects the SH pulse from the video format PCM signal, and then
The data interval is detected using pulse timing. However, there were cases where the SH pulse could not be detected correctly due to so-called dropout or an external nozzle, making it impossible to reproduce the signal correctly.

To solve this problem, in conventional devices, the one-shot multi was triggered by a vertical synchronization pulse (hereinafter referred to as the V synchronization pulse) to correct the SH pulse, but the V synchronization pulse itself also It was not possible to make a reliable correction because it could not be detected or the position could be shifted due to dropout or external noise.

SUMMARY OF THE INVENTION Therefore, it is an object of the present invention to
It is an object of the present invention to provide a data section extraction circuit capable of accurately extracting a data section even when an SH pulse in a PCM signal cannot be detected correctly due to dropout or external noise.

In order to achieve the above object, the data section extracting circuit of the present invention has the following features:
Separation detection means for separating and detecting horizontal synchronization pulses, vertical synchronization pulses and data signals based on differences in voltage levels from the signals; a cueing pulse detection circuit for detecting data cueing pulses from the data signals;
H to count horizontal sync pulses for one frame
a pulse counter; a decoder that generates a data interval start pulse and a data interval display signal according to the count value of the H pulse counter; and a decoder that counts the data interval start pulse and generates a trigger signal when the count value reaches a predetermined value. Only when the data cue pulse and the data section start pulse occur within the same horizontal scanning period, according to the generated start pulse counting means, the horizontal and vertical synchronizing pulses, the data section start pulse, and the data cue pulse. a timing control circuit for resetting the start pulse counter and resetting the H pulse counter in response to the trigger signal; and a data interval control circuit for extracting the data interval from the video format PCM signal in response to the data interval display signal. It is characterized by comprising a gate generation circuit that generates a gate signal.

Embodiments Hereinafter, embodiments of the present invention will be described with reference to FIG. 2 and the following drawings.

FIG. 2 shows a data section extracting circuit according to the present invention, in which input video format PCM
The composite synchronization pulse (hereinafter referred to as CS pulse) containing the data signal and V and H synchronization pulses in the signal is
Due to the difference in threshold level, data separation circuit 1 and
The CS pulse separation circuit 2 separates and detects each pulse. The SH pulse detection circuit 3 separates and detects the SH pulse from the separated and detected data signal.
The separated and detected SH pulses are supplied to the timing control circuit 4.

On the other hand, the separated and detected CS pulse is supplied to a V synchronization pulse separation circuit 5 and an H synchronization pulse separation circuit 6. The V synchronization pulse circuit 5 separates and detects the V synchronization pulse from the CS pulse and supplies it to the timing control circuit 4. The H synchronization pulse separation circuit 6 separates and detects the H synchronization pulse from the CS pulse and supplies it to the H pulse counter 7 and the timing control circuit 4. The timing control circuit 4 controls the arrival of the SH pulse immediately after the V synchronization pulse and the timing of first and second counters 9 and 10, which will be described later.
The H pulse counter 7 and the first counter 9 are reset under any one of the overflow conditions. The H pulse counter 7 counts the H synchronization pulses supplied to the trigger terminal, and its counting capacity is equal to the number of H synchronization pulses in one frame.
It is listed as 525.

When the count output of the H pulse counter 7 reaches 263, the decoder 8 generates an even field data interval start pulse (hereinafter referred to as EV pulse) to the EV terminal, and when it reaches 525, an odd field data interval start pulse (hereinafter referred to as EV pulse) is generated at the EV terminal. (referred to as OD pulse)
is generated at the OD terminal. The OD and EV pulses are supplied to the timing control circuit 4 and the trigger terminals T of the data period start pulse first and second counters 9 and 10. The data interval display signal of the decoder 8 is supplied to the gate signal generation circuit 11 via output terminals G ₁ to G ₄ .
1 generates a data interval gate signal in response to a data interval display signal.

FIG. 3 shows a specific circuit example of the timing control circuit 4 in FIG. 2. In FIG. In this circuit, flip-flop 20 is set by the V sync pulse;
It is reset by a Q output of 1. flip-flop
The Q output of flop 20 is logically ANDed with the SH pulse by AND gate 23 and becomes the set input of flip-flop 21. flip flop 2
1 is reset by the H sync pulse. The input signals from the OVF terminals of counters 9 and 10 are
The OR gate 24 performs a logical sum and becomes one input of an AND gate 25. The other input of AND gate 25 is the Q output of flip-flop 21. The output of the AND gate 25 serves as a reset output to the counter 7. flip flop 21
The Q output of is ANDed with the signals from the EV and OD output terminals of the decoder 8 by AND gates 26 and 27, and becomes a reset pulse for each of the counters 9 and 10.

The Q output of the flip-flop 21 in this circuit becomes logic "1" after the SH pulse is generated until the next H synchronization pulse occurs, and the data interval start pulse is supplied from the decoder 8 within this logic "1" period. Then, the AND gate 26 passes through the OR gate 28, and the AND gate 27 directly passes each counter 9, 10.
Supply a reset pulse to Further, when receiving a trigger (OVF) signal from either counter 9 or 10 within the period of logic "1", AND gate 25 supplies a reset signal to counter 7. Also, the output of AND gate 25 is OR gate 2
8 becomes a reset signal for the counter 9.

FIG. 4 shows specific circuit examples of each of the H pulse counter 7, decoder 8, and gate signal generation circuit 11 of the circuit shown in FIG. In this case, the H-pulse counter 7 uses a 12-bit counter 30 and presets the initial value to 500 when the count value reaches 1024.
I'm trying to count it. This is to simplify decoding. The _Q11 terminal of the counter 30 corresponds to 1024 counts. Further, the counter 30 is preset to a count of 500 by either the output from the _Q11 terminal or the reset signal from the timing control 4.

The decoder 8 includes a line 40 connecting the Q ₁₁ terminal of the counter 30 and the output terminal G ₁ and a line 40 connecting the Q 11 terminal of the counter 30 and the output terminal G 1
A terminal that is connected to some of the terminals Q ₁ to Q ₁₁ of
Logic circuits 41, 42, 4 each supplying G ₂ to G ₄
3. The signals on logic circuit 42 and line 40 become the outputs of the EV and OD terminals.

The gate signal generation circuit 11 consists of flip-flops 50 and 51 and an OR gate 52.
The output of OR gate 52 is 500H to 744H and 762H
This is a data interval gate signal generated between ~1007H.

Next, the operation of each part of the circuit shown in FIGS. 2 and 3 will be explained with reference to FIGS. 5 and 6.

5A to 5F show signal changes in each part of the timing control circuit 4 of FIG. 3, in which a V synchronization pulse as shown in FIG. When the SH pulse shown in B is input to the AND gate 23, the flip-flop 21 is set, and the D pulse of its Q output rises as shown in FIG. It will be reset. Therefore, the Q output of the flip-flop 21 is shown in FIG.
The level becomes low due to the H pulse immediately after the SH pulse. If either counter 9 or 10 is generating an OVF output while the D pulse is being generated, a reset output R is output from the AND gate 25.
occurs, the H pulse counter 7 is reset, and the H pulse counter 7 is reset.
The pulse counter 7 restarts integration from the H synchronization pulse immediately after the SH pulse. Further, the counter 9 is also reset.

Next, when a data interval start pulse as shown in FIG. 5E appears at the EV terminal of the decoder 8 (EV pulse) while the D pulse of the flip-flop 21 is being generated, A reset pulse as shown in Figure F is sent out. The counter 10 is reset by this reset pulse. Also, while the D pulse is being generated,
When a data interval start pulse like this appears at the OD terminal (OD pulse), the fifth
A reset pulse as shown in Figure F is sent. The counter 9 is reset by this reset pulse.

In this way, the SH pulse immediately after the V synchronization pulse
The counter 9 is reset every time an OD pulse occurs within the same horizontal scanning period (hereinafter referred to as an H period). Further, the counter 10 is reset every time an SH pulse and an EV pulse immediately after the V synchronization pulse occur within the same H period.

However, the period from the SH pulse of the odd field to the SH pulse of the even field (263H), and from the SH pulse of the even field to the period of the odd field
The periods up to the SH pulse (262H) are different from each other. Therefore, when the H pulse counter 7 is reset by an odd field SH pulse,
The OD and EV pulses occur at approximately the same timing as the SH pulses of each field.

Therefore, if the H pulse counter 7 is reset to the timing of the SH pulse of an even field, each SH pulse and the OD or EV pulse will not occur in the same H period, and the first or second counter 9, 10 is not reset and overflows. Then, due to the overflow output of the first or second counter, a signal that has passed through the OR gate 24 of the timing controller 4 is supplied to the AND gate 5, which generates a reset pulse of the H pulse counter at the timing of the next SH pulse. Reset the pulse counter 7. In this way, the H pulse counter 7
After being reset by , OD and EV pulses can be obtained at the correct timing.

The initial operation until the circuit of FIG. 2 synchronizes with the data section of the video format PCM signal will be described with reference to FIGS. 6A to 6D.

FIG. 6A shows that the counter 9 that counts the data interval start pulse of the odd field overflows before the counter 10 by integrating the OD output from the decoder 8 (FIG. 6A) eight times in a row, for example. This shows the case where the OVF signal E (see the same figure) is supplied to the timing control circuit 4. When the counter 9 overflows after the even field SH pulse (see the same figure) and before the odd field SH pulse (see the same figure), the timing control circuit 4
The H pulse counter 7 is reset by the OVF signal H (same figure) and the SH pulse, and the counter 9 is also reset (same figure). Therefore, the H pulse counter 7 restarts integration from the H pulse immediately after the SH pulse, and is synchronized with the data start position of the odd field.

FIG. 6B shows that the counter 10 is the EV pulse (sixth
This figure shows a case where the predetermined number of integrations in Figure B overflows before the counter 9 (Figure B) and the overflow time is after the SH pulse of the even field and before the SH pulse of the odd field.
Note that the waveforms of the V synchronization pulse and the SH pulse are omitted in this figure. When the counter 10 overflows due to the EV pulse (same figure), the OVF pulse (same figure) is supplied to the timing control circuit 4. The timing control circuit 4 supplies a reset pulse (shown in the same figure) to the counters 7 and 9 to reset them when the SH pulse of an odd field is supplied after the OVF pulse (shown in the figure) of the counter 10 is generated. As a result, when the counter 7 starts integrating and the count value reaches 263, an EV pulse is generated. this
When the EV pulse and the SH pulse are synchronized, the overflow of the counter 10 is reset (as shown in the figure).

FIG. 6C shows the case where counter 9 overflows earlier than counter 10 (FIG. 6C) and the time is after the odd field SH pulse (FIG. 6C) and before the even field SH pulse (FIG. 6C). It shows.

In this case, a reset pulse (see the same figure) is generated by the SH pulse of the next even field (see the same figure), and counter 7 is preset and counter 9 is reset, but counter 10 is not reset, so a reset pulse is generated in the following odd field. When the counter 10 overflows due to the EV pulse (same figure), the counter 7 is preset again (same figure). Counter 10 overflows (same figure)
Even if the counter 10 is reset, the counter 10 is not reset by the generation of the reset pulse (see figure 3) (see figure 3), and is reset by the EV output from decoder 8 (see figure) caused by the generation of the SH pulse in the next even field. be done. At this point, the EV output and the even field SH pulse are synchronized.

FIG. 6D shows a case where the SH pulse (FIG. 6C) and the OD pulse (FIG. 6D) of the odd field are synchronized.

At this time, counter 9 is reset by the SH pulse and OD pulse, but counters 7 and 10 are not reset. EV pulse (same figure)
is output and counter 10 overflows (FIG. 6), counters 7 and 9 are reset by the subsequent supply of SH pulse (FIG. 6C) (FIG. 6D). At this time, the counter 10 is not reset and continues to output the overflow.
Next, the counter 7 restarts integration from the reset pulse (same figure), counts 263 pulses, and outputs an EV pulse (same figure). When this synchronizes with the SH pulse, the counter 10 is reset (see the figure).

Thus, the odd field SH pulse and OD
The pulses are synchronized with the even field SH pulses.
EV pulses are synchronized. As long as this synchronization is maintained, counters 9 and 10 continue to be reset, and in the synchronized state, timing control circuit 4
The reset pulse R is never supplied to the counter 7 from the counter 7.

The operations shown in Figure 6C and Figure 6D are the SH pulse and the data interval start pulse (OD output and EV output).
This is caused by the fact that even if they match, the time interval between the SH pulse of the odd field and the SH pulse of the even field is different in the case of odd field → even field and even field → odd field.

Effects of the Invention As explained above, in the data section extracting circuit according to the present invention, the input video format is reset by the SH pulse and overflow output of the input video format PCM signal, and the video format is extracted.
Every time the count value of the H pulse counter that counts the H pulses of the PCM signal reaches one of two predetermined values, an OD pulse is generated, and each time it reaches the other value, an EV pulse is generated and the H pulse counter While the period when the count value is within a predetermined range is considered to be the data interval, if it is detected that the OD pulse and EV pulse do not occur within the same H period as the corresponding SH pulse, this state will be resolved. The H pulse counter is reset by the SH pulse until the As a result, the OD pulse and EV pulse are generated within the same H period as the corresponding SH pulse, and the V of the video format signal is reduced due to dropout, etc.
Even if some synchronization pulses or SH pulses cannot be detected, a data interval gate signal that correctly defines the data interval is generated, so data can be extracted. Furthermore, even if there is a relatively long dropout, it has the effect of recovering immediately after the dropout ends. Furthermore, it has a relatively simple circuit configuration without using an odd/even field discrimination circuit, and is inexpensive.

[Brief explanation of drawings]

Fig. 1 is a signal waveform diagram showing the signal configuration of a video format signal, Fig. 2 is a circuit diagram showing an embodiment of the present invention, and Figs. 3 and 4 are part of the circuit shown in Fig. 2. FIG. 5 is a circuit diagram showing a specific example of the circuit shown in FIG. 3, and FIG.
Figures A to 6D are signal waveform diagrams showing signal waveforms of some of the circuits in Figure 2. Explanation of symbols of main parts, 1...Data separation circuit,
2...CS pulse separation circuit, 3...SH pulse detection circuit, 4...timing control circuit, 5...V synchronous pulse separation circuit, 6...H synchronous pulse separation open circuit,
7... H pulse counter, 8... Decoder, 9... Data section start pulse first counter, 10... Data section start pulse second counter, 11... Data section gate signal generation circuit.

Claims (1)

[Claims] 1. A data section extraction circuit in a video format PCM signal reproducing device, which separates and detects horizontal synchronizing pulses, vertical synchronizing pulses, and data signals from input video format PCM signals based on differences in voltage levels; a cue pulse detection circuit that detects a data cue pulse from the data signal; an H pulse counter that counts horizontal synchronizing pulses for one frame;
a decoder that generates a data interval start pulse and a data interval display signal according to a count value of a pulse counter; and a start pulse counter means that counts the data interval start pulse and generates a trigger signal when the count value reaches a predetermined value. and, in response to the horizontal and vertical synchronization pulses, the data section start pulse, and the data cue pulse, the start pulse counter is reset only when the data cue pulse and the data section start pulse occur within the same horizontal scanning period. and a timing control circuit for resetting the H pulse counter in response to the trigger signal, and a gate signal for generating a data interval gate signal for extracting a data interval from the video format PCM signal in response to the data interval display signal. A circuit characterized in that it consists of a generator circuit.