JPH0142500B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a carrier tape for bonding a two-layer integrated circuit, and a method for manufacturing the tape.

For example, various methods have already been proposed as means for bonding IC chips and LSI chips, one of which is a tape carrier method. In this method, an adhesive is applied to one side of a tape made of polyimide film, for example, and device holes and sprocket holes are punched therein, and a layer of copper foil is provided on the adhesive side. A photoresist film is coated there, lead patterns of the required shape and number are baked and developed, and then etched and peeled off to form copper leads on the tape. On the other hand, gold bumps are formed on IC chips or LSI chips, which are then inner bonded to the leads on the tape, and a large number of chips are successively assembled onto the tape. The tape-side leads are then separated from the tape and outer bonded to a metal lead frame, printed circuit board, etc.

The tape carrier method described above is very efficient in automatic bonding, has a degree of freedom in lead patterns, and has the advantage of being able to test the characteristics of each chip while it is assembled in the tape. However, in this type of conventional tape carrier system, in order to incorporate two integrated circuits such as ICs and LSIs into the tape, the length of the carrier tape for the two times is naturally required. In addition, when mounting two integrated circuits, each needs to be mounted separately, which naturally requires two mounting spaces, and the degree of integration in this respect is still insufficient. It was hot.

The present invention relates to a carrier tape for integrated circuits, and is an object of the present invention to solve the above-mentioned problems of conventional carrier tapes. In other words, its purpose is to
In addition, two integrated circuits such as ICs and LSIs can be mounted on both sides of the carrier tape, and both the upper and lower circuits can be connected to form a two-layer integrated circuit. To provide a carrier tape for a two-layer integrated circuit, which can shorten the length of the tape by half, reduce the mounting space to less than half, and enable further integration, and a method for manufacturing the same. .

The present invention will be explained below by means of illustrated embodiments.

Describing the manufacturing process in order, 1 in the figure is a long tape material for carriers, and it has a thickness that is insulating.
It is made of a polyimide film of about 125 μm, and an adhesive is applied to its upper surface to form an adhesive layer 2 as shown in FIG. Next, on this tape material 1 with adhesive layer 2,
As shown in FIG. 3, a large number of device holes 3 are formed in the center by punching at equal intervals, and
Sprocket holes 4 near both sides of tape material 1
A large number of them are formed at equal intervals (see Fig. 9). Next, on the adhesive layer 2 near the center of the tape material 1, excluding the edges near both sides, a conductive layer for forming leads is applied.
A copper foil layer 5 of about 25 μm is laminated to form a copper foil layer 5 as shown in FIG. Then, from the bottom of the tape material 1,
Silver paint is printed on the lower surface of the copper foil layer 5 through the device hole 3 to a thickness of about 35 μm as a conductive paint for connection to form a silver paint layer 6 as shown in FIG. Then, an adhesive is applied to the remaining lower surface to form an adhesive layer 7, and a copper foil is laminated as a conductive layer for lead formation on the adhesive layer 7 on the lower surface in the same manner as above, as shown in FIG. A copper foil layer 8 is formed. Next, a photosensitive liquid is applied to the copper foil layers 5 and 8 on both the upper and lower surfaces of the tape material 1, and a desired lead pattern is printed on each layer and developed. Thereafter, through etching and peeling steps, desired leads 9 and 10 made of copper are formed on both the upper and lower surfaces as shown in FIGS. 7 and 9. At this time, in the leads 9 and 10,
The portion where the silver paint layer 6 is formed through the device hole 3 as described above has an outer lead portion 9a whose top and bottom are connected to each other by the silver paint layer 6.
It becomes 10a. On the other hand, the portions of the leads 9 and 10 with the tape material 1 in between become inner lead portions 9b and 10b whose top and bottom are insulated.

And upper and lower inner lead parts 9b, 10b
It is sufficient to apply silver plating to the bonding portions of each, thereby completing the carrier tape A for dual integrated circuits as shown in FIG.

After that, IC chips 11 and 12 with gold bumps are brought into contact with the silver-plated parts of the inner lead parts 9b and 10b on the upper and lower sides of the tape A, and inner bonding is performed by thermocompression bonding as shown in FIG. Chips 11 and 12 are subjected to a characteristic test while assembled in tape A. Next, moldings 13 and 14 are applied to each chip 11 and 12, and the outer lead portions 9a and 10 of the adjacent integrated circuits are pressed using a press.
A is divided into front and rear parts as shown by the two-dot chain line l in FIG. 8, and unnecessary parts of tape A are cut off, thereby completing a two-layer integrated circuit B as shown in FIG. 10. After that, outer bonding can be performed at a predetermined position on the printed circuit board using the outer lead parts 9a and 10a.

In the above configuration, polyimide is used as the tape material 1, but it is not limited thereto, and may be made of polyester, glass fiber, or other insulating film-like material. Further, in the above embodiment, an adhesive was applied to one side of the tape material and the copper foil was laminated thereon, but it is also possible to laminate the copper foil directly on one side of the tape material. Furthermore, the conductive layers 5 and 8 for forming leads are not limited to copper, and may be made of gold, tin, aluminum, etc., and the conductive paint 6 for connection is not necessarily limited to silver paint. Of course, the thicknesses of the tape material 1, the conductive layers 5 and 8, and the conductive paint 6 described above are merely examples.

As is clear from the above, the present invention has the following effects.

[B] It is possible to easily manufacture a two-layer integrated circuit in which two integrated circuits such as ICs and LSIs are layered with an insulating material in between. That is, in the present invention, leads are formed on both the upper and lower sides of a carrier tape for bonding, the inner lead portion is insulated via the tape, and the outer lead portion is connected with conductive paint. It's like this. Therefore, two different types of integrated circuit chips can be bonded to the inner lead portions on the upper and lower surfaces, and the upper and lower outer lead portions are connected, making it easy to create a two-layer integrated circuit.
It can be manufactured quickly and automatically.

[B] The length of carrier tape for bonding can be shortened to one half. That is, in the conventional carrier tape method, in order to incorporate two integrated circuit chips, a length of two carrier tapes is naturally required. In contrast, in the present invention,
Since two chips can be incorporated in the upper and lower parts of the tape in a two-layered manner, the length of the carrier tape is sufficient for one chip, which is highly economical.

[C] Furthermore, in a two-layer integrated circuit manufactured using this carrier tape, the mounting space can be reduced to one-half or less. That is, in the case of conventional integrated circuit chips, in order to mount the two chips on a printed circuit board, a space corresponding to the space for the two chips is naturally required for wiring. On the other hand, since the integrated circuit using the tape of the present invention is a two-layer type, only one mounting space is required on a printed circuit board, etc., and since the leads are directly connected, There is also no need for space for Therefore, compared to conventional integrated circuit mounting, less than half the space is required, and in this respect, the degree of integration can be further improved.

[Brief explanation of drawings]

The drawings are conceptual diagrams showing an embodiment of the present invention, in which Figs. 1 to 8 are enlarged longitudinal sectional side views at each stage of the manufacturing process, Fig. 9 is a perspective view of a part of the carrier tape, FIG. 10 is an enlarged vertical sectional side view of a two-layer integrated circuit using this carrier tape. Drawing code, A...Carrier tape, 1...Tape material, 3...Device hole, 5...Conductor layer,
6... Conductive paint, 8... Conductive layer, 9, 10
...Lead, 9a, 10a...Outer lead part, 9b, 10b...Inner lead part.

Claims (1)

[Claims] 1. A large number of leads 9, 10 are arranged on both sides of an insulating carrier tape material 1, and among the leads 9, 10 on each surface, a conductive paint 6 is passed through each device hole 3. The parts connected with the wires are the outer lead parts 9a and 10a, respectively, and the parts insulated with the tape material 1 are the inner lead parts 9b and 10b, respectively.
A carrier tape for two-layer integrated circuits. 2. A conductor layer 5 for forming leads is formed on one side of an insulating carrier tape material 1 having a large number of device holes 3, and a conductive paint 6 for connection is applied to the back side of the conductor layer 5 through the device holes 3. Then, a conductor layer 8 for forming leads is formed on the other side of the tape material 1 so as to adhere to the conductive paint 6 at the device hole 3, and the conductor layers 5 and 8 on each side are photo-etched. A large number of desired leads 9, 10 are formed by forming each lead 9, 10.
10, the parts connected with the conductive paint 6 are formed on the outer lead parts 9a and 10a of each surface,
A method for manufacturing a two-layer integrated circuit carrier tape, in which a portion insulated by the remaining tape material 1 is formed as inner lead portions 9b and 10b on each side.