JPH0143454B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for heat treatment of compound semiconductors such as GaAs.

Schottky barrier field effect transistor
The use of ion implantation technology has become essential in producing devices made of GaAs, such as GaAs logic integrated circuits. However, the ion implantation technology, which is characterized by uniformity within the wafer plane and good reproducibility between wafers, has not yet reached its goal with regard to GaAs, which is a -V group compound semiconductor. This is due to the instability of the crystal itself of the GaAs substrate and further to the instability of the heat treatment after ion implantation. In particular, the thermal instability of Cr-doped semi-insulating GaAs substrate crystals is
This significantly deteriorates the reproducibility of the characteristics of the conductive layer due to ion implantation. Therefore, there is a strong need for a heat treatment method that is as unaffected by the substrate crystal as possible and that has good in-plane uniformity and reproducibility.

Conventionally, GaAs substrates are heated at high temperatures (800°C) after ion implantation.
In order _to perform heat treatment at _temperatures higher _than
There was a need to prevent external diffusion of As or Ga from GaAs at high temperatures. However, even in this method, some of the protective films act as a barrier to the diffusion of As but are not effective against Ga, or vice versa. Ta. Even if a suitable protective film, such as a Si ₃ N ₄ film, could be formed by plasma deposition, there would be a problem with the in-plane non-uniformity of the protective film, and this non-uniformity would directly affect the heat treatment of the ion-implanted layer. This will appear later as non-uniformity. Furthermore, even if a protective film with relatively good in-plane non-uniformity is obtained, it is not easy to maintain the growth apparatus completely and always stably supply a protective film of the same quality.

In order to overcome these drawbacks, the present applicant has already proposed an improved method of heat treating a substrate after ion implantation without forming a protective film in Japanese Patent Application No. 11605/1983. According to the method of this prior application,
The GaAs substrate is heat-treated in an atmosphere with an As vapor partial pressure higher than the As decomposition pressure, effectively preventing As vapor from leaving the substrate crystal. In this case, thermal decomposition of arsine (AsH ₃ ) is used to obtain the partial pressure of As. However, since arsine is a highly toxic gas, it is desirable from the standpoint of safety to avoid its use if possible.

The first invention of the present application takes these circumstances into account, and
It provides a method that is highly safe and does not require the use of conventional protective films.
A compound characterized in that InAs and a compound semiconductor (for example, GaAs) having an As vapor pressure lower than that of the InAs in an equilibrium state at a heat treatment temperature are placed in a substantially airtight space and heat treated. The present invention relates to a semiconductor heat treatment method.

A second invention of the present application also provides a first compound semiconductor (e.g., GaAs) having a group V element (e.g., As) that evaporates at a heat treatment temperature, and an amorphous region formed by ion implantation. A second compound semiconductor (for example, another GaAs) having a higher vapor pressure of the group V element than the first compound semiconductor in an equilibrium state at the heat treatment temperature is placed in a substantially airtight space and heat treated. The present invention relates to a compound semiconductor heat treatment method characterized by the following.

Furthermore, "placed in a substantially airtight space" means
This shows a case where both semiconductor substrates are in close contact with each other, or a case where they are close to each other with the periphery sealed with GaAs or the like.

Hereinafter, the invention of the present application will be described in detail with reference to examples.

Example 1 First, as shown in FIG.
A larger amount of ions were implanted than the GaAs substrate
GaAs substrates 2 are placed in close contact with each other. At this time, the substrates 2 and 1 are sequentially stacked on the quartz susceptor 5 with the ion implantation surfaces 3 and 4 brought into close contact with each other. For example, silicon is ion-implanted into the GaAs substrate 1, and it is preferable that atoms inactive in an inert gas or GaAs are ion-implanted into the opposing GaAs substrate 2. In other words, if the ion-implanted surfaces 3 and 4 of both substrates 1 and 2 are brought into close contact with each other, and ions that will become GaAs dopants are implanted into the opposing GaAs substrate 2, unnecessary ions will flow from the substrate 2 to the 1 side during heat treatment. This is because there is a risk that impurities may be introduced. For example, substrate 1 contains 1×10 ¹² silicon ions/cm ²
Krypton ions are implanted into the substrate 2 at a rate of 1×10 ¹⁶ /cm ² .

What is important here is that since the amount of ions implanted into the substrate 2 is large, the surface of the substrate 2 has more amorphous regions, which are damaged regions due to the ion implantation, than the substrate 1. Generally, the greater the amount of damage, that is, the amount of implantation, the higher the vapor pressure of As from the damaged area. The amount of damage is determined by the dose and mass of the implanted ions, so
Although the vapor pressure of As can be controlled depending on the amount and type of ion implantation, generally the As vapor pressure of the substrate 2 may be as high as it is.

Next, under these conditions, the temperature is below 950℃ (usually 800℃)
Annealing is performed by heat treatment at ~900°C (for example, 850°C) in a simple hydrogen stream. The vapor pressure of As is 600℃
Therefore, at the above heat treatment temperature,
Although As is more likely to evaporate from GaAs, the As evaporation pressure of the substrate 2 increases as described above, and the As vapor pressure of the substrate 1 is accordingly suppressed to a low level. As a result, almost no As is released from the crystal of the substrate 1, and the thermal stability of the substrate 1 can be maintained. Note that it is not desirable to make the facing surfaces of both substrates 1 and 2 mirror-finished because evaporated As will easily flow out from the facing surfaces.

When substrate 1 is doped with Cr to make it semi-insulating,
During the heat treatment described above, carriers increase and the surface of the substrate 1 becomes N-type due to thermal transformation. This is thought to be because Cr, which acts as a deep acceptor, escapes to the surface and becomes N-type, but this is disadvantageous because the conductivity of the surface increases due to N-type formation. In FIG. 2, the carrier concentration of the surface N-type layer after heat treatment is plotted as a function of depth. In the figure, curve a shows semi-insulating GaAs film with Si ₃ N ₄ as a protective film deposited by plasma deposition method.
Data is shown when the substrate was heat-treated in hydrogen at 850°C for 15 minutes, and curve b shows the data obtained when krypton ions were implanted at 1×10 ¹⁶ /cm ² according to this example.
Data is shown when a semi-insulating GaAs substrate is heat treated with two GaAs substrates facing each other. According to this, it can be seen that when processed by the method of this example, the carrier concentration due to thermal transformation is considerably reduced compared to the conventional method, and an ion-implanted layer with good reproducibility can be stably obtained.

Example 2 In this example, an InAs substrate is used as the substrate 2 in FIG. The As vapor pressure of InAs at high temperature is
The annealing temperature (800~
950°C), which is known to be about an order of magnitude higher. Therefore, if this InAs substrate is used as the counter substrate 2,
Evaporation of As from the substrate 1 can be prevented by increasing the As vapor pressure in the substrate 2 without damaging the surface of the substrate 2 by ion implantation. Therefore, unlike in Example 1, ion implantation is not necessary for the opposing substrate, and the InAs substrate can be used as is.

The invention of the present application has been described above based on examples, but
The above-described embodiments can be further modified according to the technical idea of the invention of the present application.

For example, the ions implanted into the counter substrate 2 may be H ⁺ , He ⁺ , Ne ^{+ ,} etc. in addition to Kr ⁺ . but,
As described above, when the substrate 2 is made of InAs, ion implantation is not necessary, and in any case, it is sufficient to make the As vapor pressure higher than that of the substrate 1. In this sense, the substrate 2 is not limited to - group compounds such as GaAs and InAs, but may be made of a semiconductor containing As. Furthermore, it goes without saying that the group or group elements of the substrates 1 and 2 are not limited to those mentioned above.

The heat treatment conditions can also be changed in various ways; for example, an inert carrier gas such as N ₂ or Ar can be used instead of a hydrogen stream.

Further, a plurality of sets of substrates 1 and 2 may be stacked, or the substrates 1 and 2 may be arranged vertically or diagonally.

In the above embodiment, both substrates 1 and 2 were brought into close contact with each other, but the two substrates were placed slightly apart, GaAs, etc. was arranged in a ring shape between their peripheral parts, and heat treatment was performed with a microscopic space sealed inside. You can also. In this case as well, there is a high voltage from board 2 between both boards 1 and 2.
Since As vapor pressure exists, evaporation of As from the substrate 1 is effectively prevented.

As mentioned above, in the present invention, heat treatment is performed in a space where the vapor pressure is higher than the vapor pressure of group elements such as As contained in the compound semiconductor to be heat treated, so As is removed from the compound semiconductor. It can effectively prevent the evaporation of group elements such as, and furthermore, it does not use dangerous gases for this purpose, so it is very good from a safety point of view.

Moreover, since it is not necessary to form a protective film as in the conventional method, heat treatment up to high temperatures can be performed without using expensive equipment, and the treatment can be performed with good in-plane uniformity and reproducibility.

[Brief explanation of drawings]

The drawings show examples of the invention of the present application, in which Fig. 1 is a cross-sectional view when a semiconductor substrate is heat-treated, and Fig. 2 is a graph showing a comparative distribution of carrier concentration in the depth direction after heat treatment. It is. In addition, in the symbols used in the drawings, 1, 2...
GaAs semiconductor substrate, 5...quartz susceptor.

Claims (1)

[Claims] 1. InAs and a compound semiconductor having an As vapor pressure lower than that of the InAs in an equilibrium state at the heat treatment temperature are arranged in a substantially airtight space and heat treated. A heat treatment method for compound semiconductors. 2. The method for heat treatment of a compound semiconductor according to claim 1, wherein the compound semiconductor is ion-implanted with impurities. 3. The first material containing a group V element that evaporates at the heat treatment temperature.
and a second compound having an amorphous region formed by ion implantation and having a higher vapor pressure of the group V element than the first compound semiconductor in an equilibrium state at the heat treatment temperature. 1. A method for heat treatment of a compound semiconductor, characterized in that heat treatment is performed by disposing a semiconductor and a semiconductor in a substantially airtight space. 4. The method for heat treatment of a compound semiconductor according to claim 3, wherein the first compound semiconductor has impurity ions implanted therein. 5. The method for heat treatment of a compound semiconductor according to claim 3, wherein the first and second compound semiconductors are -V group compound semiconductors. 6. A patent claim characterized in that the vapor pressure of the Group V element of the second compound semiconductor is controlled by the dose and mass of implanted ions in the ion implantation for forming the amorphous region. The method for heat treatment of a compound semiconductor according to item 3.