JPH0144015B2 - - Google Patents
Info
- Publication number
- JPH0144015B2 JPH0144015B2 JP57224572A JP22457282A JPH0144015B2 JP H0144015 B2 JPH0144015 B2 JP H0144015B2 JP 57224572 A JP57224572 A JP 57224572A JP 22457282 A JP22457282 A JP 22457282A JP H0144015 B2 JPH0144015 B2 JP H0144015B2
- Authority
- JP
- Japan
- Prior art keywords
- metal film
- semiconductor device
- insulating film
- region
- lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W20/482—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes for individual devices provided for in groups H10D8/00 - H10D48/00, e.g. for power transistors
- H10W20/484—Interconnections having extended contours, e.g. pads having mesh shape or interconnections comprising connected parallel stripes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
- H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
- H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
- H10W72/07552—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting changes in structures or sizes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/521—Structures or relative sizes of bond wires
- H10W72/527—Multiple bond wires having different sizes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/59—Bond pads specially adapted therefor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
- H10W72/884—Die-attach connectors and bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/931—Shapes of bond pads
- H10W72/934—Cross-sectional shape, i.e. in side view
Landscapes
- Wire Bonding (AREA)
Description
【発明の詳細な説明】
この発明は、半導体装置に関し、特に露出領域
に金属膜を被着し、これにリードを結合したもの
において金属膜内に絶縁膜を設けたものに関す
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which a metal film is deposited on an exposed region and a lead is connected to the semiconductor device, and an insulating film is provided within the metal film.
従来、上記の半導体装置には第１図に示すよう
なものがあつた。第１図において、１はコレクタ
領域、２はベース領域、３はエミツタ領域で、一
方の主表面４上におけるエミツダ領域３の中央に
は例えば酸化シリコン等の絶縁膜５が設けられ、
主表面４におけるエミツタ領域３と絶縁膜５とに
アルミニウム等の電極金属膜６が蒸着され、絶縁
膜５上の金属膜６にエミツタリード７が結合され
ている。なお８，９も絶縁膜、１０も金属膜、１
１はベースリード、１２は放熱板、１３は半田層
である。 Conventionally, the above-mentioned semiconductor device has been as shown in FIG. In FIG. 1, 1 is a collector region, 2 is a base region, and 3 is an emitter region. In the center of the emitter region 3 on one main surface 4, an insulating film 5 made of, for example, silicon oxide is provided.
An electrode metal film 6 such as aluminum is deposited on the emitter region 3 and the insulating film 5 on the main surface 4, and an emitter lead 7 is bonded to the metal film 6 on the insulating film 5. Note that 8 and 9 are also insulating films, 10 is also a metal film, and 1
1 is a base lead, 12 is a heat sink, and 13 is a solder layer.
このような半導体装置では、絶縁膜５を設けて
いるので、逆バイアス時にエミツタリード７の結
合部分の真下に電流が集中するのを緩和でき、逆
バイアスASO（動作安定領域）も拡大できる。し
かし、金属膜６とエミツタ領域３との境界には熱
処理によつて薄く合金属が形成されるので、強固
に結合されているが、金属膜６と絶縁膜５との境
界は単に金属膜６が絶縁膜５に付着しているだけ
であるので、エミツタリード７を金属膜６に結合
した際に、その結合部分の金属膜６が剥れること
があり、製造における歩留りが悪いという欠点が
あつた。 In such a semiconductor device, since the insulating film 5 is provided, it is possible to alleviate the concentration of current directly under the coupling portion of the emitter lead 7 during reverse bias, and it is also possible to expand the reverse bias ASO (stable operation region). However, since a thin alloy metal is formed at the boundary between the metal film 6 and the emitter region 3 by heat treatment, they are strongly bonded, but the boundary between the metal film 6 and the insulating film 5 is simply formed by the metal film 6. Since the emitter lead 7 is only attached to the insulating film 5, when the emitter lead 7 is bonded to the metal film 6, the metal film 6 at the bonded portion may peel off, resulting in a disadvantage of poor manufacturing yield. .
この発明は、逆バイアスASOを拡大できると
共に歩留りを向上させた半導体装置を提供するこ
とを目的とする。 An object of the present invention is to provide a semiconductor device that can expand reverse bias ASO and improve yield.
以下、この考案を第２図乃至第４図に示す１実
施例に基づいて説明する。この実施例は第２図に
示すようにエミツタ領域３の主表面４上に小さな
間隙１５をおいて小絶縁膜群１６を設けたもので
ある。これら小絶縁膜１６はエミツタリード７の
結合位置の真下に設けられており、それぞれ従来
の絶縁膜５よりも幅寸法を小さくしたもので、第
３図乃至第５図に示すようにスリツト状１６ａ、
点状１６ｂまたは網状１６ｃに構成したものであ
る。そして小絶縁膜群１６間の各間隔１５には金
属膜６が侵入している。 This invention will be explained below based on one embodiment shown in FIGS. 2 to 4. In this embodiment, as shown in FIG. 2, a small insulating film group 16 is provided on the main surface 4 of the emitter region 3 with a small gap 15 therebetween. These small insulating films 16 are provided directly below the bonding position of the emitter lead 7, and have smaller width dimensions than the conventional insulating film 5. As shown in FIGS. 3 to 5, slit-shaped insulating films 16a,
It is configured in dot-like shapes 16b or net-like shapes 16c. The metal film 6 invades each interval 15 between the small insulating film groups 16.
このように構成した半導体装置では、エミツタ
リード７の真下の金属膜６内に小絶縁膜群１６を
形成しているので、逆バイアスASOを拡大する
ことができ、しかも各小絶縁膜群１６間の間隔１
５に侵入した金属膜６とエミツタ領域３との境界
には熱処理によつて薄く合金層が形成され、両者
は強固に結合されるので、エミツタリード７を金
属膜６に結合した際にその結合部分の金属膜６が
剥れることがなく、製造時における歩留りを向上
させることができる。 In the semiconductor device configured in this way, since the small insulating film group 16 is formed in the metal film 6 directly under the emitter lead 7, the reverse bias ASO can be expanded, and moreover, the small insulating film group 16 between each small insulating film group 16 is Interval 1
A thin alloy layer is formed by heat treatment on the boundary between the metal film 6 that has penetrated into the metal film 5 and the emitter region 3, and the two are firmly bonded, so that when the emitter lead 7 is bonded to the metal film 6, the bonded portion The metal film 6 does not peel off, and the yield during manufacturing can be improved.
上記の実施例ではNPNのトランジスタのエミ
ツタ領域にこの考案を実施したが、PNPのトラ
ンジスタのエミツタ領域にも実施できるし、サイ
リスタのカソード領域にも実施できる。さらに小
絶縁膜群１６の点状のもの１６ｂはそれぞれ平面
形状を矩形としたが、円形のものとしてもよい。 In the above embodiment, this invention was implemented in the emitter region of an NPN transistor, but it can also be implemented in the emitter region of a PNP transistor, and also in the cathode region of a thyristor. Furthermore, although the dots 16b of the small insulating film group 16 each have a rectangular planar shape, they may also be circular.
第１図は従来の半導体装置の縦断面図、第２図
はこの発明による半導体装置の縦断面図、第３図
乃至第５図はそれぞれ同半導体装置に用いる小絶
縁膜群の平面図である。
３……領域、４……一表面、６……電極金属
膜、７……リード、１６……小絶縁膜群。
FIG. 1 is a longitudinal sectional view of a conventional semiconductor device, FIG. 2 is a longitudinal sectional view of a semiconductor device according to the present invention, and FIGS. 3 to 5 are plan views of a group of small insulating films used in the semiconductor device. . 3...Region, 4...One surface, 6...Electrode metal film, 7...Lead, 16...Small insulating film group.
Claims (1)
の領域を有し、この各領域上にそれぞれ電極金属
膜を被着した半導体装置において少くとも一部の
上記電極金属膜と上記半導体との間に、複数に分
断された絶縁膜群を介在させ、当該電極金属膜に
対するリードを上記分断された絶縁膜群の真上に
おいて結合したことを特徴とする半導体装置。1. In a semiconductor device having a plurality of regions having different conductivity types on one surface of a semiconductor, and having an electrode metal film deposited on each region, at least a portion of the electrode metal film and the semiconductor A semiconductor device characterized in that a group of insulating films divided into a plurality of parts is interposed therebetween, and a lead for the electrode metal film is connected directly above the group of divided insulating films.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57224572A JPS59113655A (en) | 1982-12-20 | 1982-12-20 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57224572A JPS59113655A (en) | 1982-12-20 | 1982-12-20 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59113655A JPS59113655A (en) | 1984-06-30 |
| JPH0144015B2 true JPH0144015B2 (en) | 1989-09-25 |
Family
ID=16815853
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57224572A Granted JPS59113655A (en) | 1982-12-20 | 1982-12-20 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59113655A (en) |
-
1982
- 1982-12-20 JP JP57224572A patent/JPS59113655A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59113655A (en) | 1984-06-30 |
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