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JPH0144052B2 - - Google Patents
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JPH0144052B2 - - Google Patents

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Publication number
JPH0144052B2
JPH0144052B2 JP58110327A JP11032783A JPH0144052B2 JP H0144052 B2 JPH0144052 B2 JP H0144052B2 JP 58110327 A JP58110327 A JP 58110327A JP 11032783 A JP11032783 A JP 11032783A JP H0144052 B2 JPH0144052 B2 JP H0144052B2
Authority
JP
Japan
Prior art keywords
characteristic
analog
digital
bit
law
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP58110327A
Other languages
Japanese (ja)
Other versions
JPS6029037A (en
Inventor
Shigeru Kawada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP11032783A priority Critical patent/JPS6029037A/en
Publication of JPS6029037A publication Critical patent/JPS6029037A/en
Publication of JPH0144052B2 publication Critical patent/JPH0144052B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12Analogue/digital converters
    • H03M1/34Analogue value compared with reference values
    • H03M1/38Analogue value compared with reference values sequentially only, e.g. successive approximation type

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)

Description

【発明の詳細な説明】[Detailed description of the invention]

本発明は非直線アナログ・デイジタル変換器に
関するもので、特にμ法則またはA法則に基づく
折線型圧縮デイジタル信号を選択して出力できる
利点を有するものである。 音声信号などのように小振幅の生起確率が高く
大振幅の生起確率の低い信号に対しては、均一量
子化を行う直線アナログ・デイジタル変換方式は
効率的でないので、大振幅は相対的に粗く、小振
幅を相対的に細かく量子化する、すなわち、入力
振幅に応じて量子化ステツプを変える非直線アナ
ログ・デイジタル変換方式が用いられることは周
知である。非直線量子化の一つの方法には、入力
信号をまず圧縮器を通して圧縮し、その後で均一
量子化することによつて、実質的に非直線量子化
信号を得るものがあり、音声用パルス符号変調通
信方式(音声用PCM)では、対数関数に従つて
圧縮した入力アナログ信号を、更に15個または13
個の折線(セグメント)で近似した後均一量子化
して得た非直線量子化信号が用いられる。通常前
者は15折線μ法則に基づいた量子化方式また後者
は13折線A法則に基づいた量子化方式と呼ばれ、
何れも国際電信電話諮問委員会(CCITT)の勧
告に基づく国際規格の非直線アナログ・デイジタ
ル変換方式である。従つて、以下前者を単にμ法
則による変換、また後者をA法則による変換と略
称する。ここでμまたはAは入力信号の圧縮率に
関係する数値で、この値が大きい程圧縮率は大き
く、μ法則による変換およびA法則による変換に
おけるμおよびAは、それぞれ255および87.6で
ある。受信側では、均一量子化復号器の後に圧縮
器の非直線特性とは逆の特性をもつ伸張器を通せ
ば、元の信号に復調できるので、圧縮、伸張を総
称して圧伸と言われている。ここでこの用語を用
いると、上記μ法則(μ=255)またはA法則
(A=87.6)による圧伸特性F(x)はそれぞれ式
(1)および(2)で与えられる。 F(x)=sgn(x)ln(1+μ|x|)/ln(1+μ
)(1) F(x)=sgn(x)A|x|/1+lnA、(|x|1/
A) =sgn(x)1+lnA|x|/1+lnA、(1/A|x|
1) (2) ただし、μ=255、A=87.6、またはsgn(x)
は入力アナログ信号xの正負の極性を示す。 第1図a,bおよび第2図a,bは、μ法則に
よる変換およびA法則による変換における、それ
ぞれのアナログ信号とデイジタル信号との関係を
示す図で、図aには送信側が、また図bには受信
側がそれぞれ8ビツトのデイジタル・コードを用
いて示されている。第1図a,bのμ法則による
変換では、μ特性(μ=255)に従う圧縮特性を
正負合わせて15個の折線(セグメント)で近似
し、第2図a,bのA法則による変換では、A特
性(A=87.6)に従う圧縮特性を、原点に近い正
負4区間を長い一本の折線(セグメント)とする
ことによつて、正負合わせた13個の折線(セグメ
ント)で近似する。従つて、μ特性またはA特性
線上にある各折線(セグメント)の接点は、当然
それぞれの圧縮特性を満たす。ここで、これら2
つの変換則による折線特性を比較すると、相隣る
折線(セグメント)内の量子化ステツプの比は何
れも2に等しいが、量子化ステツプそのもので
は、一方のμ法則による変換が2、4、8、16、
32、64、128および256となるのに対して、他方の
A法則による変換の場合では2、2、4、8、
16、32、64および128となるので、入力アナログ
信号xの小振幅および大振幅付近における違いは
可成り大きい。ところで、何れの変換則による場
合であつても、1個の極性ビツトSと7個の信号
ビツトe1、e2、e3、e4、e5、e6、e7の8ビツトか
ら成る量子化信号は、最初の極性ビツトSを除く
つぎの3ビツトe1、e2、e3が標本値の入る折線領
域を示し、後の4ビツトe4、e5、e6、e7がその折
線内の量子化ステツプで何番目の刻みにあるかを
示しているので、入力アナログ信号xの小振幅お
よび大振幅付近における量子化コード間のレベル
差も可成り大きくなる。しかしながら、これら2
つの変換則間に現われる最も著しい違いは、この
量子化信号の出力コードの構成内容である。すな
わち、CCITTの勧告に基づく国際規格によれば、
μ法則による変換では、標本値のフルスケール値
は“0000000”でコード化され、且つこの量子化
コードがそのまま出力コードとして送信されるの
に対し、他方のA法則による変換では、標本値の
フルスケール値は“1111111”でコード化され、
更に極性ビツトSを含む8ビツトの量子化コード
について、偶数番目のビツト符号をそれぞれ反転
したものを出力コードとするよう規定されてい
る。従つてこれら2つの変換則におけるデイジタ
ル変換出力コード間には、著しい相違が見られる
ようになる。ただし技術的本質の面からは、フル
スケール値に何れのコードを用いるかの選択は任
意であるから、第2図a,bのように、標本値の
フルスケール値をμ法則による変換と同じく、
“0000000”でコード化した場合のA法則による変
換のデイジタル変換出力コードは、極性ビツトS
を含む8ビツトの量子化コードについて、第3、
第5および第7の奇数番目に位置するビツト符号
をそれぞれ反転させたものである。すなわち、第
2図aの縦軸および図bの横軸には、デイジタル
変換出力コードと共に、ビツト反転されない前の
量子化コードが、それぞれカツコ内に示されてい
る。 次表は、上記第1図a,bおよび第2図a,b
に基づき、フルスケール値を共に“0000000”で
コード化した場合の、μ法則による変換およびA
法則による変換のデイジタル変換出力コードを、
レベルとは関係なく一覧にとりまとめたものであ
る。ただし、標本値の正側のみを表示した。
The present invention relates to a nonlinear analog-to-digital converter, and particularly has the advantage of being able to select and output a polygonal compressed digital signal based on the μ-law or the A-law. For signals such as audio signals, where the probability of occurrence of small amplitudes is high and the probability of occurrence of large amplitudes is low, the linear analog-to-digital conversion method that performs uniform quantization is not efficient, so large amplitudes are relatively coarse. It is well known that a nonlinear analog-to-digital conversion method is used in which small amplitudes are quantized relatively finely, that is, the quantization step is changed depending on the input amplitude. One method of non-linear quantization is to first compress the input signal through a compressor and then uniformly quantize it to obtain a substantially non-linear quantized signal, which is a pulse code for speech. In the modulation communication method (PCM for audio), the input analog signal compressed according to a logarithmic function is further compressed by 15 or 13
A non-linear quantized signal obtained by uniformly quantizing after approximation using polygonal lines (segments) is used. The former is usually called a quantization method based on the 15-fold μ law, and the latter is called a quantization method based on the 13-fold A law.
Both are international standard non-linear analog-to-digital conversion methods based on the recommendations of the Consultative Committee on International Telegraph and Telephones (CCITT). Therefore, hereinafter, the former will be simply referred to as conversion based on the μ-law, and the latter will be simply referred to as conversion based on the A-law. Here, μ or A is a numerical value related to the compression ratio of the input signal, and the larger the value, the higher the compression ratio. μ and A in the μ-law conversion and A-law conversion are 255 and 87.6, respectively. On the receiving side, the original signal can be demodulated by passing the uniform quantization decoder through a decompressor whose nonlinear characteristics are opposite to those of the compressor. Compression and decompression are collectively called companding. ing. When this term is used here, the companding characteristic F(x) according to the above μ law (μ = 255) or A law (A = 87.6) is expressed by the formula
Given by (1) and (2). F(x)=sgn(x)ln(1+μ|x|)/ln(1+μ
)(1) F(x)=sgn(x)A|x|/1+lnA, (|x|1/
A) =sgn(x)1+lnA|x|/1+lnA, (1/A|x|
1) (2) However, μ=255, A=87.6, or sgn(x)
indicates the positive and negative polarities of the input analog signal x. Figures 1a and 2b and 2a and 2b are diagrams showing the relationship between analog signals and digital signals in μ-law conversion and A-law conversion, respectively. In b, the receiving side is shown using an 8-bit digital code each. In the conversion using the μ-law shown in Figures 1a and b, the compression characteristics according to the μ characteristic (μ = 255) are approximated by 15 broken lines (segments), including the positive and negative values, and in the conversion using the A-law shown in Figures 2a and b, , the compression characteristic according to the A characteristic (A=87.6) is approximated by 13 polygonal lines (segments) including the positive and negative by making the four positive and negative sections near the origin into one long polygonal line (segment). Therefore, the contact points of each broken line (segment) on the μ-characteristic or A-characteristic line naturally satisfy the respective compression characteristics. Here, these two
Comparing the polygonal line characteristics according to the two transformation rules, the ratio of the quantization steps in adjacent polygonal lines (segments) is all equal to 2, but when it comes to the quantization steps themselves, the transformation according to one of the μ-laws is 2, 4, and 8. ,16,
32, 64, 128, and 256, whereas in the case of the conversion according to the other A law, 2, 2, 4, 8,
16, 32, 64, and 128, so the difference near the small amplitude and large amplitude of the input analog signal x is quite large. By the way, no matter which conversion rule is used, it consists of 8 bits: one polarity bit S and seven signal bits e 1 , e 2 , e 3 , e 4 , e 5 , e 6 , e 7. In the quantized signal, the next 3 bits e 1 , e 2 , e 3 excluding the first polarity bit S indicate a polygonal region where the sample value is included, and the latter 4 bits e 4 , e 5 , e 6 , e 7 Since it indicates the number of quantization steps within the broken line, the level difference between the quantization codes near the small amplitude and large amplitude of the input analog signal x is also quite large. However, these two
The most significant difference between the two conversion rules is the content of the output code of this quantized signal. In other words, according to international standards based on CCITT recommendations:
In the μ-law conversion, the full-scale value of the sample value is encoded as “0000000” and this quantization code is sent as an output code, whereas in the A-law conversion, the full-scale value of the sample value is The scale value is coded as “1111111”,
Further, for an 8-bit quantized code including the polarity bit S, it is specified that the output code is obtained by inverting the even-numbered bit codes. Therefore, there will be a significant difference between the digital conversion output codes under these two conversion rules. However, from the technical point of view, the selection of which code to use for the full-scale value is arbitrary, so as shown in Figure 2 a and b, the full-scale value of the sample value can be converted in the same way as the μ-law conversion. ,
The digital conversion output code of the A-law conversion when encoded with “0000000” is the polarity bit S.
For an 8-bit quantization code containing
The codes of the fifth and seventh odd-numbered bits are respectively inverted. That is, on the vertical axis of FIG. 2a and the horizontal axis of FIG. 2b, the quantized code before bit inversion is shown in brackets together with the digital conversion output code. The following table shows the above figures 1 a, b and 2 a, b.
Based on the μ-law conversion and A when both full-scale values are encoded as “0000000”,
The digital conversion output code of the conversion according to the law,
It is compiled into a list regardless of level. However, only the positive side of the sample value was displayed.

【表】【table】

Claims (1)

【特許請求の範囲】 1 逐次近似レジスタとμ特性またはA特性の圧
縮特性を有するデイジタル・アナログ変換器とを
備える逐次比較型アナログ・デイジタル変換回路
と、前記逐次近似レジスタの極性ビツト最終格納
段を除く各段のマスター段とスレーブ段間に前記
デイジタル・アナログ変換器の圧縮特性がμ特性
またはA特性に設定される場合にそれぞれ対応し
て選択的に接続挿入されるビツト符号反転回路と
を含み、前記逐次比較型アナログ・デイジタル変
換回路は前記逐次近似レジスタのマスター段にそ
れぞれ1ビツトづつ格納されるμ法則またはA法
則によるアナログ・デイジタル変換コードのビツ
ト符号を前記ビツト符号反転回路を介し先頭の極
性ビツトを除き奇数番目または偶数番目において
それぞれ一斉反転して出力することを特徴とする
非直線アナログ・デイジタル変換器。 2 前記デイジタル・アナログ変換器の圧縮特性
をμ特性に設定する重みづけ抵抗のステツプ量子
化回路と、前記量子化回路の最小ステツプに対応
する重みづけ抵抗の両端に該重みづけ抵抗と同一
抵抗値の抵抗素子を並列挿入して該圧縮特性をA
特性に切換える機械的スイツチ手段とを備えるこ
とを特徴とする特許請求の範囲第1項記載の非直
線アナログ・デイジタル変換器。
[Scope of Claims] 1. A successive approximation type analog-to-digital conversion circuit comprising a successive approximation register and a digital-to-analog converter having μ-characteristic or A-characteristic compression characteristics, and a polarity bit final storage stage of the successive approximation register. A bit sign inversion circuit is selectively connected and inserted between the master stage and slave stage of each stage except for when the compression characteristic of the digital-to-analog converter is set to μ characteristic or A characteristic. , the successive approximation type analog-to-digital conversion circuit converts the bit sign of the μ-law or A-law analog-to-digital conversion code, which is stored in the master stage of the successive approximation register one bit at a time, through the bit sign inversion circuit to the first one. A non-linear analog-to-digital converter characterized in that the odd or even bits are simultaneously inverted and output except for the polarity bit. 2. A step quantization circuit of a weighting resistor that sets the compression characteristic of the digital-to-analog converter to μ characteristic, and a weighting resistor corresponding to the minimum step of the quantizing circuit having a resistance value the same as that of the weighting resistor at both ends thereof. resistance elements are inserted in parallel to make the compression characteristic A
2. A nonlinear analog-to-digital converter according to claim 1, further comprising mechanical switching means for switching characteristics.
JP11032783A 1983-06-20 1983-06-20 Non-linear analog/digital converter Granted JPS6029037A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11032783A JPS6029037A (en) 1983-06-20 1983-06-20 Non-linear analog/digital converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11032783A JPS6029037A (en) 1983-06-20 1983-06-20 Non-linear analog/digital converter

Publications (2)

Publication Number Publication Date
JPS6029037A JPS6029037A (en) 1985-02-14
JPH0144052B2 true JPH0144052B2 (en) 1989-09-25

Family

ID=14532917

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11032783A Granted JPS6029037A (en) 1983-06-20 1983-06-20 Non-linear analog/digital converter

Country Status (1)

Country Link
JP (1) JPS6029037A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61139030U (en) * 1985-02-16 1986-08-28

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5544256A (en) * 1978-09-22 1980-03-28 Komatsu Ltd Programmable a-d converter
JPS55130226A (en) * 1979-03-29 1980-10-08 Fujitsu Ltd Voltage division circuit

Also Published As

Publication number Publication date
JPS6029037A (en) 1985-02-14

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