JPH0145670B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a signal input circuit that detects a change in an input signal and stores the state of the change.

[Background technology]

FIG. 1 shows a conventional circuit, which includes a noise removal circuit 6 consisting of two stages of D flip-flops 1 and 2, NOR gates 3 and 4, and an RS flip-flop 5;
It is composed of a change detection circuit 9 consisting of a flip-flop 7 and an exclusive OR circuit 8, and an SR latch 10. An input signal is input to the D input terminal of the D flip-flop 1 in the first stage of the noise removal circuit 6, and the SR latch 10 A changing data signal is output from the Q output terminal of each D flip-flop, and a sample clock signal is input to the clock input terminal CK of each D flip-flop 1, 2, and 7, and a power-on reset signal is input to the reset input terminal R of each D flip-flop. It is designed so that it will be done.
Figure 2 shows a time chart of the circuit in Figure 1, in which a is the power-on reset signal POC, b is the sample clock signal, c is the input signal, and d is the first D
Q output of flip-flop 1, e is Q output of second D flip-flop 2, f is noise removal circuit 6
, g is the Q output of the D flip-flop 7 of the change detection circuit 9, h is the output of the exclusive OR circuit 8, i
indicates a changing data signal which is the Q output of SR latch 10. By the way, the time chart in Figure 2 shows the operation of the circuit in Figure 1 when the input signal is "H" when the circuit is powered on. As shown, when the power is turned on, all D flip-flops 1,
Even though 2 and 7 have been reset, even if the input signal is "H" when the power is turned on, a change will be erroneously detected and the changed data signal will be "H".
This has the problem of causing malfunctions, and even if the D flip-flops 1, 2, and 7 are set when the power is turned on, the same problem occurs if the input signal is "L" at this time. This has the problem that a change is detected and a changed data signal is output.

Therefore, in the conventional example circuit as shown in Fig. 1,
Depending on the state of the input signal, a changing data signal may be output incorrectly immediately after the power is turned on, even though there is actually no change in the input signal. In a system that is monitored and controlled from an operation panel, signals from these terminals are input to the main operation panel via the signal input circuit shown in Figure 1, and changes occur in the input signals from the terminals. If the main operation panel is configured to receive interrupts, a large number of interrupts will occur when the power is turned on, and the processing of these interrupts will take a long time, impeding the functions of the main operation panel.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a signal input circuit that can prevent erroneous change detection outputs from occurring immediately after power is turned on, and can always provide stable change detection outputs.

[Disclosure of the invention]

(Embodiment) FIG. 3 shows a circuit diagram of an embodiment of the present invention. In the conventional example shown in FIG. , a reset circuit 13 consisting of a 3-bit counter 11 and an RS flip-flop 12 is provided.The sample clock signal is input to the CK terminal of the counter 11, and its Q3 output is input to the reset input terminal of the RS flip-flop 12. , the power-on reset signal is connected to the R terminal of the counter 11 and the RS flip-flop 1.
2 is input to the set input terminal, and the Q output of this RS flip-flop 12 is input to the reset input terminal of the SR latch 10.

(Operation) FIG. 4 shows a time chart of the embodiment of FIG. 3, in which a is a power-on reset signal, b is a sample clock signal, c is an input signal, and d is the first D
Q output of flip-flop 1, q is Q output of second D flip-flop 2, f is noise removal circuit 6
, g is the Q output of the D flip-flop 7 of the change detection circuit 9, h is the output of the exclusive OR circuit 8, i
is the output of the counter 11, j is the output of the reset circuit 13, and k is the change data signal. As is clear from FIG. 4, even if the input signal is "H" when the power is turned on, the time in FIG. 4 at which this input state is captured and the change point detection pulse is output is The time up to the timing t ₀ is at most three periods of the sample clock signal. Therefore, in the embodiment shown in FIG. 3, the output SR latch 10 is forcibly reset for a period of time corresponding to three cycles of this sample clock signal. It is designed so that no output is generated. That is, in the reset circuit 13, the RS flip-flop 12 is activated by the power-on reset signal.
and resets the counter 11. After that, this counter 11 counts the sample clock signal, and when this counter 11 counts up, the above-mentioned RS flip-flop 12
When the RS flip-flop 12 is in the set state, the SR latch 10 is forcibly reset by its Q output. Therefore, the sample clock signal 4
The reset is canceled at the second time, and a changed data signal is output only when the input signal changes.

〔Effect of the invention〕

As described above, the present invention has a counter that counts an appropriate number of sample clock signals, and the period from when the power is turned on until the counter counts up.
Since it is equipped with a reset circuit that forcibly resets the SR latch, there will be no erroneous change detection immediately after the power is turned on, regardless of the state of the input signal, and stable change detection will always be possible. This has the effect of making it possible.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a conventional example, FIG. 2 is a time chart of the same as above, and FIG. 3 is a circuit diagram of an embodiment of the present invention.
Figure 4 is the same time chart as above, 1 and 2 are D flip-flops, 6 is a noise removal circuit,
7 is a D flip-flop, 8 is an exclusive OR circuit,
9 is a change detection circuit, 10 is an SR latch, 11 is a counter, and 13 is a reset circuit.

Claims (1)

[Claims] 1. A noise removal circuit having one or more stages of D flip-flops, a change detection circuit consisting of another D flip-flop and an exclusive OR circuit, which receives the output of the noise removal circuit, and latches the output of this change detection circuit to detect changes. SR that outputs data signals
The signal input circuit has a latch and inputs a sample clock signal to the clock input terminal of each of the D flip-flops. A signal input circuit comprising a reset circuit for forcibly resetting the SR latch until the counter counts up.