JPH0779317B2 - Alarm detection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] In a communication system, an alarm detection circuit for detecting a randomly generated alarm signal and resetting the detection state by a reset signal of a constant cycle, the timing of which coincides with the reset signal, Moreover, with the purpose of being able to reliably detect any alarm signal such as an alarm signal within its pulse width, a randomly generated alarm signal is used as the clock input.
A flip-flop, a second flip-flop that latches the output of the first flip-flop and outputs a latch signal as an alarm detection signal based on a reset signal of a constant cycle, and an alarm signal is input after the first flip-flop is cleared Until the reset signal for the first flip-flop is inhibited and the alarm signal is input before the timing of generation of the reset signal.
And circuit means for validating the reset signal to the flip-flop.

[Industrial application field]

The present invention, in a communication system, detects an alarm signal randomly generated due to noise intrusion into the transmission system,
In addition, the present invention relates to an alarm detection circuit that resets its detection state with a reset signal having a constant cycle.

[Conventional technology]

 FIG. 3 is a block diagram of a conventional alarm detection circuit.

In FIG. 3, a + V voltage is applied to the input terminal D of the delay-type first flip-flop 31. Further, the clock terminal CK is connected to the clock input terminal 32 to which the alarm signal AS _IN randomly generated from the communication system is applied, and the clear terminal CLR of the first flip-flop 31 is connected via the NOT gate 33 for a fixed period. The input terminal 34 to which the reset signal RS is applied is connected. The Q output terminal of the first flip-flop 31 is connected to the input terminal D of the second flip-flop 35, and its clock terminal CLK is connected to the reset signal input terminal 34. The Q output of the second flip-flop 35 is connected to the alarm output terminal 36.

Next, the operation of the conventional alarm detection circuit configured as described above will be described with reference to the time chart shown in FIG.

When the reset signal RS having a constant cycle shown in FIG. 4 (a) is input to the reset signal input terminal 33, the clear terminal CLR of the first flip-flop 31 is inverted by the NOT gate 33, as shown in FIG. 4 (b). ) Is added to the reset signal RS '.

On the other hand, when the alarm signal AS _IN is applied to the clock terminal CK through the input terminal 32 at the timing shown by AS _IN1 in FIG. 4 (c), the input from the input terminal D latched by the first flip-flop 31 is input. Is transmitted from the Q output. FIG. 4 (d) shows the state of the latch output at this time, which continues from the rising time of the alarm signal AS _{IN1 to} the falling time of the next inverted RS 'of the reset signal RS. The latch output output from the first flip-flop 31 is latched by the second flip-flop 35, and is output from the Q signal terminal to the output terminal 36 when the next reset signal RS is applied to the clock terminal CK. FIG. 4E shows the detected alarm signal AS _OUT with _respect to the alarm signal AS _IN1 at this time. Then, the output state of the second flip-flop 35 is further reset by the next reset signal RS.

On the other hand, even if the alarm signal AS _IN2 generated within the pulse width of the reset signal RS is input to the clock terminal CK of the first flip-flop 31 as shown in FIG. Since it has been reset by the reset signal RS 'shown in FIG. 7B, the detection with respect to the alarm signal AS _IN2 becomes impossible.

[Problems to be Solved by the Invention]

As described above, in the alarm detection circuit, in order to detect an alarm signal that is generally generated at random, it is necessary to latch using a latch circuit and reset the latched state with a reset signal of a constant cycle. Even if an alarm signal that coincides with the signal and is within the pulse width is generated, there is a problem that this cannot be detected.

The present invention has been made in view of the above points, and an alarm detection circuit capable of reliably detecting any alarm signal such as an alarm signal whose timing coincides with that of a reset signal and is within its pulse width. The purpose is to provide.

[Means for Solving the Problems]

An alarm detection circuit according to the present invention latches an output of the first flip-flop, which receives a randomly generated alarm signal as a clock input, and latches the output of the first flip-flop, and uses the latch signal as an alarm detection signal based on a reset signal having a constant cycle. A reset signal for the second flip-flop to be output and the first flip-flop is cleared after the first flip-flop is cleared and before the alarm signal is input, and the alarm signal is output before the generation timing of the reset signal. And circuit means for validating the reset signal to the first flip-flop when input.

[Action]

When an alarm signal whose timing coincides with that of the reset signal is input to the first flip-flop, the circuit means sets all the reset signals for the first flip-flop to the inhibit state to enable detection for the alarm signal, and When the alarm signal is input before the generation timing, the reset signal for the first flip-flop is validated. Therefore, it is possible to detect any alarm signal.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1 and 2.

FIG. 1 is a block diagram of an alarm circuit according to the present invention, in which delay type first and second flip-flops 11 and 12 are provided.
And the Q output terminal of the first flip-flop 11 and the input terminal D of the second flip-flop 12 are directly connected. A voltage of + 5V is supplied to the input terminal D of the first flip-flop 11, and the clock terminal CK is connected to the clock input terminal 13. Clear terminal of the first flip-flop 11
In the CLR, one input of the NAND gate 14 is connected to the reset signal input terminal 15, and the other input is connected to the output terminal of the first flip-flop 11 via the NOT gate 16.

The clock terminal CK of the second flip-flop 12 is connected to the reset signal input terminal 15, and the Q output terminal has an output terminal 17
It is connected to the.

Next, the operation of this embodiment configured as described above will be described with reference to the time chart of FIG.

First, the alarm signal AS randomly generated from the communication system is input to the clock input terminal 13 as shown in FIG. 2 (c), and the reset signal input terminal 15 has a fixed cycle shown in FIG. 2 (a). The reset signal RS is input. Along with this, the first flip-flop 11 outputs the inverted output of the first flip-flop 11 and the reset signal RS from the time it is cleared at a certain time until the alarm signal AS is input.
All reset signals to the clear terminal CLR are inhibited by the NAND logic. And the first flip-flop
The reset signal RS 'to the clear terminal CLR of 11 is output as valid only when the alarm signal AS is input before the reset signal RS is input as shown in FIG. 2 (b). Therefore, as shown in FIG. 2 (c), when the alarm signal AS _IN1 which coincides with the reset signal RS and is within its pulse width is applied to the clock terminal CK of the first flip-flop 11 through the clock input terminal 13. Since the reset signal RS 'to the clear terminal CLR of the first flip-flop 11 by the reset signal RS is inhibited, the latch input of the first flip-flop 11 is sent to the Q output terminal by the alarm signal AS _IN1 in FIG. ), The reset signal RS of the next cycle is output in the reset signal input terminal 15
Until added. Then, as shown in FIG. 2 (c), when the alarm signal AS _IN2 existing between the reset signals RS is applied to the clock terminal CK of the first flip-flop 11 through the clock input terminal 13, the latch signal from the D input becomes Output from the Q output terminal as shown in FIG. 2 (d),
The output state continues until the reset signal RS of the next cycle is applied to the reset input terminal 15.

In this way, the latch signal output from the first flip-flop 11 is latched by the second flip-flop 12 and the next reset signal RS delayed by one pulse is applied to the clock terminal CK of the second flip-flop 12. And the first
The latch signal of the flip-flop 11 is output from the Q output terminal to the output terminal 17 at the timing shown in FIG. 2 (e). This becomes the detected alarm signal AS _OUT .

In this embodiment, the first flip-flop is used.
From the time when 11 is cleared at some point until the alarm signal AS is input, the clear terminal is created by the NAND logic of the output that is the inverted output of the first flip-flop 11 and the reset signal RS.
The reset signal RS 'for the first flip-flop 11 is inhibited only when the reset signal to the CLR is inhibited and the alarm signal AS is input before the reset signal RS is input.
Since it is configured to be effective, it is possible to reliably detect an alarm signal of any timing, for example, an alarm signal AS _IN1 input at the timing of the reset signal RS.

Needless to say, the alarm detection circuit according to the present invention is not limited to the circuit configuration shown in the above embodiment.

〔The invention's effect〕

As described above, according to the present invention, when the alarm signal whose timing coincides with that of the reset signal is input to the first flip-flop, the circuit means sets all the reset signals for the first flip-flop to the inhibit state and outputs the alarm. Since the detection signal can be detected and the reset signal for the first flip-flop is enabled when the warning signal is input before the generation timing of the reset signal, it is possible to reliably detect any warning signal. it can.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an alarm circuit according to the present invention. FIG. 2 is a time chart for explaining the operation. FIG. 3 is a block diagram of a conventional alarm detection circuit. FIG. 4 is a time chart for explaining the operation. 11 …… First flip-flop 12 …… Second flip-flop 13 …… Clock input terminal 14 …… NAND gate 15 …… Reset signal input terminal 16 …… NOT gate.

Claims (1)

[Claims] 1. A first flip-flop having a randomly generated alarm signal as a clock input, and a second flip-flop that latches an output of the first flip-flop and outputs a latch signal as an alarm detection signal based on a reset signal of a constant cycle. A flip-flop and a reset signal for the first flip-flop, which is inhibited from being cleared until the alarm signal is input, and the alarm signal is input before the timing of generation of the reset signal An alarm detection circuit comprising: circuit means for enabling a reset signal to the first flip-flop.