JPH0145744B2 - - Google Patents

Abstract

PURPOSE:To realize inspection for junction part without giving any external force and any contact thereto and to improve inspection accuracy by selecting the inspection object to the area of junction part. CONSTITUTION:A register control signal RCS is not generated from a register control circuit and a register 72 holds ''Ax''. Thereafter, the data as many as one line is read up to mth bit by operation of a read circuit R, but ''lx'' output from a selector 53 and ''Ax'' output from the register 72 do not change. Therefore, the central processing unit CPU can read accurately the junction area data lx and junction area end data Ax in the step B7. The processing data generating path LC is capable of accurately counting only the junction areas 5 without miscounting patterns or damages of semiconductor integrated circuit element 2 even in case they are projected in black in addition to junction area 5 on the picture taken by a TV camera 20.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a joint inspection method and apparatus for inspecting the strength, etc. of a joint joined by a joining means, and particularly relates to a joint inspection method and apparatus for inspecting the strength, etc. of a joint joined by a joining means, and particularly for inspecting the strength of a joint between elements of a semiconductor integrated circuit or between the element and a post. The present invention is suitable for use in inspecting joints between the element and the lead wires, or between the posts and the lead wires when connecting with lead wires using various wire bonding devices.

For connections between semiconductor integrated circuit elements mounted on a substrate, or between the semiconductor integrated circuit elements and posts formed on the substrate, lead wires made of aluminum wire are used, and these are connected to the semiconductor integrated circuit or posts. It is widely used to perform sonic bonding. Figure 1 shows a state in which a semiconductor integrated circuit element mounted on a substrate is connected to a post, where 1 is a substrate, 2 is a semiconductor integrated circuit element mounted on the substrate 1, 3 is a post, and 4 is a post. This is a lead wire that electrically connects the semiconductor integrated circuit element 2 and the post 3. Generally, an aluminum wire is used as the lead wire 4. In this structure, the joint 5 between the semiconductor integrated circuit element 2 or the post 3 and the lead wire 4 is inspected by pulling the lead wire 4 with a predetermined force using a tensioning tool 6, and in this state, the lead wire 4 is This is done depending on whether or not to maintain the connection state. That is, by pulling with a predetermined force, if the joint of the joint portion 5 is separated, the test piece is judged as defective, and if the joint state is maintained, the test piece is passed. Note that the magnitude of this tensile force is determined through experiments and the like.

In this way, the joint 5 is inspected by applying an external force to the lead wire 4 and physically changing it, thereby applying force to the joint. As a result, the lead wire 4 may be deformed, this may cause damage, or there may be an adverse effect on the joint, which ultimately results in a decrease in yield.

FIGS. 2 and 3 are a plan view and a side view of the bonding portion 5 of the lead wire 4 by the ultrasonic wire bonding apparatus. As shown in these figures, when joining is performed by the ultrasonic method, the lead wire 4 undergoes plastic deformation. This plastically deformed portion is the joint portion 5. The maximum deformation width W of this joint portion 5 changes for each joining operation. Here, it is conventionally known that the maximum deformation width W of the joint portion 5 and the tensile strength value have a correlation. Therefore, the maximum deformation width W of the joint 5
If the strength of the joint 5 can be determined indirectly based on whether it has a predetermined width or not, the strength of the joint 5 can be determined without contact and without applying any external force to the lead wire 4. It is conceivable that the following tests can be performed. According to this, the drawbacks of the conventional ones described above can be overcome. However, the bonded portion 5 shown in FIGS. 2 and 3 shows an ideal bonded state, and the actual bonded portion 5 has various shapes. For example, as shown in FIG. 4, when the joint 5 has a shape with a protrusion 7 at its center, even if the maximum deformation width W has a predetermined width, the tensile test is not performed. When you look at it, it does not have the required tensile strength and the bond comes off.

The present invention has been made in view of the above points, and its purpose is to enable non-contact inspection of the joint without applying external force to the joint, and to improve inspection accuracy. An object of the present invention is to obtain a method and apparatus for inspecting joints that can be improved.

In order to achieve the above object, the present invention is characterized in that the inspection target is the area of a plastically deformed joint.

The inventors made numerous samples of joints, tensile tested each of them, and collected data. According to this, for a joint having a shape as shown in FIG. 2, there is a correlation between the maximum deformation width W and the tensile strength. However, it has become clear that for other unique shapes, such as the shape represented by FIG. 4, the above-mentioned correlation becomes extremely weak or disappears altogether. From this, the present inventors have found that, for example, in the one shown in FIG. It was concluded that it hardly contributes to the improvement of strength. Therefore, various studies were conducted on the joint portion 5 having an extremely protruding portion 7 in which the correlation between the deformation width W and the tensile strength is weak or not at all. As a result, such a protrusion 7
It was concluded that the area ratio is extremely small when compared to the entire area of the joint portion 5. Therefore, for each of the many samples,
The area and tensile strength of the joint were measured. Figure 5 summarizes these measurement results. The samples were prepared by ultrasonic bonding, and the conditions were as follows. In other words, the wire used
The bonding device is an ultrasonic type with a maximum oscillation output of 20
[W], made by ORTHODYNE ELECTRONICS in the United States, is for thick wire, and the wedge is made of cemented carbide and has grooves. The bonding surface is aluminum vapor-deposited film, the lead wire is aluminum 99.99 [%], thickness 300 [um],
An aluminum wire with a tensile strength of 350 [g] was used.
In FIG. 5, the vertical axis indicates the tensile strength [g] when the lead wire 4 is pulled in a direction perpendicular to the substrate 1. The horizontal axis shows the area increase rate [%]. This area increase rate [%] was calculated as follows. That is, in FIG. 6, the wire diameter of the lead wire 4 is lmini,
The width of the joint 5 is the wire diameter of the lead wire 4.
If the length of the part that is 1.2 times or more lmini is lt, and its area, that is, the area of the shaded part in the figure, is Σlx, then the area increase rate Wa is calculated by the following formula.

Wa=Σlx−lmini・lt/lmini・lt×100 [%]……(1) In this equation (1), lmini・lt is the area of the lead wire 4 per length lt, and in short, the area increase rate Wa
represents the degree of area increase after bonding in the length lt portion of the lead wire 4. length lt 1.2lmini
This is based on the premise that the characteristics of the joint 5 are concentrated in the center.

As is clear from FIG. 5, which summarizes the measurement results, there is a correlation between the tensile strength and the area increase rate Wa. According to the measurement results, the area increase rate Wa
In many cases, the bonded portion 5 peels off when the bonding area is less than 30%. In addition, when the area increase rate Wa is 30 [%] or more, most of the parts are cut off. In this cutting region, the tensile strength depends not on the strength of the joint 5 but on the strength of the plastically deformed lead wire 4 itself. Further, in a region where the area increase rate Wa is large, the tensile strength gradually decreases as the area increase rate Wa increases.

Therefore, by utilizing this relationship, the area of the joint 5 was set as the inspection target of the joint 5. In other words, the inspection passing range of the bonded portion 5 bonded under the same conditions as above is,
The area increase rate Wa of the joint portion 5 was set to 30 [%] to 55 [%]. This range differs depending on the tensile strength of the joint 5 and the yield [%], and can be varied depending on each. After the connection of the lead wire 4 is completed, the connection portion 5 is
Measure the area of , and calculate the junction increase rate Wa using equation (1). As a result, this area increase rate Wa is 30 [%]
If it falls within ~50 [%], it will be considered as passing.
In other cases, the test will be rejected.

In this way, the joint 5 can be inspected in a non-contact manner without applying any external force to the joint 5. Furthermore, according to this, a joint 5 that has an unusual shape as typified by the shape shown in FIG. 4 and does not have a predetermined tensile strength is judged to be rejected. It is possible to improve inspection accuracy. That is, as described above, the area of the protrusion 7 is small compared to the entire area of the joint 5. Therefore,
This is because the influence of the protrusion 7 is negligible when calculating the area increase rate Wa using equation (1).

The above describes the case where formula (1) is used to inspect the joint 5, but when calculating the area increase rate Wa, the entire area of the joint 5 is inspected. You can do it like this. That is, in Fig. 7, the entire area of the joint 5 is Σlx', the length of the joint 5 is lt', and the area increase rate is
Calculate Wa′ using the following formula.

Wa′＝Σlx′−lmini・lt′／lmini・lt′×100[%
]...(2) Also, W′a＝Σlx′／lmini・lt′×100[%]……(3) Furthermore, 1.2lmini・lt or
It may also be taken as the ratio of the area of the shaded area in FIG. 8 to lmini·lt. Furthermore, it may be the reciprocal of the above.

Further, when determining the inspection, the determination may be made based on the absolute value of the area of the joint portion 5. In other words, the maximum allowable area and the minimum allowable area are set in advance,
The area of the joint may be compared with these, and the quality may be determined based on whether or not the area is within this range.

In short, various judgment conditions can be considered, but the present invention is not limited to these judgment methods.

By doing the above, the inspection accuracy of the joint portion is significantly improved. Incidentally, if a further improvement in accuracy is desired, the shape of the joint is determined. That is, according to Figure 5, the area increase rate Wa
A peculiar phenomenon occurs in which the vertical tensile strength is about 160 [g] even though it is within the prescribed range. In FIG. 5, S indicates this. 9th
The figure shows the shape of the joint 5 of this product. As is clear from this figure, the left and right sides of the joint 5 are extremely unbalanced with respect to the center line C of the lead wire 4. That is, the center line C
On the other hand, the left side is hardly plastically deformed, and the right side is largely plastically deformed. Such a shape may actually occur when the lead wires 4 are joined, depending on the contact between the lead wires 4 and the tool that presses the lead wires 4 against the surface to be joined. If the joint portion 5 takes on such a shape, its tensile strength will decrease.

Therefore, in addition to the area increase rate of the joint portion 5 described above, the shape of the joint portion 5, that is, the left-right imbalance ratio (hereinafter referred to as the distortion rate) with respect to the center line C of the lead wire 4 is also determined. Do it like this. 1st
Figure 0 is a sample that was intentionally created so that the left and right sides are unbalanced with respect to the center line C of the lead wire 4.
The tensile strength [g] was measured and organized. In preparing the sample, other conditions were the same as those in FIG. 5, and the area increase rate was within the acceptable range. In FIG. 10, the vertical axis is the same as that in FIG. 5, and the horizontal axis is the strain rate Wc [%]. The distortion factor Wc was calculated as follows.
That is, in FIG. 9, the center line C of the lead wire 4 is located at a portion of the joint portion 5 whose width is 1.2 times or more the width lmini of the lead wire 4 (portion shown in perspective).
Let the area on the left side be ΣA, and the area on the right side be ΣB, and calculate it using the following formula. (ΣA<ΣB.) Wc | (1-ΣA/ΣB) | × 100 [%] ...(4) As is clear from Figure 10, even if the area increase rate is within the acceptable range. When the strain rate exceeds 25%, the tensile strength gradually decreases. Therefore, by utilizing this relationship, it was decided that the strain rate of the joint portion 5 was within 20% to pass.
Like the area increase rate, this range also varies depending on the tensile strength, yield, etc., and can be changed to various ranges depending on each. After the lead wires 4 are joined, the ΣA and ΣB of the joint portion 5 are measured or calculated, and the distortion factor Wc is calculated using equation (4). As a result, if the distortion rate Wc is within 20%, the test is considered to be a pass; otherwise, the test is a fail. Note that this determination based on the distortion rate may be performed after the determination of the area increase rate, or may be performed at a prior stage.

In this way, by adding the distortion rate to the determination conditions, inspection accuracy can be further improved.

The case where equation (4) is used in calculating the distortion rate has been described above, but as with the calculation of the area increase rate described above, various methods can be considered. for example,
This is the area ratio after subtracting the area of the lead wire 4, and the present invention is not limited to these calculation methods.

Regarding the configuration of the device, it includes an imaging means and a processing means. The joint portion is imaged by an imaging means. As is clear from the above description, the joints are extremely fine. Therefore, in order to improve accuracy, it is desirable to image the joint through a magnifying means such as a lens. Note that the enlarging means may be separate from the imaging means, and preferably, it is advantageous in terms of the configuration of the apparatus to use an imaging means equipped with an enlarging means. The imaging means is preferably one that converts the image formed on the imaging surface into an electrical signal and outputs it as video information.For example, the image formed on the imaging surface is converted to an electron beam emitted from an electron gun using a coil. Television, which uses an image pickup tube that deflects and focuses the image to extract the image as an electrical signal.
A camera or a so-called solid-state television camera in which the image pickup tube is replaced with a solid-state image pickup tube element can be used. This type of device divides the imaging surface into a large number of rows and sequentially scans each row to convert the image into an electrical signal and output it.

The processing means takes in video information from the imaging means, extracts the area of the joint from this information, and determines the quality of the joint based on the extracted joint area. It is convenient for the processing means to adopt a digital processing method from the viewpoint of its functionality. To this end, it is preferable to provide a binarizing means to binarize the video information from the imaging means, and to perform subsequent processing based on the output of this binarizing means. In processing, the output of the binarization means may be directly processed, but a storage means is provided, the binarized video information is temporarily stored in the storage means, and subsequent processing is carried out by the storage means. It is advantageous in terms of the configuration of the device to perform the process based on the contents of . A so-called microcomputer is well suited for the main part of the processing means, especially for making decisions. However, it is also possible to use other arithmetic processing means with similar functionality. In the determination processing, the arithmetic processing means may sequentially read out the stored contents from the storage means that temporarily stores the video information, that is, the video storage means. It is desirable to provide processing data creation means for creating necessary information, and to have the arithmetic processing means execute the determination based on the information from the means, in the sense that processing speed can be improved.

FIG. 11 shows an embodiment of the apparatus of the present invention, and this figure will be explained below. IP is an imaging means, and PC is a processing means. The main part of the imaging means IP is a television camera (hereinafter referred to as a TV camera). Consists of 20. In the example,
Using a solid-state image sensor as the TV camera 20,
It uses a so-called solid-state television camera. FIG. 12 shows an example of this operating principle. A solid-state image sensor is a highly integrated circuit device consisting of a large number of photo sensors PS arranged vertically and horizontally, for example, 244 photo sensors (vertical) and 320 photo sensors (horizontal), and a switching circuit SW. Take it out as That is, the imaging plane is divided into (244×320) pixels.
This signal is then sent to the TV via the video amplifier IA.
It is output as a signal from the camera 20. When the lead wires 4 are bonded using a group-shaped tool 8, for example, as shown in FIG. The result will be as shown in the figure. The imaging means IP also includes an illumination source 21, a condensing lens 22 that focuses light from the illumination source 21 onto the imaged area, an objective lens 23, and a reflecting mirror 24. Joint portion 5 having a cross-sectional shape as shown in FIG.
When the light from the illumination source 21 is projected from vertically above by the reflecting mirror 24, the light that hits the joint 5 is scattered and does not enter the objective lens 23, and therefore does not enter the TV camera 20. Since the surface of the semiconductor integrated circuit element 2 or the post 3 that is the object to be bonded is flat, the light is reflected in the projection direction and is reflected by the objective lens 2.
3 and enters the TV camera 20. Therefore, when monitoring the video of the TV camera 20, the first
It will look like Figure 5. This figure shows the case where the object to be bonded is a semiconductor integrated circuit element 2, in which the bonding portion 5 and the lead wire 4 in the shaded area are black, and the semiconductor integrated circuit element 2 is white. Even in semiconductor integrated circuit elements, there are parts that appear black, but these are 2P due to surface irregularities, scratches, or wiring patterns.

The processing means PC includes a binarization circuit BC and a video storage unit.
It consists of an IPM, a readout circuit R, a processing data creation circuit LC, and an arithmetic processing unit CPU. TV camera 20
Since the output signal from is an analog quantity, the binarization circuit BC converts it into two values, that is, "1" and "0".
signal. FIG. 16 shows a specific example of the binarization circuit BC, and shows a case where it is constructed from a comparison circuit using an operational amplifier OP. R ₁ and R ₂ are voltage dividing resistors, and by dividing the voltage of the power supply V by these resistors R ₁ and R ₂ , which potential of the input voltage from the TV camera 20 is set as the boundary, "1", " Create a reference voltage for converting to 0''. Therefore, if the input voltage from the TV camera 20 is higher than this reference voltage, the operational amplifier
The output of the OP, that is, the output of the binarization circuit BC, is "1", and if it is less than the reference voltage, it is "0".

The image storage unit IPM has one image storage unit corresponding to each photo sensor PS of the solid-state image sensor provided in the TV camera 20.
It is equipped with a bit storage section. That is, assuming that there are 244 solid-state image sensors in the vertical direction and 320 in the horizontal direction, this device will have a total of 78,080 photo sensors PS. Therefore, the video storage unit IPM is at least
Prepare a storage device with a storage capacity of 78080 bits. However, this is a case where the accuracy is to be further increased, and the capacity of the video storage unit IPM may be reduced by appropriately thinning out the data from time to time. Although not shown, the video value storage unit
The IPM is equipped with a writing circuit, and the TV camera 2
0 generates an output from the photo sensor PS at a certain position by the action of the switching circuit SW, at this point the storage address associated with the photo sensor PS is specified. Then, in accordance with the output of the TV camera 20, "1" or "0" from the binarization circuit BC is written into the storage section at the designated address. In this way, when the TV camera 20 outputs all images as electrical signals, the image storage section
Binarized video is temporarily stored in IPM.
Figure 17 shows the video storage unit IPM that stores this video.
This is a partial conceptual diagram of , and corresponds to that of FIG. 15. In FIG. 17, one square indicates one storage section. The TV camera 20 generates a relatively high voltage in the white portion in FIG.
The output of the binarization circuit BC in this part is "1", and on the other hand, the black part has a relatively low voltage, so the output of the binarization circuit BC in this part is "0", resulting in video storage. The storage section of each IPM contains the 17th memory section.
As shown in the figure, "1" and "0" are stored. Here, the central portion where "0"s are concentrated is the joint portion 5. In addition, in correspondence with FIG. 17, the video storage unit IPM is shown for the case where an (m×n) bit storage device is used, and the addresses are sequentially assigned from the left to the right of the top row, Thereafter, they are added sequentially to the rows below.

The readout circuit R sequentially reads out the stored contents of the video storage unit IPM, and in this readout, the clock generation command signal CLI from the arithmetic processing unit CPU, which will be described later, is performed in units of one line in correspondence with FIG. 17. Read out. Therefore, this readout circuit R
consists of a one-row clock generation circuit 30 and a read address generation circuit 31. When the clock generation command signal CLI is input, the one-line clock generation circuit 30 generates m pulses corresponding to one line of the image in the image storage unit IPM. Figure 18 shows 1
A specific example of the row clock generation circuit 30 is shown in which it is constructed from a clock signal generator 32, an RS flip-flop circuit 33, an AND gate 34, and a counter 35. The clock signal generator 32 always generates continuous pulses with a constant period. This clock signal generator 3
The pulse which is the output of 2 is inputted to the count terminal CK of the counter 35 via the AND gate 34. A clock generation command signal CLI from the arithmetic processing unit CPU is input to the set terminal S of the RS flip-flop circuit 33, and the RS
The flip-flop circuit 33 is set. Then, the output from the output terminal Q of the flip-flop circuit 33 is used as the control side input of the AND gate 34, and when the flip-flop circuit 33 is set, the AND gate 34 is opened. The counter 35 stores the video memory unit IPM in one line m.
Due to the bit structure, it is constructed of an (m-1) base counter, and the output from its overflow terminal OFL is input to the reset terminal R of the RS flip-flop circuit 33. Note that the output of the AND gate 34 is the count terminal of the counter 35.
It is input to the read address generation circuit 31 as the read clock pulse RCL as well as to the read clock pulse RCL. By doing this, when the clock generation command signal CLI is input from the arithmetic processing unit CPU, the RS
The flip-flop circuit 33 is set, and the AND gate 34 is set by the output of "1" from the output terminal Q.
will be held. Therefore, the clock pulse from clock generator 32 passes through AND gate 34;
It is added to the counter 35 and also to the read address generation circuit 31. The counter 35 is sequentially counted up by this clock pulse. and,
When m-th signal is added, overflow terminal OFL
A signal is output from the RS flip-flop circuit 33 to reset it. As a result, the signal from the output terminal Q of the RS flip-flop circuit 33 becomes "0", which closes the AND gate 34.
As a result, subsequent clock pulses from clock generator 32 will not be output from AND gate 34. That is, this circuit 30 outputs m clock pulses, ie, read clock pulse RCL, every time it receives the clock generation command signal CLI from the arithmetic processing unit CPU, and then stops generating the read clock pulse RCL.

The read address generation circuit 31 inputs the read clock pulse RCL from the clock generation circuit 30 for one row, and based on this pulse RCL, the image storage section
Sequentially scan and designate IPM addresses and sequentially read out the stored contents. This consists of an address counter, etc. That is, this circuit 31 realizes the above function by incrementing the address contents by 1 each time one read clock pulse RCL is input. Here, the clock generation circuit 3 for one row is
0 is a clock generation command signal from the arithmetic processing unit CPU
Since m pulses are generated each time CLI is received, when the clock generation circuit 30 for one row first receives the signal CLI, the read address generator 31 generates m bits of the first row in FIG. Address each and read the memory contents of each. Next, when signal CLI is applied to circuit 30, read address circuit 31 addresses each of the m bits of the second row and reads the respective stored contents of that row. Below, in the same way, the arithmetic processing section
Every time the clock generation command signal CLI is input from the CPU, the memory contents of each row are read out, and when the last row, that is, the nth row, is read out, the first row can be read out next. It is set as follows.

Based on the output from the image storage unit IPM, the processing data creation circuit LC inputs the area of the joint 5 and the data necessary for quality determination to the first output of the image storage unit IPM.
In correspondence with Figure 7, it is created and output for each line. FIG. 19a shows the memory contents of an arbitrary row b in FIG.
Junction data lx consisting of the number of bits corresponding to
The junction end data Ax consisting of the number of bits from the first digit to the end of the junction 5 is detected and outputted to the arithmetic processing unit CPU, which will be described later. As is clear from this figure, in this figure, the number of bits, that is, the number of pixels, corresponds to the area. The main parts of the processing data creation circuit LC are a junction detection circuit LX that detects junction data lx and a junction end detection circuit AX that detects junction end data Ax.
A falling detection circuit 40 is provided to provide timing signals to LX and AX.

As shown in Figure 17, the video storage unit IPM has the following information:
"1" is stored in white parts of the video, and "0" is stored in black parts. Due to the circuit configuration, the processing data creation circuit LC is a video storage section.
In order to negate the signal read from the IPM before taking it in, it is equipped with a negate circuit NOT.
In this way, white parts of the video can be taken in as "0" and black parts as "1". Figure 19b is a negative circuit for Figure 19a.
Shows the output of NOT.

The fall detection circuit 40 detects the time when the image changes from black to white, that is, from "0" to "1" in FIG. 19a, and outputs a signal. However, the circuit 40 is connected to a negative circuit, which will be described later.
Since the signal from the video storage unit IPM is input via NOT, the circuit 40 detects a fall from "1" to "0". (See Figure 19b)
FIG. 20 shows a specific example of the fall detection circuit 40, the main parts of which consist of a D-type flip-flop circuit 41 and a JK flip-flop circuit 42, and a read clock pulse RCL and an inverting circuit.
By inputting the output from NOT, the falling point is detected from both signals, and the falling signal 40S is detected.
Create and output. The output of the NOT circuit NOT is input to the input terminal D of the D-type flip-flop circuit 41. That is, the contents of each row of the video storage unit IPM are negated by the action of the readout circuit R and then sequentially inputted to this terminal D. That is, the first
Referring to Figure 9a, from the left side, the signal that is negated, in short, if it is “0”, it is “1”, and “1”
If so, "0" is input sequentially. The read clock pulse RCL is applied to the clock terminal CK of the D-type flip-flop circuit 41 via a delay circuit 43 and a one-shot pulse generation circuit 44.
The D-type flip-flop circuit 41 is a clock terminal.
When a clock signal is input to CK, the signal currently being input to input terminal D is temporarily stored and output from output terminal Q. By the way, the video storage unit
IPM specifies an address and requires some delay time until the stored contents of the specified address are read. Therefore, even if the read clock pulse RCL is directly input to the clock terminal CK, the contents of the address to be read by the read clock pulse RCL cannot be stored in the D-type flip-flop circuit 41. Therefore, the read clock pulse RCL is delayed by this amount by the delay circuit 43.
The one-shot pulse generation circuit 14 detects the rise of the output after the delay and generates a clock signal. D
The output of the flip-flop circuit 41 is inputted to the clock terminal CK of a JK flip-flop circuit 42 whose input terminal J is set to the power supply V, ie, "1", and whose input terminal K is set to ground, ie, "0". The output of this circuit 42 is outputted as the output of the fall detection circuit 40 via a one-shot pulse generation circuit 45. At the same time, the output of the one-shot pulse generating circuit 45 is input to the clear terminal CLR of the JK flip-flop circuit 42 via the NOT circuit 46, and is cleared. FIG. 21 is a time chart showing the operating status of each part in FIG. 20, where RCL is the read clock pulse RCL,
NOTS is the output of the NOT circuit NOT, 44S is the output of the one-shot pulse generation circuit 44, 41S is the output of the D-type flip-flop circuit 41, 42S is JK
The output of flip-flop circuit 42 is shown. 40S
is the output of the one-shot pulse generation circuit 45, which means the output of the falling edge detection circuit 40,
In other words, it becomes a falling signal. As is clear from this figure, the read clock pulse RCL is output at a constant cycle, and as it does so, the stored contents are read out sequentially from the video storage unit IPM, and the read contents change from "1" to "0". At this point, a falling signal 40S is output.

The junction detection circuit LX mainly includes counters 51, 52, a data selector 53, a comparator 54, AND gates 55, 56, 57, and flip-flop circuits 58, 59. counter 5
1 and 52 count the number of pulse signals input to the count input terminal CK, and output the counted value as output data. The data selector 53 inputs respective data from the counters 51 and 52, and selectively outputs one of them in response to a signal to the select terminal SLT. That is, in this case, the select terminal
If a “1” signal is input to the SLT, the data input to the input terminal A side, that is, the count value of the counter 51, is selected and output, and conversely, a “0” signal is input to the select terminal SLT. If so, the data input to the input terminal B side, that is, the count value of the counter 52 is selectively output. The comparator 54 compares the data input to the input terminal A side, that is, the count value of the counter 51, and the data input to the input terminal B side, that is, the count value of the counter 52, and if they are the same, the output terminal A =B
Therefore, if the value on the input terminal A side is large, the output terminal A
>B, and if the value on the input terminal B side is large, a signal of "1" is output from the output terminal A<B. Each output terminal A=B, A> of the comparator 54
B, the output of A<B is the corresponding AND gate 55,
56, 57, and each AND gate 55, 5
The falling signal 40S from the falling detection circuit 40 is input to each of 6 and 57, respectively. Therefore, at the time when the falling signal 40S is input to the AND gates 55, 56, and 57, only those to which the "1" signal is input from the comparator 54 output a "1" signal. An AND gate 56 is connected to the set terminal S of the flip-flop circuit 58.
The output of the AND gate 57 is input to the reset terminal R. The output from the output terminal Q of the flip-flop circuit 58 is input to the select terminal SLT of the comparator 53. By doing this, at the time when the falling detection signal 40S is output, the counter 5
If the count value of 1 is larger than that of the counter 52, the flip-flop circuit 58 is set and "1" is applied to the select terminal SLT of the data selector 53. Output the count value of 51. Conversely, when the falling detection signal 40S is output, if the count value of the counter 52 is larger than that of the counter 51, the flip-flop circuit 58 is reset and "0" is applied to the select terminal SLT of the data selector 53. Because of that,
The data selector 53 outputs the count value of the counter 52 input to the input terminal B. Note that if the count values of the counters 51 and 52 are the same, there is no change in the output of the flip-flop circuit 58, and the data selector 53 selects the previously selected counter 51,
The count value of one of 52 is output.

The flip-flop circuit 59 is an AND gate 5
The outputs of the AND gates 5 and 56 are input to the set terminal S via the OR gate 60, and the output of the AND gate 57 is input to the reset terminal R. Then, the output of the output terminal Q is inputted to the one shot pulse generation circuit 61 via the AND gate AND2, and further this circuit 61
The pulse signal created by the OR gate 62
The signal is applied to the clear terminal CLR of the counter 52 via the counter 52. The output of the negative output terminal of the flip-flop circuit 59 is input to the one-shot pulse generation circuit 63 via the AND gate AND1, and the pulse signal generated by this circuit 63 is input to the clear terminal CLR of the counter 51 via the OR gate 64. so that it is applied to and,
Falling signal 4 for AND gates AND1 and AND2
Make sure to input 0S. The output of the NOT circuit NOT is input to the count input terminals CK of the counters 51 and 52 via AND gates 65 and 66, respectively. The output from the output terminal Q of the flip-flop circuit 59 is input to the AND gate 66 via the delay circuit 67, and the output from the output terminal is input to the AND gate 65 via the delay circuit 68. In this way, if one or both of the AND gates 55 and 56 outputs a signal, that is, if the count value of the counter 51 is greater than or equal to the count value of the counter 52, the flipflop circuit 59 is set, and the counter 52 is cleared by the output from the output terminal Q. Conversely, if the count value of the counter 52 is greater than the count value of the counter 51, the flip-flop circuit 59 is reset by the output of the AND gate 57, and the counter 51 is cleared by the output of the output terminal. That is, counter 5
The maximum value up to now is stored in either one of 1 and 52, and the other count value smaller than this is cleared. Further, by setting the flip-flop circuit 59, the AND gate 66 is opened and the AND gate 65 is closed after the time set by the delay circuits 67 and 68 has elapsed. Conversely, when the flip-flop circuit 59 is reset, the delay circuits 67,
After the time period 68 has elapsed, AND gate 66 is closed and AND gate 65 is opened. Note that the delay circuits 67 and 68 are provided to prevent signals from being input to the counters that are being cleared while the counters 51 and 52 are being cleared. in short,
With this configuration, at a certain point in time, one of the AND gates 65 and 66 is open, and the corresponding counters 51 and 5 are open.
One of the two counts the signal from the NOT circuit NOT.
Then, based on the comparison result at the time when the falling signal 40S is generated, the contents of the counters 51 and 52 having the smaller count value are cleared, and almost simultaneously, the AND gates 65 and 66 on the side corresponding to the counters 51 and 52 are cleared. The counters 51 and 52 on the opened and cleared side start counting.

The junction end detection circuit AX includes a counter 71, a register 72, and a register control circuit 70.
The counter 71 counts the number of input pulses to its count input terminal CK, and stores the value in the register 72.
Enter. The register 72 temporarily stores the input from the counter 71 at the fall of the signal to the load terminal L, and outputs the stored contents. register 72
The fall of the signal to the load terminal L occurs when the comparison result of the comparator 54 moves from the output terminal A>B to the output terminal A<B, or from the output terminal A<B to the output terminal A>B. Let it happen. However, in the initial state, output terminal A = B to output terminal A.
The same applies when moving to >B. These are performed by the register control circuit 70. FIG. 22 shows a specific example of the register control circuit 70. The circuit 70 outputs the output of the AND gate 56 corresponding to the output terminal A>B of the comparator 54 and the AND gate corresponding to the output terminal A<B. gate 57
The function is realized by inputting the output of Therefore, the SR flip-flop output 73,
74, D-type flip-flop circuits 75 and 76, an AND gate 77, and a one-shot pulse generation circuit 78. The output from the AND gate 56 is input to the set terminal S of the flip-flop circuit 73 and the reset terminal R of the flip-flop circuit 74. and gate 57
The output from the flip-flop circuit 73 is input to the reset terminal R of the flip-flop circuit 73 and the set terminal S of the flip-flop circuit 74. Input terminals D of the flip-flop circuits 75 and 76 are connected to the power supply V, that is, a signal of "1" is always input to the terminal D. The output of the flip-flop circuit 73 is input to the clock terminal CK of the flip-flop circuit 75, and the output of the flip-flop circuit 74 is input to the clock terminal CK of the flip-flop circuit 76. The outputs of the flip-flop circuits 75 and 76 are connected to the OR gate 7.
7, and the output of the OR gate 77 is inputted to the load terminal L of the register 72 as a register control signal RCS via a one-shot pulse generation circuit 78. Note that the output of the one-shot pulse generating circuit 78 is simultaneously applied to the clear terminals CLR of the flip-flop circuits 75 and 76.
With this arrangement, when either one of the AND gates 56, 57 outputs a signal, the signal is sent to the set terminal S of the flip-flop circuits 73, 74.
The side that is input to is set, and the other side is reset. As a result, one of the flip-flop circuits 75 and 76 on the set side is set to "1", and accordingly, the one-shot pulse generating circuit 75 generates the register control signal RCS based on the output of the OR gate 77. Furthermore, both flip-flop circuits 75 and 76 are cleared by this signal RCS and return to their initial states.

The arithmetic processing unit CPU is connected to the video storage unit via the reading circuit R and further via the processing data creation circuit LC.
Import each product data necessary for judgment from IPM,
This is for determining the quality of the joint 5, and the case where a microcomputer is used is shown. A microcomputer executes processing, calculations, etc. according to a program stored in advance in a program storage device. FIG. 23 is a flowchart showing an outline of the program. In this figure, the arithmetic processing section CPU first performs initial settings of each section in step A. For example, this may be to clear a data storage section that temporarily stores data taken in from the processing data creation circuit LC, or to clear a data storage section that stores intermediate results of calculations or the like. In the next step B, the video storage unit IPM
The joint data shown in Fig. 19 in each row of
lx and junction end data Ax are read via the reading circuit R and the processing data creation circuit LC, and stored in a predetermined area of the data storage section. In the next step C, various data necessary for determining the quality of the joint 5 are calculated from the joint data lx and joint end data Ax of each row stored in the data storage section.
In the following explanation, each data is defined as follows. That is, as shown in FIG.
In correspondence with the figure, the junction data lx indicates the length of the junction 5 in a given row, that is, the number of bits, and the junction data Ax indicates the length from the left end of the row to the right end of the junction 5, that is, the number of bits. Show the number. Amini indicates the smallest numerical value among the joint end data Ax, and lmini indicates the smallest numerical value among the joint data lx. Note that lmini eventually matches the diameter of the lead wire 4. The lc row indicates the length from the left side to the center C of the lead wire 4, that is, the number of bits. lt is the length of the part where the length of the joint part 5 is 1.2lmini or more,
In other words, it indicates the number of bits. Further, within the range of lt, the area to the left of the center of the lead wire 4 of the joint 5, that is, the total number of bits, is ΣA, and similarly, the right side is ΣB, and the area of the joint 5 within the range of lt,
That is, let the number of bits be Σlx. Note that, as is clear from this figure, Σlx is the sum of ΣA and ΣB. From this, in step C described above, Amini, lmini, and Σlx are calculated. Subsequently, based on these data, in step D, the quality of the joint portion 5 is determined.

The arithmetic processing unit CPU outputs the initial clear signal ICL and clock generation command signal at the appropriate timing shown below.
CLI is output, and a signal from the overflow terminal OFL of the clock generation circuit 30 for one line and the processing data creation circuit are output at appropriate timings shown below.
By inputting the junction data lx and the junction end data Ax from the LC, the above calculations, processes, etc. are executed. Note that the initial clear signal ICL from the arithmetic processing unit CPU is the clear terminal of the OR gates 62 and 64 and the counter 71 of the processing data creation circuit LC.
Input to CLR.

FIGS. 25, 26, and 27 are detailed flowcharts of steps B, C, and D in FIG. 23, and the overall operation will be explained below with reference to these figures. In FIG. 25, in step B, the counter CNT is first set to 0 in step B1. This counter CNT is created in software and is associated with a predetermined address in the data storage section. This counter CNT is a row counter that counts each row of the video storage unit IPM. Next, in step B2, the processing data creation circuit LC is initialized. That is,
This applies the initial clear signal ICL to the OR gates 62 and 64 of the circuit LC and the clear terminal CLR of the counter 71. As a result, counter 5
1, 52, and 71 will be cleared. Next, in step B3, the clock generation command signal CLI is applied to the readout circuit R, and in the next step B4, the clock generation command signal CLI is applied to the readout circuit R.
Add 1 to CNT. In step B3, when the clock generation command signal CLI is applied to the reading circuit R, the circuit R sequentially reads out the stored contents of the first row of the video storage unit IPM. Then, in step B5, the output of the overflow terminal OFL of the counter 35 is read, and in step 6, the output of the overflow terminal OFL is "1", that is, the readout circuit R
It is determined whether or not the clock pulses for one line of the video storage unit IPM have been generated. Here, steps B5 and B6 are repeated until an overflow signal is output from the overflow terminal OFL. If the overflow signal is confirmed in step B6,
In step B7, the joint part data lx and joint part end data Ax from the processing data creation circuit LC are read and stored in the data storage section. Next step
At B8, it is determined whether the counter CNT has scanned n, that is, the image storage unit IPM, to the last line, and the process is repeated from step B2 to step B8 until this condition is satisfied. When the content of is n, the process proceeds to step C.

At step B3, the clock generation command signal is
When CLI is input to the readout circuit R, the readout circuit R sequentially reads out one line of the video storage unit IPM from the left and inputs it to the processing data creation circuit LC.
The flip-flop circuit 59 of the circuit LC is in either the set or reset state when the power is turned on. Now, the flip-flop circuit 59 is in the set state, and the series of data shown in FIG.
It is assumed that the data is read out according to the clock of the row clock generation circuit 30. Since flip-flop circuit 59 is in the set state, AND gate 65 is open and AND gate 66 is closed. Therefore, the counter 51 sequentially counts the number of "1"s input through the NOT circuit NOT. (See FIG. 19b) At the same time, the counter 71 clocks the clock generator 3 for one row.
The read clock pulses RCL from 0 are sequentially counted. From the 5th bit to the 6th bit, the data falls from "1" to "0". Then, the falling detection circuit 40 detects this and the falling signal 40S
Output. At this point, the count value of the counter 51 is "2", the count value of the counter 52 is "0", and the count value of the counter 71 is "5". Therefore, the AND gate 56 outputs a signal, and the selector 53 outputs the count value of the counter 51 "2".
Then, by setting the flip-flop circuit 59, the AND gate 65 is closed and the AND gate 66 is closed. In addition, the register control circuit 7
3 outputs a register control signal RCS, and the count value "5" of the counter 71 is set in the register 72. Furthermore, since signals are continuously output from the video storage unit IPM, the counter 52 counts subsequent "1"s. Then, when the data falls from "1" to "0" at the Pth bit, the fall detection circuit 40 detects this and outputs a fall signal 40S. At this point, the count value of the counter 51 becomes "2," the count value of the counter 52 becomes "lx," and the count value of the counter 71 becomes "Ax." Then, due to the generation of the falling signal 40S, the count value "lx" of the counter 52 is larger than the count value "2" of the counter 51, so the flip-flop circuit 58 is reset, and the selector 53 resets the count value of the counter 52. "lx" is output, and the flip-flop circuit 59
is reset, AND gate 66 is closed, AND gate 65 is opened, and counter 51 is cleared. Further, a register control signal RCS is generated, and the count value "Ax" of the counter 71 is set in the register 72. Subsequently, the counter 51 counts the number of "1"s from the NOT circuit NOT. After that, when the data falls from "1" to "0" again at the g-th bit, the falling detection circuit 4
0 detects this and outputs a falling signal 40S. At this point, the count value of the counter 51 is "3",
The count value of the counter 52 is "lx", and the count value of the counter 71 is "g". Then, the falling signal 40
Due to the occurrence of S, the count value "lx" of the counter 52 is larger than the count value "3" of the counter 51, so the flip-flop circuit 58 is reset again, and the selector 53 selects the count value "lx" of the counter 52.
will continue to be output. Furthermore, since the flip-flop circuit 59 is reset again, the AND gate 66 is closed, the AND gate 65 is opened, and the counter 51 is cleared. However, in this state, the register control signal RCS is not generated from the register control circuit 73, and the register 72 is set to "Ax".
continue to hold. Thereafter, one row of data is read out by the action of the readout circuit R up to the m-th bit, but there is no change in "lx" output from the selector 53 and "Ax" output from the register 72.
Therefore, in step B7, the arithmetic processing section
CPU accurately displays junction data lx, junction end data
Ax can be read.

As is clear from this explanation, since the processing data creation circuit LC is configured as shown in FIG. To effectively count only the joint portion 5 without erroneously counting even when a scratch or the like appears black. This is based on the idea that the width of the joint 5 is larger than that of other patterns, scratches, etc.

Thereafter, by repeating steps B2 to B8, the joint data lx and joint end data for each row up to the n-th row of the video storage unit IPM are
Ax is stored in the data storage unit in the arithmetic processing unit CPU.

When the above processing is completed, the arithmetic processing unit CPU calculates various data necessary for determining the quality of the joint 5 based on the contents stored in the data storage unit. That is, as shown in FIG.
In _C1 , search for lmini and Amini. This reads the lx of each row sequentially from the data storage unit, compares them sequentially, takes the smallest value among them as lmini, and sets the corresponding Ax.
This value is stored as Amini at a predetermined address in the data storage section. In the following step _C2 , the length lc of the lead wire 4 to the center C is calculated. As is clear from FIG. 24, this is done by subtracting 1/2lmini from Amini. In step C3, in order to execute the following steps,
Each address of the data storage unit storing the junction area Σlx, the junction effective length lt, and the area ΣB is cleared. In the next step C5, lx and Ax are read out for each row. And the steps
At C6, it is determined whether the lx is larger than 1.2·lmini, and if it is, the value of lx is added to the address set as Σlx at step _C7 . Then, the value of (Ax-lc) is further added to the address set as ΣB, and 1 is added to lt set as the storage address of the length of the joint portion 5. At step _C6 , if lx is not greater than or equal to 1.2·lmini, the value in this line is ignored and the process proceeds to step C8. At step C8, for each row step C5,
It is determined whether steps C6 and C7 have been executed, and if not, steps C5, C6, and C7 are executed for the next line. That is, steps C5, C6, and C7 are repeated n times for each row, as is clear from FIG. 17. At step C8,
When it is confirmed that the processing for each row has been completed, the process proceeds to step D. At this point, the number of bits corresponding to the junction lx, that is, the numerical value in the storage section, is stored at the address Σlx where the junction area is stored. Similarly, the corresponding bit values are stored in lt and ΣB.

In step D, a determination process is executed based on the various data calculated above. That is, in FIG. 27, the area increase rate Wa is calculated in step _D1 . This is done based on equation (1). Then, the result is stored in the preset address as Wa in the data storage section.
In D2, Σlx calculated in step C,
ΣA is calculated from ΣB and stored in the data storage unit. Based on the above calculation results, next we calculate the distortion factor Wc
Calculate. For this calculation, first
At D3, the magnitudes of ΣA and ΣB are compared, and based on the magnitude, a distortion factor Wc is calculated at either step D4 or step D4', and this value is stored in the data storage section. The following are steps for making an actual determination. In step D5, the area increase rate Wa stored in the data storage section is retrieved, and the area increase rate Wa, the allowable minimum area increase rate W1,
and the allowable maximum area increase rate W2, and if the area increase rate Wa is within this range, proceed to step D6; if it is outside this range, proceed to step D6.
Proceed to D7' and determine that the product is defective. minimum allowable,
For example, in FIG. 5, the allowable maximum area increase rates W1 and W2 are 30 [%], 55 [%], etc.
In step D6, the distortion factor Wc is determined. In other words, the distortion factor Wc stored in the data storage unit
and compare it with the maximum allowable distortion factor Wc,
If the distortion rate is within this range, it is determined to be a good product in step D7, and if it is outside this range, it is determined to be a defective product in step D7'. What is the maximum allowable distortion factor wc?
For example, in FIG. 10, this corresponds to 20 [%]. In steps D7 and D7', the arithmetic processing unit
The CPU outputs a signal corresponding to the judgment result to the outside, and for example, in step D7', control processing is performed such as issuing an alarm or removing the product from the line as defective. It will be used effectively. Also, step D7
In response to the signal, the product is sent to the next stage, and the joints of the next product are inspected. The series of tests is completed in the above manner.

In the above embodiments, the case where the readout circuit R, the image storage unit IPM, and the processed data creation circuit LC are arranged around the arithmetic processing unit CPU in order to improve the inspection speed has been described. It can be omitted if the specifications allow it. That is, the signal from the TV camera 20 may be binarized by the binarization circuit BC, and this may be directly taken in by the arithmetic processing unit CPU, thereby executing each process. Furthermore, a video storage unit IPM may be added to this, and each process may be executed in correspondence with the video storage unit IPM and the arithmetic processing unit CPU.

Further, the installation position of the TV camera 20 has not been specifically explained, but it may be any position where the joint portion 5 can be imaged, and for example, it may be installed on an arm of a bonding device. Also,
In the above embodiment, the TV camera 20 is arranged relative to the joint 5 so that the joint 5 is parallel to the edge of the imaging surface, that is, the center line of the lead wire 4 is parallel to the end of the imaging surface. Although described, the present invention is not limited thereto. That is, even if the joint portion 5 is tilted with respect to the edge of the imaging plane, it is possible to detect this, and accordingly, it is also possible to correct it.

Furthermore, in the above embodiments, a case has been described in which a bonded portion bonded by a wire bonding device employing an ultrasonic method is inspected, but the present invention is not limited to this, and the present invention is not limited to this. The present invention can also be applied to the inspection of joints formed by wire bonding equipment employing thermocompression bonding methods such as those typified by the method. Furthermore, the present invention is not limited to the bonded portion formed by pressure bonding such as the above-mentioned ultrasonic bonding or diffusion bonding typified by thermocompression bonding. That is, it can be widely used for inspecting joints formed by welding such as fusion welding, pressure welding, brazing, or other joining means. In addition, in the embodiment, the lead wire 4
Although the description has been made with respect to the joint between the semiconductor integrated circuit element and the post 3, the members in the present invention are not limited to these, and furthermore, there is no limit to the number of these members.

As is clear from the above description, when inspecting a joint, the present invention targets the area of the joint that has been plastically deformed. It is possible to obtain a method and apparatus for inspecting a bonded portion that can inspect the bonded portion and improve the inspection accuracy.

[Brief explanation of drawings]

Fig. 1 is an explanatory diagram for explaining the conventional inspection method, Fig. 2 is a plan view showing an example of a joint, Fig. 3 is a side view of the same, and Fig. 4 is a plan view showing another example of a joint. Figure 5 is a diagram for explaining the present invention, Figure 6 is a diagram for explaining the present invention.
7, 8, and 9 are plan views of joints for explaining the present invention, FIG. 10 is a diagram for explaining the present invention, and FIG. 11 is an embodiment of the apparatus of the present invention. A block diagram showing an example, FIG. 12 is an explanatory diagram showing the principle of a television camera, FIG. 13 is a diagram showing the groove shape of the bonding device, FIG. 14 is a cross-sectional view of the bonding part, and FIG. 15 is an illustration of the imaging FIG. 16 is a circuit diagram showing an example of a binarization circuit; FIG. 17 is a circuit diagram showing an example of a binarization circuit.
18 is a block diagram showing an example of a clock generation circuit for one line, FIG. 19 is a diagram showing an example of the output from the video storage section, and FIG. 20 is a diagram showing an example of the output from the video storage section. A block diagram showing an example of a fall detection circuit, FIG. 21 is a time chart showing operating waveforms of each part in FIG. 20, FIG. 22 is a block diagram showing an example of a register control circuit, and FIG. A flowchart showing an example of a control procedure, FIG. 24 is an explanatory diagram for explaining the operation of the arithmetic processing section, and FIGS. 25, 26, and 27 are flowcharts showing the process in FIG. 23 in detail. be. 5: Joint part, IP: Imaging means, 20: Television camera, PC: Processing means, BC: Binarization means, IPM: Image storage means, R: Reading means, LC:
Processing data creation circuit, LX: joint detection means,
AX: Junction end detection circuit, 40: Fall detection circuit, CPU: Arithmetic processing unit.

Claims (1)

[Scope of Claims] 1. In a product in which a member is plastically deformed and joined to another member, the area of the plastically deformed joint is measured, the measured value is compared with a predetermined reference area, and the comparison result is A joint inspection method for determining the quality of the joint based on the quality of the joint. 2. The method for inspecting a bonded portion according to claim 1, wherein the bonded portion is formed at a portion where the lead wire is bonded to a mating member using a wire bonding device. 3. A patent characterized in that the standard area consists of a maximum permissible area and a minimum permissible area, and the quality of the joint is judged based on whether or not the area of the joint is within the range defined by each of the permissible areas. A method for inspecting a joint according to claim 1. 4. The method for inspecting a joint according to claim 1, wherein the determination is made based on an allowable rate of change in the joint area with respect to one reference area. 5. The method for inspecting a joint according to claim 1, wherein the reference area is the area of the members to be joined before joining. 6. The method for inspecting a joint according to claim 1, wherein the reference area is a part of the joint. 7. Claim 1, characterized in that the reference area is one side divided into two from the center of the joint part.
Inspection method for joints described in Section 1. 8. Claim 1, characterized in that the joint is imaged on an imaging surface, the area of the joint is substantially extracted from this image, and the quality of the joint is determined based on the extracted area. Method for inspecting joints. 9. The joint inspection method according to claim 8, wherein the video is binarized for each pixel, and the area of the joint is made to correspond to the number of pixels. 10 In a product in which a member is plastically deformed and joined to another member, an imaging means for imaging the plastically deformed joint and outputting the image formed on an imaging surface as an electrical signal; and a video signal input from the imaging means; , processing means for extracting the area of the joint from the video signal and comparing the extracted area with a predetermined reference area to determine the quality of the joint. . 11 At the joint, wire the lead wire to the mating member.
11. The inspection device for a bonded portion according to claim 10, wherein the inspection device is formed on a portion bonded by a bonding device. 12. The joint inspection device according to claim 10, wherein the imaging means includes a solid-state imaging device. 13. The joint inspection device according to claim 10, wherein the processing means includes binarization means for binarizing the video signal from the imaging means for each pixel and outputting the binarized image signal. 14. Claims in which the processing means comprises an image storage means that temporarily stores the output of the binarization means pixel by pixel, and binarizes and stores the resulting image formed on the imaging surface of the imaging means. 14. The joint inspection device according to item 13. 15. The processing means according to claim 14, wherein the processing means includes a processing section that extracts the area of the joint based on the stored content of the video storage means and determines the quality of the joint based on this area. Joint inspection device. 16 The processing unit comprises a processing data creation means for creating data necessary for determination from the stored contents of the video storage means, and an arithmetic processing means for performing pass/fail determination based on the output data from the processing data creation means. A joint inspection device according to claim 15. 17. The joint inspection device according to claim 16, wherein the processing section comprises reading means for sequentially reading out the stored contents of the video storage means in response to a command signal from the arithmetic processing means. 18. Claim No. 1, characterized in that the video stored in the video storage means is divided into a plurality of lines each composed of a plurality of pixels, and the processing data creation means creates data necessary for processing for each row. 17. The joint inspection device according to item 16. 19. The joint unit according to claim 17, wherein the video stored in the video storage means is divided into a plurality of lines each composed of a plurality of pixels, and the reading means reads out the stored content in units of rows. inspection equipment. 20. The joint inspection device according to claim 18, wherein the processing data creation means outputs the joint data line by row. 21. The joint inspection device according to claim 18, wherein the processing data creation means outputs joint data and joint end data on a line-by-row basis.