JPH0249016B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a joint inspection method and apparatus for inspecting the strength, etc. of a joint joined by a joining means. It can be used to inspect the joint between the element and the lead wire, or the post and the lead wire when connecting the element and the post with a lead wire using various wire bonding devices. It is suitable.

[Background of the invention]

For connections between semiconductor integrated circuit elements mounted on a substrate, or between the semiconductor integrated circuit elements and posts formed on the substrate, lead wires made of aluminum wire are used, and these are connected to the semiconductor integrated circuit or posts. It is widely used to perform sonic bonding. Figure 1 shows a state in which a semiconductor element circuit element mounted on a substrate is connected to a post, where 1 is a substrate, 2 is a semiconductor integrated circuit element mounted on the substrate 1, 3 is a post, and 4 is a post. This is a lead wire that electrically connects the semiconductor integrated circuit element 2 and the post 3. Generally, an aluminum wire is used as the lead wire 4. In this structure, the joint 5 between the semiconductor integrated circuit element 2 or the post 2 and the lead wire 4 is inspected by pulling the lead wire 4 with a predetermined force using a tensioner 6, and in this state, the lead wire 4 is This is done depending on whether or not the connection status is maintained. That is, by pulling with a predetermined force, if the joint of the joint portion 5 is separated, the test piece is judged as defective, and if the joint state is maintained, the test piece is passed. Note that the magnitude of this tensile force is determined through experiments and the like.

In this way, the joint 5 is inspected by applying an external force to the lead wire 4 and physically changing it, thereby applying force to the joint. As a result, the lead wire 4 may be deformed, this may cause damage, or there may be an adverse effect on the joint, which ultimately results in a decrease in yield.

FIGS. 2 and 3 are a plan view and a side view of the bonded portion of the lead wire 4 by the ultrasonic wire bonding device. As shown in these figures, when joining is performed by the ultrasonic method, the lead wire 4 undergoes plastic deformation.
This plastically deformed portion is the joint portion 5. The shape of this joining portion 5 changes for each joining operation. Here, it is conventionally known that the maximum deformation width W of the joint portion 5 and the tensile strength value have a correlation.
Furthermore, the present inventors have proposed that the area of the joint portion 5 and the tensile strength value have a correlation. Therefore, conventionally, the maximum deformation width W of the joint portion 5
Alternatively, if the area is measured and the strength of the joint 5 is determined indirectly depending on whether or not it has a predetermined value, the joint can be joined without contact and without applying any external force to the lead wire 4. It is conceivable that part 5 can be inspected. According to this, the drawbacks of the conventional ones described above can be overcome. However, in Figure 2,
The joint 5 shown in FIG. 3 shows an ideal joint state, and the actual joint 5 has various shapes. For example, as shown in FIG. 4, when the joint 5 has a shape with a protrusion 7 at its center,
Even if the maximum deformation width W or area has a predetermined value, when a tensile test is carried out, it does not have the predetermined tensile strength and the bond comes off.

[Object of the Invention] The present invention has been made in view of the above points, and its purpose is to enable non-contact inspection of the joint without applying external force to the joint. The object of the present invention is to provide a joint inspection device that can improve inspection accuracy.

[Summary of the invention]

The inventors made numerous samples of joints, tensile tested each of them, and collected data. According to this, for a joint having a shape as shown in FIG. 2, there is a correlation between the maximum deformation width W and the tensile strength. However, it has become clear that for other unique shapes, such as the shape represented by FIG. 4, the above-mentioned correlation becomes extremely weak or disappears altogether. From this, the present inventors concluded that, for example, in the one shown in FIG. 4, the extremely protruding protrusion 7 of the joint 5 hardly contributes to improving the joint force, that is, the tensile strength. I got it.

Therefore, in order to achieve the above object, the present invention
It includes an imaging means and a processing means. The imaging means images the joint portion of the joining member, divides the image formed on the imaging surface into a plurality of lines, sequentially scans each row, converts the image into an electrical signal, and outputs the image.
The processing means inputs the video signal from the imaging means, and determines whether or not correction is necessary for the width data of the joint portion in each row in relation to the width data of other rows, and according to the determination result. The quality of the joint portion is determined based on each determined width data.

When taking an image of the bonded portion using an imaging means, it is desirable to take an image through a magnifying means such as a lens in order to improve accuracy. Note that the enlarging means may be separate from the imaging means, and preferably, it is advantageous in terms of the configuration of the apparatus to use an imaging means equipped with an enlarging means. As an imaging means, for example, a television camera using an image pickup tube that takes out an image as an electrical signal by deflecting and focusing an electron beam emitted from an electron gun using a coil to capture an image formed on an imaging surface, or A so-called solid-state television camera or the like in which the image pickup tube is replaced with a solid-state image pickup tube element can be used. This type of device divides the imaging surface into a large number of rows and sequentially scans each row to convert the image into an electrical signal and output it.

It is convenient for the processing means to adopt a digital processing method from the viewpoint of its functionality. To this end, it is preferable to provide a binarizing means to binarize the video information from the imaging means, and to perform subsequent processing based on the output of this binarizing means. In processing, the output of the binarization means may be directly processed, but a storage means is provided, the binarized video information is temporarily stored in the storage means, and subsequent processing is carried out by the storage means. It is advantageous in terms of the configuration of the device to perform the process based on the contents of .
A so-called microcomputer is well suited for the main part of the processing means, especially for making decisions. However, it is also possible to use other arithmetic processing means with similar functionality. In the determination processing, the arithmetic processing means may sequentially read out the stored contents from the storage means that temporarily stores the video information, that is, the video storage means. It is desirable to provide a processing data creation means for creating necessary information, and to have the arithmetic processing means execute the determination based on the information from the means, in the sense that processing speed can be improved.

[Embodiments of the invention]

An embodiment of the present invention shown in FIG. 5 will be described below. This embodiment shows a case where the quality of the joint 5 is inspected based on the area increase rate of the joint described above. As an example, this area increase rate was calculated as follows. That is, in FIG. 6, the wire diameter of the lead wire 4 is lmini, and the joint part 5 is
If the length of the part whose width is more than 1.2 times the wire diameter lmini of lead wire 4 is lt, and its area, that is, the area of the shaded part in the figure, is Σlx, then the area increase rate is
Wa is calculated using the following formula.

Wa=Σlx−lmini・lt/lmini×lt×100[%]……(1) In this equation (1), lmini×lt is the area of the lead wire 4 per length lt, and in short, the area increase rate Wa
represents the degree of area increase after bonding in the length lt portion of the lead wire 4. length lt 1.2lmini
This is based on the premise that the characteristics of the joint 5 are concentrated in the center.

FIG. 7 shows the joint area and tensile strength measured for each of a number of samples. Figure 5 summarizes these measurement results. The samples were prepared by ultrasonic bonding, and the conditions were as follows. In other words, the wire bonding device used was an ultrasonic type, with a maximum oscillation output of 20
[W], made by ORTHODYNE ELECTRONICS in the United States, is for thick wire, and the wedge is made of cemented carbide and has grooves. The bonding surface is aluminum vapor-deposited film, the lead wire is aluminum 99.99 [%], thickness 300 [um],
An aluminum wire with a tensile strength of 350 [g] was used.
In FIG. 7, the vertical axis shows the tensile strength [g] when the lead wire 4 is pulled perpendicularly to the substrate 1, and the horizontal axis shows the area increase rate [%].

As is clear from FIG. 7, which summarizes the measurement results, there is a correlation between the tensile strength and the area increase rate Wa. According to the measurement results, the area increase rate Wa
In many cases, the bonded portion 5 peels off when the bonding area is less than 30%. In addition, the area increase rate Wa is 30 [%]
Most of the above will be cut off. In this cutting region, the tensile strength depends not on the strength of the joint 5 but on the strength of the plastically deformed lead wire 4 itself. Further, in a region where the area addition rate Wa is large, the tensile strength gradually decreases as the area increase rate Wa increases.

Therefore, for example, the area increase rate of the joint 5 is defined as the inspection passing range of the joint 5 joined under the same conditions as above.
Wa was set at 30 [%] to 55 [%]. This range differs depending on the tensile strength of the joint 5 and the yield [%], and can be varied depending on each.

Furthermore, this embodiment shows a case where the shape of the joint is determined in order to further improve accuracy. That is, according to FIG. 7, a peculiar phenomenon occurs in which the vertical tensile strength is about 160 [g] even though the area increase rate Wa is within a predetermined range. In FIG. 7, S indicates this. FIG. 8 shows an example of the shape of the joint portion 5 of this product. As is clear from this figure, the left and right sides of the joint 5 are extremely unbalanced with respect to the center line C of the lead wire 4. That is, with respect to the center line C, the left side is hardly plastically deformed, and the right side is largely plastically deformed. Such a shape may actually occur when the lead wires 4 are joined, depending on the contact between the lead wires 4 and the tool that presses the lead wires 4 against the surface to be joined. If the joint portion 5 takes on such a shape, its tensile strength will decrease.

Therefore, in addition to the above-mentioned area increase rate of the joint 5, the shape of the joint 5, that is, the left and right unbalance rate (hereinafter referred to as the distortion rate) with respect to the center line C of the lead wire 4 is also a criterion. I'll do what I do. 9th
The figure shows the measured tensile strength [g] of samples that were intentionally made to be unbalanced left and right with respect to the center line C of the lead wire 4, and the results are summarized. In preparing the sample, other conditions were the same as those in FIG. 5, and the area increase rate was within the acceptable range. In FIG. 9, the vertical axis is the same as that in FIG. 5, and the horizontal axis is distortion Wc [%]. The distortion factor Wc was calculated as follows.
That is, in FIG. 8, the center line C of the lead wire 4 is located at a portion of the joint portion 5 whose width is 1.2 times or more the width lmini of the lead wire 4 (portion shown in perspective).
Let the area on the left side be ΣA, and the area on the right side be ΣB, and calculate it using the following formula. (ΣA<ΣB.) Wc=|(1−ΣA/ΣB)|×100[%]……(2) As is clear from Figure 9, the area increase rate is within the acceptable range. However, when the strain rate exceeds 25%, the tensile strength gradually decreases. Therefore, by utilizing this relationship, it was decided that the strain rate of the joint portion 5 was within 20% to pass.
Like the area increase rate, this range also varies depending on the tensile strength, yield, etc., and can be changed to various ranges depending on each. After the lead wires 4 are joined, the ΣA and ΣB of the joint portion 5 are measured or calculated, and the distortion factor Wc is calculated using equation (2). As a result, if the distortion rate Wc is within 20%, the test is passed; otherwise, the test is rejected. Note that this determination based on the distortion rate may be performed after the determination of the area increase rate, or may be performed at a prior stage.

In this way, by adding the distortion rate to the determination conditions, inspection accuracy can be further improved.

Furthermore, in the embodiment, the necessity of correcting the width data of each row of the joint portion is shown in the following manner. That is, Fig. 10, 1st
As shown in Figure 1, the width lx at any position of the joint 5 is taken as the vertical axis, and the length of the joint 5 in the central axis direction of the lead wire 4 is determined laterally from the boundary d between the lead wire 4 and the joint 5. If x is taken as the axis, a curve as shown in FIG. 11 will be obtained. This curve can be approximated to the following quadratic polynomial without an inflection point.
(a, b, and c are constants.) lx=ax ² +bx+c ……(3) When this formula (3) is first differentiated, dlx/dx=2ax+b ……(4) and (3) When we differentiate the formula to the second order, we get d ² lx/dx ² = 2a (5). The embodiment focuses on the fact that this second-order differentiated value becomes a constant, and calculates the second-order differential value from the second-order difference value at regular intervals of x, and determines that the value changes significantly as an abnormality, and further corrects it. It is something.

That is, lx (x=1 to n) is determined as shown in FIG. 10, and the first-order difference value for this lx is determined using the following equation. (However, x=1 to n-1) Δlx=l _x+1 −l _x (6) Furthermore, the second-order difference value Δ ² lx due to lx is determined by the following equation. (However, x=1 to n-2) Δ ² l _x = Δl _x+1 −Δl _x (7) This Δ ² lx becomes a constant for becoming a second-order differential value. In reality, since variations are expected, the standard value of the constant is approximated to a quadratic polynomial from the data and is 2a
Alternatively, a histogram or the like may be created from the data and the most frequent value may be determined. 12th
The figure shows an example of the histogram, and here, the most frequent value Δ ² lc is taken as the standard value. 1st
The histogram in Fig. 2 is for a normal-shaped joint 5 as shown in Fig. 10. For example, if this is a shape with an extremely protruding protrusion 7 as shown in Fig. 4, the lx curve and , the histogram is the 13th
As shown in FIG. 14 and FIG. That is,
Due to the protrusion 7, the value deviated from the most frequent value,
Δ ² f, Δ ² lg, and Δ ² lh begin to appear. Therefore, these Δ ² lf, Δ ² lg, and Δ ² lh are determined to be abnormal. Furthermore, by setting Δ ² lf, Δ ² lg, and Δ ² lh to the standard value Δ ² lc, the accompanying Δlx,
This is done by changing the value of lx.

In FIG. 5, IP is an imaging means and PC is a processing means. The main part of the imaging means IP consists of a television camera (hereinafter referred to as TV camera) 20. In the embodiment, a so-called solid-state television camera using a solid-state image sensor is used as the TV camera 20. FIG. 15 shows an example of this operating principle. A large number of solid-state image sensors are arranged vertically and horizontally, for example, 244 in the vertical direction and 320 in the horizontal direction.
It is a highly integrated circuit element consisting of two photo sensors PS and a switching circuit SW, and extracts the image formed on the imaging surface as an electrical signal by switching scan. That is, the imaging plane is divided into (244×320) pixels. This signal is then output as a signal to the TV camera 20 via the video amplifier IA. For example, a group-shaped tool 8 as shown in FIG. 16 is used in a wire bonding device employing ultrasonic waves to
When these are joined, the cross-sectional shape of the plastically deformed joint after joining becomes as shown in FIG. Imaging means
The IP also includes an illumination source 21, a condenser lens 22 that collects light from the illumination source 21 onto an imaged area, an objective lens 23, and a reflecting mirror 24. When light from the illumination source 21 is projected from vertically above the joint 5 having a cross-sectional shape as shown in FIG. , does not enter the TV camera 20. Since the surface of the semiconductor integrated circuit element 2 or the post 3, which is the object to be bonded, is flat, the light is reflected in the projection direction and enters the TV camera 20 through the objective lens 23. For this reason, the TV camera 20
When the image is monitored, it becomes as shown in Fig. 18.
This figure shows the case where the object to be bonded is a semiconductor integrated circuit element 2, in which the bonding portion 5 and the lead wire 4 in the shaded area are black, and the semiconductor integrated circuit element 2 is white. Even semiconductor integrated circuit elements appear black, but these are surface irregularities, scratches, or wiring patterns 2P.

The processing means PC includes a binarization circuit BC and a video storage unit.
It consists of an IPM, a readout circuit R, a processing data creation circuit LC, and an arithmetic processing unit CPU. TV camera 20
Since the output signal from is an analog quantity, the binarization circuit BC binarizes it, that is, converts it into a signal of "1" and "0". FIG. 19 shows a specific example of the binarization circuit BC, and shows a case where it is constructed of a comparison circuit using an operational amplifier OP. R ₁ and R ₂ are voltage dividing resistors, and by dividing the voltage of the current V by these resistors R ₁ and R ₂ , at which potential of the input voltage from the TV camera 20 is the boundary, it becomes "1" or "0". Create a reference voltage for converting to ``. Therefore, if the input voltage from the TV camera 20 is equal to or higher than this reference voltage, the output of the operational amplifier OP, that is, the output of the binarization circuit BC, will be "1", and if it is less than the reference voltage, it will be "0". .

The image storage unit IPM has one image storage unit corresponding to each photo sensor PS of the solid-state image sensor provided in the TV camera 20.
It is equipped with a bit storage section. That is, assuming that there are 224 solid-state image sensors in the vertical direction and 320 in the horizontal direction, this device will have a total of 78,080 photo sensors PS. Therefore, the video storage unit IPM is at least
Prepare a storage device with a storage capacity of 78.080 bits. However, this is a case where the accuracy is to be further increased, and the capacity of the video storage unit IPM may be reduced by appropriately thinning out the data from time to time. Although not shown, the video storage unit
The IPM is equipped with a writing circuit, and the TV camera 2
0 generates an output from the photo sensor PS at a certain position by the action of the switching circuit SW, at this point the storage unit associated with the photo sensor PS is addressed. And TV camera 20
In response to the output of
“1” or “0” from the value conversion circuit BC is written. In this way, when the TV camera 20 outputs all images as electrical signals, the image storage section
Binarized video is temporarily stored in IPM.
Figure 20 shows the video storage unit IPM that stores this video.
This is a partial conceptual diagram of , and corresponds to that of FIG. 18. In FIG. 20, one square represents one storage section. The TV camera 20 generates a relatively high voltage in the white part in FIG.
The output of the binarization circuit BC in this part is "1", and on the other hand, the black part has a relatively low voltage, so the output of the binarization circuit BC in this part is "0", and as a result, the video memory is stored. The memory section of each IPM contains the 20th memory section.
As shown in the figure, "1" and "0" are stored. Here, the central portion where "0"s are concentrated is the joint portion 5. In addition, in correspondence with FIG. 20, the video storage unit IPM is shown for the case where an (m×n) bit storage device is used, and the addresses are sequentially assigned from the left to the right of the top row, Thereafter, they are added sequentially to the rows below.

The readout circuit R sequentially reads out the stored contents of the video memory unit IPM, and in this readout, the clock generation command signal CLI from the arithmetic processing unit CPU, which will be described later, is performed in units of one line in correspondence with FIG. 20. Read out. Therefore, this readout circuit R
is composed of a one-row clock generation circuit 30 and a read address generation circuit 31. When the clock generation command signal CLI is input, the one-line clock generation circuit 30 generates m pulses corresponding to one line of the image in the image storage unit IPM. Figure 21 shows 1
A specific example of the row clock generation circuit 30 is shown in which it is constructed from a clock signal generator 32, an RS flip-flop circuit 33, an AND gate 34, and a counter 35. The clock signal generator 32 always generates continuous pulses with a constant period. This clock signal generator 3
The pulse which is the output of 2 is inputted to the count terminal CK of the counter 35 via the AND gate 34. A clock generation command signal CLI from the arithmetic processing unit CPU is input to the set terminal S of the RS flip-flop circuit 33, and the RS
The flip-flop circuit 33 is set. The output from the output terminal Q of the flip-flop circuit 33 is used as a control input of the AND gate 34, and the AND gate 34 is opened when the flip-flop circuit 33 is set. The counter 35 is constituted by a (m-1) base counter because the video storage unit IPM is configured with m bits per line, and the output from the overflow terminal OFL is input to the reset terminal R of the RS flip-flop circuit 33. Make it. Note that the output of the AND gate 34 is the count terminal of the counter 35.
It is input to the read address generation circuit 31 as the read clock pulse RCL as well as to the read clock pulse RCL. By doing this, when the clock generation command signal CLI is input from the arithmetic processing unit CPU, the RS
The flip-flop circuit 33 is set, and the AND gate 34 is set by the output of "1" from the output terminal Q.
will be held. Therefore, the clock pulse from clock generator 32 passes through AND gate 34;
It is added to the counter 35 and also to the read address generation circuit 31. The counter 35 is sequentially counted up by this clock pulse. and,
When m-th signal is added, overflow terminal OFL
A signal is output from the RS flip-flop circuit 33 to reset it. As a result, the signal from the output terminal Q of the RS flip-flop circuit 33 becomes "0", which closes the AND gate 34.
As a result, subsequent clock pulses from clock generator 32 will not be output from AND gate 34. That is, this circuit 30 outputs m clock pulses, ie, read clock pulse RCL, every time it receives the clock generation command signal CLI from the arithmetic processing unit CPU, and then stops generating the read clock pulse RCL.

The read address generation circuit 31 inputs the read clock pulse RCL from the clock generation circuit 30 for one row, and based on this pulse RCL, the image storage section
Sequentially scan and designate IPM addresses and sequentially read out the stored contents. This consists of an address counter, etc. That is, this circuit 31 realizes the above function by incrementing the address contents by 1 each time one read clock pulse RCL is input. Here, the clock generation circuit 3 for one row is
0 is a clock generation command signal from the arithmetic processing unit CPU
In order to generate m pulses while receiving CLI, when the clock generation circuit 30 for one row first receives the signal CLI, the read address generator 31 generates m bits of the first row as shown in FIG. Address each and read the memory contents of each. Next, when signal CLI is applied to circuit 30, read address circuit 31 addresses each of the m bits of the second row and reads the respective stored contents of that row. Below, in the same way, the arithmetic processing section
Every time the clock generation command signal CLI is input from the CPU, the memory contents of each row are read out, and when the last row, that is, the nth row, is read out, the first row can be read out next. It is set as follows.

Based on the output from the image storage unit IPM, the processing data creation circuit LC generates the area of the joint 5 and the data necessary for pass/fail judgment in the second part of the image storage unit IPM.
In correspondence with Figure 0, it is created and output for each row. FIG. 22a shows the memory contents of an arbitrary k row in FIG. lx
Then, the junction end data Ax consisting of the number of bits from the first digit to the end of the junction 5 is detected and outputted to the arithmetic processing unit CPU, which will be described later. As is clear from this figure, the number of bits,
In other words, the number of pixels is made to correspond to the area. The main parts of the processing data creation circuit LC are a junction detection circuit LX that detects junction data lx and a junction edge detection circuit AX that detects junction edge data Ax. A downlink detection circuit 40 is provided.

As shown in Figure 20, the video storage unit IPM has the following information:
"1" is stored in white parts of the video, and "0" is stored in black parts. Due to the circuit configuration, the processing data creation circuit LC is a video storage section.
In order to negate the signal read from the IPM before taking it in, it is equipped with a negate circuit NOT.
In this way, white parts of the video can be taken in as "0" and black parts as "1". Figure 22b is a negative circuit for Figure 22a.
Shows the output of NOT.

The fall detection circuit 40 detects the time when the image changes from black to white, that is, from "0" to "1" in FIG. 22a, and outputs a signal. However, the circuit 40 is connected to a negative circuit, which will be described later.
Since the signal from the video storage unit IPM is input via NOT, the circuit 40 detects a fall from "1" to "0". (See Figure 22b)
FIG. 23 shows a specific example of the fall detection circuit 40, the main part of which consists of a D-type flip-flop circuit 41 and a JK flip-flop circuit 42, and a read clock pulse RCL and an inverting circuit.
By inputting the output from NOT, the falling point is detected from both signals, and the falling signal 40S is detected.
Create and output. The output of the NOT circuit NOT is input to the input terminal D of the D-type flip-flop circuit 41. That is, the contents of each row of the video storage unit IPM are negated by the action of the readout circuit R and then sequentially inputted to this terminal D. That is, the second
Referring to Figure 2a, from the left side, the signal that is negated, in short, if it is “0”, it becomes “1”, and “1”
If so, "0" is input sequentially. The read clock pulse RCL is applied to the clock terminal CK of the D-type flip-flop circuit 41 via a delay circuit 43 and a one-shot pulse generation circuit 44.
The D-type flip-flop circuit 41 is a clock terminal.
When a clock signal is input to CK, the signal currently being input to input terminal D is temporarily stored and output from output terminal Q. By the way, the video storage unit
IPM specifies an address and requires some delay time until the stored contents of the specified address are read. Therefore, even if the read clock pulse RCL is directly input to the clock terminal CK, the contents of the address to be read by the read clock pulse RCL cannot be stored in the D-type flip-flop circuit 41. Therefore, the read clock pulse RCL is delayed by this amount by the delay circuit 43.
The one-shot pulse generation circuit 14 detects the rise of the output after the delay and generates a clock signal. D
The output of the flip-flop circuit 41 is inputted to the clock terminal CK of a JK flip-flop circuit 42 whose input terminal J is set to the power supply V, ie, "1", and whose input terminal K is set to ground, ie, "0". The output of this circuit 42 is outputted as the output of the fall detection circuit 40 via a one-shot pulse generation circuit 45. At the same time, the output of the one-shot pulse generating circuit 45 is input to the clear terminal CLR of the JK flip-flop circuit 42 via the NOT circuit 46, and is cleared. FIG. 24 is a time chart showing the operating status of each part in FIG. 23, where RCL is the read clock pulse RCL,
NOTS is the output of the NOT circuit NOT, 44S is the output of the one-shot pulse generation circuit 44, 41S is the output of the D-type flip-flop circuit 41, 42S is JK
The output of flip-flop circuit 42 is shown. 40S
is the output of the one-shot pulse generation circuit 45, which means the output of the falling edge detection circuit 40,
In other words, it becomes a falling signal. As is clear from this figure, the read clock pulse RCL is output at regular intervals, and the stored contents are sequentially read from the video storage unit IPM, and the read contents change from "1" to "0". At this point, a falling signal 40S is output.

The junction detection circuit LX mainly includes counters 51, 52, a data selector 53, a comparator 54, AND gates 55, 56, 57, and flip-flop circuits 58, 59. counter 5
1 and 52 count the number of pulse signals input to the count input terminal CK, and output this counted value as output data. The data selector 53 inputs respective data from the counters 51 and 52, and selectively outputs one of them in response to a signal to the select terminal SLT. That is, in this case, the select terminal
If a “1” signal is input to the SLT, the data input to the input terminal A side, that is, the count value of the counter 51, is selected and output, and conversely, a “0” signal is input to the select terminal SLT. If so, the data input to the input terminal B side, that is, the count value of the counter 52 is selectively output. The comparator 54 compares the data input to the input terminal A side, that is, the count value of the counter 51, and the data input to the input terminal B side, that is, the count value of the counter 52, and if they are the same, the output terminal A =B
Therefore, if the value on the input terminal A side is large, the output terminal A
>B, and if the value on the input terminal B side is large, a signal of "1" is output from the output terminal A<B. Each output terminal A=B, A> of the comparator 54
B, the output of A<B is the corresponding AND gate 55,
56, 57, and each AND gate 55, 5
The falling signal 40S from the falling detection circuit 40 is input to each of 6 and 57, respectively. Therefore, at the time when the falling signal 40S is input to the AND gates 55, 56, and 57, only those to which the "1" signal is input from the comparator 54 output a "1" signal. An AND gate 56 is connected to the set terminal S of the flip-flop circuit 58.
The output of the AND gate 57 is input to the reset terminal R. The output from the output terminal Q of the flip-flop circuit 58 is input to the select terminal SLT of the comparator 53. By doing this, at the time when the falling detection signal 40S is output, the counter 5
If the count value of 1 is larger than that of the counter 52, the flip-flop circuit 58 is set and "1" is applied to the select terminal SLT of the data selector 53. Output the count value of 51. Conversely, if the count value of the counter 52 is larger than that of the counter 51 at the time when the rising edge detection signal 40S is output, the flip-flop circuit 58 is reset and "0" is applied to the select terminal SLT of the data selector 53. Therefore,
The data selector 53 outputs the count value of the counter 52 input to the input terminal B. Note that if the count values of the counters 51 and 52 are the same, there is no change in the output of the flip-flop circuit 58, and the data selector 53 selects the previously selected counter 51,
The count value of one of 52 is output.

The flip-flop circuit 59 is an AND gate 5
The outputs of the AND gates 5 and 56 are input to the set terminal S via the OR gate 60, and the output of the AND gate 57 is input to the reset terminal R. Then, the output of the output terminal Q is inputted to the one shot pulse generation circuit 61 via the AND gate AND2, and further this circuit 61
The pulse signal created by the OR gate 62
The signal is applied to the clear terminal CLR of the counter 52 via the counter 52. The output of the negative output terminal of the flip-flop circuit 59 is input to the one-shot pulse generation circuit 63 via the AND gate AND1, and the pulse signal generated by this circuit 63 is input to the clear terminal CLR of the counter 51 via the OR gate 64. so that it is applied to and,
Falling signal 4 for AND gates AND1 and AND2
Make sure to input 0S. The output of the NOT circuit NOT is input to the count input terminals CK of the counters 51 and 52 via AND gates 65 and 66, respectively. The output from the output terminal Q of the flip-flop circuit 59 is input to the AND gate 66 via the delay circuit 67, and the output from the output terminal is input to the AND gate 65 via the delay circuit 68. In this way, if one or both of the AND gates 55 and 56 outputs a signal, that is, if the count value of the counter 51 is greater than or equal to the count value of the counter 52, the flip-flop circuit 59 is set, and the counter 52 is cleared by the output from the output terminal Q. Conversely, if the count value of the counter 52 is larger than the count value of the counter 51, the flip-flop circuit 59 is activated by the output of the AND gate 57.
The counter 51 is reset and cleared by the output from the output terminal. That is, counter 5
The maximum value up to now is stored in either one of 1 and 52, and the other count value smaller than this is cleared. Further, by setting the flip-flop circuit 59, the AND gate 66 is opened and the AND gate 65 is closed after the time set by the delay circuits 67 and 68 has elapsed. Conversely, when the flip-flop circuit 59 is reset, the delay circuits 67,
After the time period 68 has elapsed, AND gate 66 is closed and AND gate 65 is opened. Note that the delay circuits 67 and 68 are provided to prevent the cleared counter signals from being input while the counters 51 and 52 are being cleared. In short, with this configuration, at a certain point in time, one of the AND gates 65 and 66 is open, and the corresponding counters 51 and 52 are open.
One of them counts the signal from the NOT circuit NOT.
Then, at the time of generation of the falling signal 40S, the counter 5 on the side having a smaller count value as a result of the comparison
The contents of counters 1 and 52 are cleared, and almost at the same time, the AND gate 6 on the side corresponding to the counters 51 and 52 is cleared.
5 and 66 are opened, and then the counters 51 and 52 on the cleared side start counting.

The junction end detection circuit AX includes a counter 71, a register 72, and a register control circuit 70.
The counter 71 counts the number of input pulses to its count input terminal CK, and stores the value in the register 72.
Enter. The register 72 temporarily stores the input from the counter 71 at the fall of the signal to the load terminal L, and outputs the stored contents. register 72
The fall of the signal to the load terminal L occurs when the comparison result of the comparator 54 moves from the output terminal A>B to the output terminal A<B, or from the output terminal A<B to the output terminal A>B. Let it happen. However, in the initial state, output terminal A = B to output terminal A.
The same applies when moving to >B. These are performed by the register control circuit 70. FIG. 25 shows a specific example of the register control circuit 70, and the circuit 70 outputs the output of the AND gate 56 corresponding to the output terminal A>B of the comparator 54 and the AND gate corresponding to the output terminal A<B. gate 57
The function is realized by inputting the output of Therefore, the RS flip-flop circuit 73,
74, D-type flip-flop circuits 75 and 76, an OR gate 77, and a one-shot pulse generation circuit 78. The output from the AND gate 56 is input to the set terminal S of the flip-flop circuit 73 and the reset terminal R of the flip-flop circuit 74. and gate 57
The output from the flip-flop circuit 73 is input to the reset terminal R of the flip-flop circuit 73 and the set terminal S of the flip-flop circuit 74. Input terminals D of the flip-flop circuits 75 and 76 are connected to the power supply V, that is, a signal of "1" is always input to the terminal D. The output of the flip-flop circuit 73 is input to the clock terminal CK of the flip-flop circuit 75, and the output of the flip-flop circuit 74 is input to the clock terminal CK of the flip-flop circuit 76. The outputs of the flip-flop circuits 75 and 76 are connected to an OR gate 77.
Further, the output of this OR gate 77 is sent to the load terminal L of the register 72 as a register control signal RCS via a one-shot pulse generation circuit 78.
. Note that the output of the one-shot pulse generating circuit 78 is simultaneously applied to the clear terminals CLR of the flip-flop circuits 75 and 76.
With this arrangement, when either one of the AND gates 56, 57 outputs a signal, the signal is sent to the set terminal S of the flip-flop circuits 73, 74.
The side that is input to is set, and the other side is reset. As a result, one of the flip-flop circuits 75 and 76 on the set side is set to "1", and accordingly, the one-shot pulse generating circuit 75 generates the register control signal RCS based on the output of the OR gate 77. Furthermore, both flip-flop circuits 75 and 76 are cleared by this signal RCS and return to their initial states.

The arithmetic processing unit CPU is connected to the video storage unit via the reading circuit R and further via the processing data creation circuit LC.
Import various data necessary for judgment from IPM,
This is for determining the quality of the joint 5, and the case where a microcomputer is used is shown. A microcomputer executes processing, calculations, etc. according to a program stored in advance in a program storage device. FIG. 26 is a flowchart showing an outline of the program. In this figure, the arithmetic processing section CPU first performs initial settings of each section in step A. For example, this may be to clear a data storage section that temporarily stores data taken in from the processing data creation circuit LC, or to clear a data storage section that stores intermediate results of calculations or the like. In the next step B, the video storage unit IPM
The joint data shown in Fig. 22 in each row of
lx and junction end data Ax are read via the reading circuit R and the processing data creation circuit LC, and stored in a predetermined area of the data storage section. In the next step C, various data necessary for determining the quality of the joint 5 are calculated from the joint data lx and joint end data Ax of each row stored in the data storage section.
In the following explanation, each data will be defined as follows. That is, as shown in FIG.
In correspondence with the figure, the junction data lx indicates the length of the junction 5 in a given row, that is, the number of bits, and the junction data Ax indicates the length from the left end of the row to the right end of the junction 5, that is, the number of bits. Show the number. Amini indicates the smallest numerical value among the joint end data Ax, and lmini indicates the smallest numerical value among the joint data lx. Note that lmini eventually matches the diameter of the lead wire 4. lc indicates the length from the left end of the row to the center C of the lead wire 4, that is, the number of bits. lt is the length of the part where the length of the joint part 5 is 1.2lmini or more,
In other words, it indicates the number of bits. Further, within the range of lt, the area to the left of the center of the lead wire 4 of the joint 5, that is, the total number of bits, is ΣA, and similarly, the right side is ΣB, and the area of the joint 5 within the range of lt,
That is, let the number of bits be Σlx. Note that, as is clear from this figure, Σlx is the sum of ΣA and ΣB. From this, in step C described above, Amini, lmini, and Σlx are calculated. and,
Subsequently, based on these data, in step D, the quality of the joint portion 5 is determined.

The arithmetic processing unit CPU outputs the initial clear signal ICL and clock generation command signal at the appropriate timing shown below.
CLI is output, and a signal from the overflow terminal OFL of the clock generation circuit 30 for one line and the processing data creation circuit are output at appropriate timings shown below.
By inputting the junction data lx and the junction end data Ax from the LC, the above calculations, processes, etc. are executed. Note that the initial clear signal ICL from the arithmetic processing unit CPU is the clear terminal of the OR gates 62 and 64 and the counter 71 of the processing data creation circuit LC.
Input to CLR.

Figures 28, 29, 30, 31, 32, 33, 34, and 35 are 26
Step B, Step C, Step D in the diagram
This is a detailed flowchart, and the overall operation will be explained below with reference to this figure. In Figure 28,
In step B, first, the counter CNT is set to 0 in step B1. This counter
The CNT is created in software and is associated with a predetermined address in the data storage unit.
This counter CNT is a row counter that counts each row of the video storage unit IPM. Next, in step B2, the processing data creation circuit LC is initialized.
That is, this applies the initial clear signal ICL to the OR gates 62, 64 and counter 7 of the circuit LC.
1 clear terminal CLR. This results in
This is done by clearing the counters 51, 52, and 71. Subsequently, in step B3, a clock generation command signal CLI is applied to the readout circuit R, and in the next step B4, 1 is added to the counter CNT. In step B3, when the clock generation command signal CL1 is applied to the readout circuit 6, the circuit R is activated to the video storage section.
Read out the memory contents of the first line of IPM sequentially. Then, in step B5, the output of the overflow terminal OFL of the counter 35 is read, and in step B6
At this point, it is determined whether the output of the overflow terminal OFL is "1", that is, whether the readout circuit R has finished generating clock pulses for one row of the video storage unit IPM. Here, step B continues until the overflow signal is output from the overflow terminal OFL.
5 and B6 are repeated. When an overflow signal is confirmed in step B6, the joint data lx and joint end data Ax are read from the processing data creation circuit LC and stored in the data storage section, respectively, in step B7. Next, in step B8,
It is determined whether the counter CNT has scanned n, that is, the image storage unit IPM has been scanned to the last line, and the process continues from step B2 to step B8 until this condition is satisfied.
It is repeated until the last line is scanned, and the counter is
When the content of CNT reaches n, proceed to step C.

In step B3, the clock generation command signal is
When CLI is input to the readout circuit R, the readout circuit R sequentially reads one line of the video storage unit IPM from the left and inputs it to the processing data creation circuit LC.
The flip-flop circuit 59 of the circuit LC is in either the set or reset state when the power is turned on. Now, the flip-flop circuit 59 is in the set state, and the series of data shown in FIG.
It is assumed that the data is read out according to the clock of the row clock generation circuit 30. Since flip-flop circuit 59 is in the set state, AND gate 65 is open and AND gate 66 is closed. Therefore, the counter 51 sequentially counts the number of "1"s input through the NOT circuit NOT. (See FIG. 22b) At the same time, the counter 71 clocks the clock generator 3 for one row.
The read clock pulses RCL from 0 are sequentially counted. From the 5th bit to the 6th bit, the data falls from "1" to "0". Then, the falling detection circuit 40 detects this and the falling signal 40S
Output. At this point, the count value of the counter 51 is "2", the count value of the counter 52 is "0", and the count value of the counter 71 is "5". Therefore, the AND gate 56 outputs a signal, and the selector 53 outputs the count value of the counter 51 "2".
Then, by setting the flip-flop circuit 59, the AND gate 65 is closed and the AND gate 66 is closed. In addition, the register control circuit 7
8 outputs a register control signal RCS, and the count value "5" of the counter 71 is set in the register 72. Furthermore, since signals are continuously output from the video storage unit IPM, the counter 52 counts subsequent "1"s. Then, when the data falls from "1" to "0" at the Pth bit, the detection circuit 40 detects this and outputs a falling signal 40S. At this point, the count value of the counter 51 becomes "2," the count value of the counter 52 becomes "lx," and the count value of the counter 71 becomes "Ax." Then, due to the generation of the falling signal 40S, the count value "lx" of the counter 52 is larger than the count value "2" of the counter 51, so the flip-flop circuit 58 is reset, and the selector 53 resets the count value of the counter 52. "lx" is output, and the flip-flop circuit 59
is reset, AND gate 66 is closed, AND gate 65 is opened, and counter 51 is cleared. Further, a register control signal RCS is generated, and the count value "Ax" of the counter 71 is set in the register 72. Subsequently, the counter 51 counts the number of "1"s from the NOT circuit NOT. After that, when the data falls from "1" to "0" again at the g-th bit, the falling detection circuit 4
0 detects this and outputs a falling signal 40S. At this point, the count value of the counter 51 is "3",
The count value of the counter 52 is "lx", and the count value of the counter 71 is "g". Then, the falling signal 40
Due to the occurrence of S, the count value "lx" of the counter 52 is larger than the count value "3" of the counter 51, so the flip-flop circuit 58 is reset again, and the selector 53 selects the count value "lx" of the counter 52.
will continue to be output. Furthermore, since the flip-flop circuit 59 is reset again, the AND gate 66 is closed, the AND gate 65 is opened, and the counter 51 is cleared. However, in this state, the register control signal RCS is not generated from the register control circuit 73, and the register 72 is set to "Ax".
continue to hold. Thereafter, one row of data is read out by the action of the readout circuit R up to the m-th bit, but there is no change in "lx" output from the selector 53 and "Ax" output from the register 72.
Therefore, in step B7, the arithmetic processing section
CPU accurately displays junction data lx, junction end data
Ax can be read.

As is clear from this explanation, since the processing data creation circuit LC is configured as shown in FIG. Even if the pattern appears black, only the joint 5 can be counted effectively without miscounting.This is because the width of the joint 5 is larger than that of other patterns, scratches, etc. Based on this idea.

Thereafter, by repeating steps B2 to B8, the joint data lx and joint end data for each row up to the nth row of the video storage unit IPM are
Ax is stored in the data storage unit in the arithmetic processing unit CPU.

When the above processing is completed, the arithmetic processing unit CPU calculates various data necessary for determining the quality of the joint 5 based on the contents stored in the data storage unit. That is, as shown in FIG. 29, in step C1, lmini and Amini are searched.
This sequentially reads lx of each row from the data storage unit, compares them sequentially, xminiizes the smallest value among them, and calculates the corresponding Ax.
This value is stored as Amini at a predetermined address in the data storage section. In the following step C2, the length lc of the lead wire 4 to the center C is calculated. This is clear from Figure 27,
This is done by subtracting lmini from Amini.
In step C3, initial setting of counter x for sequentially reading all rows of junction data lx, and
A counter y for counting the number of junction data lx larger than lmini is initialized. In the next step C4, the joint part data lx of the joint part 5 is compared with lmini. This is a step for extracting the junction data lx of the junction 5 that can be approximated by a quadratic polynomial. And the junction data lx is
If it is not larger than lmini, proceed to step C7.
If it is larger, proceed to step C5 and set the counter y to 1.
The value of the counter y is further stored in the address n1 of the data storage unit. In the next step C6, lx is divided into left and right sides from the center line lc, the left side from the center line lc is set as l1y, the right side is set as l2y, and after calculation,
l1y and l2y are stored in the data storage section. This is because when calculating the distortion factor, if only the joint data lx is corrected, an accurate value cannot be obtained, so each of l1y and l2y is corrected. Next step C
7, the counter x is compared with n in order to check whether the junction data lx has been read out for all rows. If all rows have not been read out, the counter x is incremented by 1 in step 8.
Return again to step C4. If completed, the process of actually correcting the data is executed. First, in step C9, the counter y is initialized in order to sequentially calculate the first-order difference value Δl1y. Next, in step C10, a first-order difference value Δl1y is calculated, and in step C11, a comparison is made to see if all the first-order difference values Δl1y have been calculated. Here, n1 is
Longer than lmini, that is, junction data of junction 5
is the number of lx. If all first-order difference values Δl1y have not been calculated in step C11, step C
At 12, count up the counter y by 1,
The process returns to step C10 again. Once completed, the next step is to calculate the second-order difference value Δ ² l1y. first,
In step C13, initial settings are made to sequentially calculate the second-order difference values Δ ² l1y. Next, in step C14, the calculation of the second-order difference value Δ ² l1y is executed, and in step C15, it is compared and checked to see if the calculation of all the second-order difference values Δ ² l1y has been completed. Since the total number of first-order difference values Δl1y is (n1-1), the value of the counter y is compared with (n1-2) to determine whether or not the process has ended. If the process has not been completed, the counter y is counted up in step C16, and the process returns to step C14. When the process is completed, the process moves to the step of determining the allowable range of the second-order difference value Δ ² l1y. For example, in the histogram of FIG. 14, the second-order difference values Δ ² la, Δ ² lb, which are expected to be normal,
Tolerance of second-order difference value Δ ² l1y to distinguish between group A of Δ 2 lc, Δld, and Δ ² le and group B of second-order difference values Δ ² lf, Δ ² lg, and Δ ² lh that are expected to be ^abnormal . This is the process of determining the range. The characteristics of this histogram are that group A has a higher frequency than group B, and group A shows a certain probability distribution. In this example, the probability distribution of group A is a normal distribution, and the allowable range is set to three times the standard deviation 6 of the distribution from the center value Δ ² ls of the distribution in FIG. In other words, the lower limit of the allowable range is (Δ ² ls−36) and the upper limit is (Δ ² ls+36). This allows most of the distribution, approximately 99.7%, to be within the acceptable range. Note that this is about an ideal regular distribution. In this embodiment, sampling of data for determining the center value Δ ² ls and standard deviation 6 is performed as follows. For example, in the histogram of FIG. 14, first, the second-order difference value Δ ² lc indicating the highest frequency is searched, and the frequency is stored in the data storage unit. Next, the second-order difference value Δ ² lb having the highest frequency other than the second-order difference value Δ ² lc is searched for, and that frequency is added to the frequency of the previous second-order difference value Δ ² lc. Thereafter, the calculations are performed in the same manner, and the calculation is stopped when the ratio of the added frequencies to the total frequency exceeds a certain value. Then, the average value Δ ² ls and standard deviation 6 of group A are approximately determined based on the second-order difference value searched until it exceeds a certain value and the corresponding frequency. The process will be explained below with reference to the flowchart of FIG. 30 again. First, in step C17, f1 is initialized for frequency addition, m is initialized for storing the maximum standard value Δ ² l'm, and its frequency fm. Next, in step C18, the most frequent value Δ ² l'm' of the second order difference value Δ ² l1y and the frequency fm are searched and further stored in the data storage section. In step C19, the frequency fm is integrated, and in the next step C20, it is determined whether the ratio of the integrated value to the total number has exceeded a certain value. In this example, the constant value is 90
It is expressed as [%]. If it does not account for 90% of the total number, go to step C21 and remove the most frequent value Δ ² lm' from among the second-order difference values Δ ² l1y.
In step C22, m is counted up and the process returns to step C18. If the total number is 90
[%] or more, the average value Δ ² ls of Δ 2 lm' is calculated in step C23 in FIG ^{. 31, and the standard deviation 6 of Δ 2 lm} ' is calculated in the next step C24. In the next step C25, the lower limit Δ ² ld and upper limit Δ ² lu of the allowable values are calculated, and then the process moves to the step of actually correcting l1y. The second-order difference value Δ ² l1y is influenced by the data at the three points l _1y+2 and l _1y+1 , as is clear from the diagram showing the difference in FIG. 37. Therefore, even if an abnormality is discovered, 3
I don't know which of the points is the root cause of the abnormality. Therefore, in this embodiment, when examining y toward the final value (n _1-2 ) for the second-order difference value Δ ² l1y,
l _1y+2 was determined to be the fundamental abnormality, and when examining y toward the first, l ¹ y was determined to be the fundamental abnormality. In other words, the other two points are determined to be normal. Therefore, it is necessary to select at least two consecutive points as the reference l ₁ y.

In this embodiment, first, the second-order difference values Δ ² l ₁ y are checked, and J second-order difference values Δ ² l ₁ y are consecutively determined.
If it is within the allowable limit, it is determined that l ₁ y, which is the basis for calculating the J second-order difference values Δ ² l ₁ y, is normal.

Now, if the second-order difference value Δ ² lp to Δ ² l (p+J− ₁ ) is continuously within the allowable limit, first y is investigated starting from (p− ₁ ) toward the first one. If a second-order difference value Δ ² l ₁ y that is outside the allowable range appears, l ₁ y is determined to be fundamentally abnormal, and l ₁ y is corrected and corrections made accordingly as follows.

First, the second-order difference value Δ ² l ₁ y is set to the average value Δ ² ls, and Δl ₁ y is thereby corrected as shown in equation (8).

Δl _1y = Δl _1y+1 −Δ ² ls (8) Then, the fundamental abnormality l ₁ y is corrected as shown in equation (9).

l _1y = l _1y+1 −Δl _1y (9) Furthermore, by correcting l ¹ y, Δ _1y-1 is also corrected as shown in equation (10).

Δl _1y-1 = l _1y −l _1y-1 ………(10) (y≧2) Then, by correcting Δl _1y and Δl _1y-1 , Δ ² l _1y-1 can be changed as shown in equation (11). Correct it to

Δ ² l _1y-1 = Δl _1y − Δl _1y-1 ………(11) (y≧2) Finally, by correcting Δl _1y-1 , Δ ² l _1y-2 becomes
Correct as shown in equation (12).

Δ ² l _1y-2 = Δ _1y-1 −Δl _1y-2 ………(12) (y≧3) After checking up to the second-order difference value Δ ² l ₁₁ , next y is the final one from (P+J). Δ ² l ₁ y toward (n ₁ −2)
I will investigate. Then, when Δ ² l _1y that is outside the allowable range appears, l _1y+2 is determined to be a fundamental abnormality, and the following is done.
l Make the correction for _1y+2 and the corresponding corrections.

First, Δ ² l _1y is set to the average value Δ ² ls, and Δl _1y+1 is thereby corrected as shown in equation (13).

Δl _1y+1 = Δl _1y + Δ ² ls (13) Then, the fundamental abnormality l _1y+2 is corrected as shown in equation (14).

l _1y+2 = l _1y+1 + Δl _1y+1 ………(14) Furthermore, by correcting l _1y+2 , Δ _1y+2 becomes (15)
Modify it as shown in the formula.

Δl _1y+2 = l _1y+3 −l _1y-2 ………(15) (y≦n ₁ −3) And by correcting Δl _1y+1 and Δl _1y+2 , Δ ² l _1y+1 Correct as shown in equation (16).

Δ ² l _1y+1 = Δl _1y+2 − Δl _1y+1 ………(16) (y≦n ₁ −3) Finally, by correcting Δl _1y+2 , Δ ² l _1y+2 becomes ( 17) Correct as shown in the formula.

Δ ² l _1y+2 = Δl _1y+3 −Δl _1y+2 (17) (y≦n ₁ −4) The above will be explained again using the flowchart of FIG. 31. First, a process is performed in which a portion where J second-order difference values Δ ² l ₁ y consecutively fall within the allowable range is searched for when y is set to 1. In step C26, y is initialized, and in step C27, a counter Z for counting the number of Δ ² l ₁ y that falls within the allowable range is initialized. In the next step C28, y is counted up, and in step C29 it is determined whether Δ ² l ₁ y is within the allowable range.
If not, the process returns to step C27; if it is, the process proceeds to step C30, where Z is counted up, and the process proceeds to step C31. Here, it is determined whether all second-order difference values Δ ² l ₁ y have been read out.
If all the numbers have been read out, it is assumed that the reference l ₁ y has not been found, and the process proceeds to step C32, where a process is executed to notify the outside that correction is impossible. If all the numbers have not been read out, the process advances to step C33 to check whether Z has reached the specified number. In this embodiment, the specified number J is five. Z is 5 at step C33
If this has not been reached, the process returns to step C28, and if it has been reached, the process proceeds to step C34 in FIG. In step C34, the final y of Δ ² l ₁ y that falls within the allowable range is stored at address n ₂ of the data storage section. In the next step C35, 5 is subtracted from the current y in order to bring y to the position before the first one within the tolerance range. Next step C
36, the second-order difference value Δ ² l ₁ y is the first (y=1)
It is determined whether or not it is necessary to make corrections toward the future. Here, if y is not 0, it is determined that correction is necessary, and the process moves to correction processing. First, the 33rd
In step C44 of the figure, it is checked whether Δ ² l ₁ y is within the allowable range, and if it is, step C44 is performed.
The process moves to step 50, and if it is not included, correction processing is performed. First, in step C45, Δ ² l ₁ y is set to the average value Δ ² ls
By doing so, Δl ₁ y and further l ₁ y are corrected.
Next, if y is 2 or more in step C46, Δl _1y-1 and Δ ² l _1y-1 are further corrected in step C47, and if y is not 2 or more, it is determined that y is 1, and the process goes to step C37. Move. After modifying in step C47,
The process moves to step C48, and if y is 3 or more, further correction of Δ ² l _1y-2 is performed in step C49. 3
If not, the process proceeds to step C50 and counts down y. After correction in step C49, the process also proceeds to step C50. In the next step C51, it is determined whether y has been checked up to the first position. If not completed, step C4
Return to 4 again. If the process has been completed, the process moves to the next step C37 in FIG. If y is found to be 0 in step C36, that is, five y's from the first value are within the allowable range, the process also proceeds to step C37. In the next step C37, 1 is added to the content of the address _n2 , which _is set as y, and in the next step C38, it is checked whether ^Δ2l1y is within the allowable range.
If it is found, the process advances to step C42; if it is not found, correction processing is performed. First, step C3
By setting Δ ² l _1y to the average value Δ ² ls in step 9, Δl _1y+1 ,
l _1y+2 is corrected, and if y is less than or equal to (n ₁ -3) in the next step C40, it is determined that all Δ ² l _1y have been read out, and the process proceeds to step C54, and if it is less than or equal to that, the process proceeds to step C41. Proceed and correct Δl _1y+2 and Δ ² l _1y+1 . Furthermore, if y is less than (n ₁ -4) at step C52, the process proceeds to step C53, where Δ ² l _1y+2 is corrected. If it is less than (n ₁ - 4), step C
Proceed to 43. If it is within the allowable range in step C38, it is determined in step C42 whether or not all readings of Δ ² l _1y have been completed, and if so, the process advances to step C54, and if not, the process advances to step C43.
The process advances to step C38, increments y by 1, and returns to step C38.

When the reading of all second-order difference values Δ ² l _1y is completed, the process advances to step C54. In this step, the same corrections made for l ₁ y are made for l ₂ y.

When the above processing is completed, the arithmetic processing unit CPU calculates various data necessary for determining the quality of the joint 5 based on the contents stored in the data storage unit. First, in step C55, each address of the data storage unit storing the joint area Σlx, the joint effective length lt, and the area ΣB is cleared in order to execute the following steps. In the next step C56, l ₁ y and l ₂ y of each row are read out one by one. In the following step C57, this l ₁ y,
Add l ₂ y and use this as junction data lx. Then, in step C58, the lx is 1.2.
It is determined whether or not it is larger than lmini, and if it is larger, the value of lx is added to the address set as Σlx in step C59. Then, the value of (l ₂ y+ΣB) is further added to the address set as ΣB, and 1 is added to lt set as the storage address for the length of the joint portion 5. In step C58, if lx is not greater than 1.2·lmini, the value in this row is ignored and the process proceeds to step C60. In step C60, steps C56 and C5 are performed for each row.
7, C58, C59 are executed or not, and if not, steps C56, C59 are executed for the next line.
57, C58, and C59. That is, steps C56, C57, C58, and C59 are repeated n times in each row, as is clear from FIG. 20. In step C60, when it is confirmed that the processing of each row has been completed,
Proceed to step D. At this point, the address Σlx where the junction area is stored is the junction lx.
The number of bits corresponding to , that is, the numerical value in the storage section is stored. Similarly, the corresponding bit values are stored in lt and ΣB.

In step D, a determination process is executed based on the various data calculated above. That is, in FIG. 35, the area increase rate Wa is calculated in step _D1 . This is done based on equation (1). The result is then stored at a preset address as Wa in the data storage section. step
In D ₂ , Σlx calculated in step C above,
ΣA is calculated from ΣB and stored in the data storage unit. Based on the above calculation results, the distortion factor Wc is then calculated. For this calculation, first
At _D3 , the magnitudes of ΣA and ΣB are compared, and based on the magnitude, a distortion factor Wc is calculated at either step _D4 or step _D4 ', and this value is stored in the data storage section. The following are the steps for making the actual determination. In Step _D5 , the area increase rate Wa stored in the data storage unit is retrieved, and the area increase rate Wa, the allowable minimum area increase rate w ₁ , and the allowable maximum area increase rate Compare each with ₂ ,
If the area increase rate Wa is within this range, step
The process proceeds to step _D6 , and if it is outside this range, the process proceeds to step _D7 ', where it is determined that the product is defective. For example, in FIG. 7, the allowable minimum and allowable maximum area increase rates w ₁ and w ₂ are 30 [%], 55 [%], etc. In step _D6 , the distortion factor Wc is determined. That is, the distortion factor Wc stored in the data storage section is extracted and compared with the allowable maximum distortion wc, and if the distortion factor is within this range, the product is determined to be non-defective in step _D7 .
If the product is outside this range, it is determined to be defective at step _D7 '. The maximum allowable distortion factor wc is, for example, 20% in FIG. 9. In steps D ₇ and D ₇ ′, the arithmetic processing unit CPU outputs a signal corresponding to the judgment result to the outside, and for example, in the process of step D ₇ ′, the signal is used to issue an alarm, or to mark the product as defective. It is used effectively, such as by performing control processing such as removing it from the line. Also, with the signal from step _D7 ,
The product is sent to the next stage, and the joints of the next product are inspected. The series of tests is completed in the above manner.

In the above embodiments, the case where the readout circuit R, the image storage unit IPM, and the processed data creation circuit LC are arranged around the arithmetic processing unit CPU in order to improve the inspection speed has been described. It can be omitted if the specifications allow it. That is, the signal from the TV camera 20 may be binarized by the binarization circuit BC, and this may be directly taken in by the arithmetic processing unit CPU, thereby executing each process. Furthermore, a video storage unit IPM may be added to this, and each process may be executed in correspondence with the video storage unit IPM and the arithmetic processing unit CPU.

Although the installation position of the TV camera 20 has not been specifically explained, it may be any position where the joint portion 5 can be imaged, and for example, it may be installed on the arm of a Honging device. Also,
In the above embodiment, when the TV camera 20 is arranged at the position of the joint 5 so that the joint 5 is parallel to the edge of the image plane, that is, the center line of the lead wire 4 is parallel to the imaging end. However, the present invention is not limited thereto. That is, even if the joint portion 5 is tilted with respect to the edge of the imaging plane, this can be detected and therefore corrected.

Furthermore, in the above embodiments, a case has been described in which a bonded portion bonded by a wire bonding device employing an ultrasonic method is inspected, but the present invention is not limited to this, and the present invention is not limited to this. The present invention can also be applied to the inspection of joints formed by wire bonding equipment employing thermocompression bonding methods such as those typified by the method. Furthermore, the present invention is not limited to the bonded portion formed by pressure bonding such as the above-mentioned ultrasonic bonding or diffusion bonding typified by thermocompression bonding. i.e. fusion welding,
It can be widely used to inspect joints formed by pressure welding, welding such as brazing, or other joining means. Further, in the embodiment, the joint portion between the lead wire 4 and the semiconductor integrated circuit element or the post 3 has been described, but in the present invention, the members are not limited to these, and furthermore, the members are not limited to these. There is no limit to the number of

Furthermore, in the embodiment, the width data of the joint part 5 can be approximated to a second-order polynomial, and the second-order differentiated value of this second-order polynomial is used to correct the width data of the joint part 5 by focusing on a constant. However, a case has been described in which a location where the second-order differential value changes significantly is determined to be abnormal, and correction is performed based on this. However, the present invention is not limited to this, and a second-order polynomial may be obtained by the least squares method, and correction may be performed based on this. Also, other mathematical methods may be used.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, it is possible to inspect a joint in a non-contact manner without applying external force to the joint, and the inspection accuracy can be improved. You can get the equipment.

[Brief explanation of the drawing]

FIG. 1 is a diagram for explaining a conventional inspection device.
FIG. 2 is a plan view showing an example of the joint, FIG. 3 is a side view of the same, and FIG. 4 is a plan view showing another example of the joint.
FIG. 5 is a block diagram showing one embodiment of the device of the present invention, FIG. 6 is a plan view of a joint portion for explaining the present invention, FIG. 7 is a diagram for explaining the present invention, and FIG. 8 is a diagram for explaining the present invention.
The figures are a plan view of a joint for explaining the present invention, FIG. 9 is a diagram for explaining the present invention, FIG. 10 is a plan view of a joint for explaining the present invention, and FIG.
Figures 12, 13, and 14 are diagrams for explaining the present invention, Figure 15 is an explanatory diagram showing the principle of a television camera, and Figure 16 is a diagram showing the group shape of the bonding device. , FIG. 17 is a cross-sectional view of the joint, FIG. 18 is a diagram showing one example of imaging, and FIG.
FIG. 9 is a circuit diagram showing an example of a binarization circuit, FIG. 20 is a diagram showing an example of binarized imaging, FIG. 21 is a block diagram showing an example of a one-line clock generation circuit, and FIG. FIG. 23 is a block diagram showing an example of the falling detection circuit; FIG. 24 is a time chart showing the operating waveforms of each part in FIG. 23; FIG. 25 is register control. A block diagram showing an example of the circuit, FIG. 26 is a flowchart showing an example of the control procedure of the arithmetic processing section, FIG. 27 is an explanatory diagram for explaining the operation of the arithmetic processing section, FIGS. 28, 29, Figure 30, Figure 31,
Figures 32, 33, 34, and 35 are
A flowchart showing details of the processing in FIG. 6,
FIGS. 36 and 37 are explanatory diagrams for explaining the operation of the arithmetic processing section. 5: Joint part, IP: Imaging means, 20: Television camera, PC: Processing means, BC: Binarization means, IPM: Image storage means, R: Reading means, LC:
Processing data creation circuit, LX: joint detection means,
AX: Junction end detection circuit, 40: Fall detection circuit, CPU: Arithmetic processing unit, BC, IPM, R, LC,
Steps B1-B8: Extraction means, Steps C1-
C38: Determination means, Steps C39-C54: Correction means, Steps C55-C60, Step D:
Good/failure judgment means.

Claims (1)

[Scope of Claims] 1. Imaging means that images the joint portion of the joining member and divides the image formed on the imaging surface into a plurality of lines, sequentially operates each row, converts the image into an electrical signal, and outputs the image; Extraction means for extracting width data of a joint portion in each row from a video signal from the means, and a determination for determining whether or not correction is necessary for the width data in each row extracted by the extraction means in relation to the width data of other rows. correction means for correcting the width data of the row when the judgment means determines that correction is necessary; A joint inspection device comprising a quality determining means for determining quality. 2. The joint inspection device according to claim 1, wherein the joint member is a lead wire. 3. The joint part inspection device according to claim 1, wherein the joint part is a part where the joint member is plastically deformed by the joining means with respect to the mating member. 4. The joint part inspection device according to claim 1, wherein the joint part is formed at a portion where joining members are joined by welding. 5. The joint inspection device according to claim 1, wherein the joint is formed at a portion where the lead wire is joined to a mating member by a wire bonding device. 6. The joint inspection device according to claim 1, wherein the imaging means includes a solid-state imaging device. 7. The joint inspection device according to claim 1, wherein the extraction means includes binarization means for binarizing and outputting the video signal from the imaging means for each pixel. 8. Claims in which the extraction means comprises an image storage means that temporarily stores the output of the binarization means pixel by pixel, and binarizes and stores the resulting image formed on the imaging surface of the imaging means. 8. The joint inspection device according to item 7. 9. The extracting means extracts the width data of each line of the joint part based on the stored content of the video storage means, and the determining means and the correction means determine the width data of the joint member based on the width data of each row. A joint inspection device according to claim 8. 10 The extraction means includes processing data creation means for creating data necessary for extracting the width of the joint member from the memory content of the video storage means, and calculates the width of the joint part in each row based on the output data from the processing data creation means. 9. The joint inspection device according to claim 8, which extracts data. 11. The joint inspection device according to claim 10, wherein the extracting means includes reading means for sequentially reading out the stored contents of the video storage means. 12. Claim No. 1 characterized in that the video stored in the video storage means is divided into a plurality of lines each composed of a plurality of pixels, and the processing data creation means creates data necessary for processing for each row. The joint inspection device according to item 10. 13. The joint according to claim 11, wherein the video stored in the video storage means is divided into a plurality of rows each composed of a plurality of pixels, and the reading means reads out the stored content in units of rows. inspection equipment. 14. The joint inspection device according to claim 12, wherein the processing data creation means outputs the joint data on a line-by-row basis. 15. The joint inspection device according to claim 12, wherein the processing data creation means outputs width data of the joint and end data of the joint on a line-by-row basis.