JPH0146949B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a word-by-word erasing method for electrically programmable non-volatile memory cells having memory cells arranged in a matrix.

“IEEE Transactions on Electron de―
It is known to use floating gate memory cells in the construction of electrically programmable non-volatile memories, according to J. V. Vices, ED-24 [5] p. 606-610 (1977). This field effect transistor has a fully insulated floating memory gate and a controllable control gate stacked vertically over a channel section, with the control gate covering the entire channel section and the floating gate covering the entire channel section. It only covers part of it.
Errors when reading from memory cells with erased depletion characteristics are avoided by what is called a split gate structure. Charging of the floating memory gate is by channel injection. To do this, electrons are briefly accelerated in the channel and directed towards the memory gate by means of an auxiliary transverse electric field. Discharge (erase) of the floating gate is due to reverse tunneling of electrons that occurs under high voltage applied between the control gate and one diffusion region.

A word-by-word erasable non-volatile memory made using floating gate technology has already been proposed (see Japanese Patent Application Laid-Open No. 57972/1983). In this case, the charging and discharging of the floating gate is due to the direct transfer of electrons between the floating gate and the substrate, for which a strong electric field of appropriate polarity is applied between the floating gate and one of the diffusion regions.

In all known memory devices constructed with such memory cells, the erasing time is adjusted and fixed through an external time unit. This erasing time is selected to be sufficiently long, taking into account variations in erasing characteristics caused by manufacturing techniques, not only for cells on one chip but also for cells on chips belonging to different manufacturing charges. In addition, variations in erase time due to the time unit itself must also be taken into account. Therefore, in principle, it is inevitable that at least a portion of the memory cell transistor will be overerased to the depletion state. This overerased memory cell acts as an undesirable shunt for the selected memory cell transistor during a read. Therefore, as a general rule, memory cells of electrically erasable memories have an auxiliary selection transistor. The selection transistor can often be combined with the memory cell transistor to form a split-gate structure, but this poses manufacturing technical difficulties and lowers the manufacturing yield. In addition, long memory erasing times increase the risk of adjacent word interference, which causes a deterioration of the programming characteristics, especially in the case of memory cells that are programmed by channel injection. Furthermore, longer erase times reduce the number of possible write-erase cycles and shorten the lifetime of the memory.

It is an object of the present invention to avoid depletion states of the transistors of memory cells to be erased in a word-by-word electrically erasable non-volatile memory and to achieve the shortest erase time for each memory cell. It is to compose.

To this end, according to the invention, memory cells consisting of MOS transistors which can be programmed by changing the threshold voltage are arranged in a matrix, the gates of each memory cell transistor being connected row by row to a common gate conductor; The source and drain of each memory cell transistor are connected to a common source conductor and drain conductor for each column, and information is erased by applying an erase voltage to the memory cell transistor. The threshold voltage of the memory cell transistor is monitored for each column, and when the monitored threshold voltage reaches a value representing the erased state, the erase voltage is cut off for each column.It can be electrically reprogrammed. In the word-by-word erasing method of non-volatile memory cells, an erasing voltage is simultaneously applied to a predetermined number of memory cell transistors, and this predetermined number corresponds to the number of bits of one information word to be stored. The threshold voltage of the cell transistor is monitored by detecting the drain voltage of the memory cell transistor, and when the monitored drain voltage reaches a drain voltage value that is a measure of the threshold voltage representing the erased state, a predetermined value is detected. This is achieved by individually cutting off the erase voltage for those memory cell transistors that have reached the erased state.

There are no special requirements regarding the various circuit components used when carrying out the erasing method according to the present invention, and any circuit components may be used as long as they achieve their respective intended functions.

The memory according to the invention has the advantage that depletion states of the transistors of the memory cells to be erased can be prevented. Since the erased memory transistor does not reach a depletion state, the memory according to the invention allows the use of one-transistor memory cells, and the required area of the memory chip is reduced. The shortest erase time of the memory cell also minimizes oxide changes during erase, resulting in an increased number of write-erase cycles and a longer lifetime than conventional memory.

Furthermore, when the known semiconductor memory mentioned above is used outside the component unit, it is necessary to connect an external time unit as an auxiliary circuit, whereby the duration of the erasing process is preset for all memory cells. However, this results in various disadvantages as mentioned above. Since the invention makes it possible to omit such a time unit, no disadvantages can arise from using a time unit.

In the development of this invention, the erasing time of each memory cell is made variable by a control circuit connected in combination with the memory matrix, and the erasing voltage applied to the memory cells for controlling the erasing state of the memory cells is varied over time. A control readout is inserted between the pulse intervals. This allows the use of one transistor cell in the memory configuration. Further, by dividing the erase voltage into a series of pulses, heating of the crystalline substrate during erasing is reduced, thereby reducing damage. This advantage becomes more important as the erase current becomes larger and the heating caused by it becomes larger. Such erase currents are caused, for example, by undesirable through-discharge phenomena.

In a cell that does not have an erase area insulated from the channel area, for example, in the case of an n-channel memory cell, a high positive voltage must be applied to the source for erasing, and the source must be grounded for control read. It is not possible to perform control reads simultaneously. In the case of a p-channel cell, it is also impossible to simultaneously satisfy the two conditions because the sign of the applied voltage is simply reversed. On the other hand, dividing the erase voltage into a series of pulse voltages allows controlled reading during the pulse intervals. The control circuit connected in combination with the memory matrix must ensure that during the control read process, the absolute value of the threshold voltage V _T (“0”) of the memory cell is equal to or greater than the absolute value of the specified threshold voltage U _GL of the memory cell. When it becomes small (｜V _T (“0”)｜≦｜U _GL
|) It is advantageous if the erasure time of this memory cell expires.

In the case of an n-channel memory cell, if there is a relationship between the lower threshold voltage V _T (“0”) and the control read voltage U _GL such that U _GL > V _T (“0”) > O, the erased cell will deplete. state is never reached. To ensure this relationship, the length (duration) of each erase pulse is chosen such that the erase cells are cut off before reaching the depletion state for the duration of the erase pulse.

One embodiment of the invention provides for a variable erase time to be achieved by means of controlled readings performed simultaneously with temporally consecutive erase voltages, where the erase time of each cell is determined by its threshold voltage V _T (“ 0”) is
A control circuit is combinatorially connected to the memory cell matrix such that it terminates when U _GL is equal to or between U _GL and O.

Sequential erasure and simultaneous reading can be performed in floating gate memory cells. The cell has an erase window insulated from the channel region; for n-channel the source voltage is OV during the entire erase process, and a high positive voltage is applied to the isolated diffusion region within the erase window. This type of cell is known from the West German patent application publication no.
It is described in Publication No. 2643987.

Bitwise writes are of relatively little practical importance. During programming, all threshold voltages reach their final values gradually, their fluctuations are small and their exact values are not required. Excessive writing corresponding to over-erasing does not occur. The control for writing is as follows:
This is done in such a way that the external time unit is omitted and at the same time a certain minimum value for the state "1" is ensured.

It is advantageous if during the control readout during the erasing process the erased state is indicated by a fall in the absolute value |U _D | of the drain voltage.

The conductivity of a floating gate transistor varies depending on the state of charge of the floating gate. This change in conductivity can be used as a signal for the termination of the erasing process. If a certain read voltage is applied to the drain conductor connected on a bit by bit basis, the drain remains floating during the control read period during erasing, and is raised to a certain voltage when the transistor is sufficiently erased. In this case, it is assumed that a low gate voltage of approximately 0V is applied to the unselected memory cells so that they do not enter the depletion state. It is advantageous to connect the control circuit in combination with the memory cell matrix in such a way that the drain output signal indicating the end of the erasing process of a memory cell is used to interrupt the erasing voltage applied to this cell.

It is also advantageous to connect the gate conductors of the field effect transistors forming the memory cell word by word and their drain conductors bit by bit. When a memory cell with an isolated diffusion region within the erase window is used, the erase window conductor is always connected bit by bit and the source conductor is placed at ground potential. In cells without an isolated erase area, the source conductors are separated from each other on a bit by bit basis. Finally, a pre-given threshold voltage for control read during erase.
The control circuit is connected in combination to the memory cell matrix in such a way that the gate voltage required for U _GL and for reading the memory are derived from the same voltage divider, so that U _GL is always smaller than U _GR It is also advantageous to do so.

By this means, the gate voltage during reading
U _GR and erased state threshold voltage V _T (“0”), [V _T
Since a minimum interval is ensured between (“0”)>U _GR ], reliable reading is always possible. Differences in erase characteristics due to tolerances between memory cells within one memory do not affect read reliability, but only affect the duration of the erase process. In this case, since the unprogrammed state is precisely fixed relative to the read voltage, the width of the erase window, i.e. the difference between the gate voltage for control read during erase and the gate voltage for the programmed state "1". can be lowered. This allows for lower voltages during programming or extremely short programming times. Furthermore, it is also possible to place the electrical window within a predefined threshold voltage range.

Next, the present invention will be described in more detail with reference to examples. Although this embodiment and the drawings are directed to an n-channel memory cell, they can also be applied to a p-channel memory cell by changing the sign appropriately.

FIG. 1 shows the course of the voltage applied to the memory transistors erased by a pulse voltage during the erase time τ of one memory cell matrix row. During the time τ shown in a), the flip-flop input terminals 130 and 230 of the circuit shown in FIG. 2 and the gates of the transistors 113 and 213 of the circuit shown in FIG. 3 change from the voltage corresponding to "0" to "1". raised to the corresponding voltage. b) shows the time course of the difference between the source potential U _S and the gate voltage U _G and the difference between the charging voltage U _L and the gate potential U _G of one transistor cell. A sufficient number of pulses (shown here as 10, 11, and 12) are applied to one erased cell until the cell reaches a specific threshold voltage V _T (“0”)≦U _GL .
is given. Thereafter, a very small pulse (here 1
3, 14) or no voltage pulse is applied to the erased cell.
c) shows the time course of the gate voltage applied during the erase pulse interval. Although the entire pulse interval is filled with the control readout time T _KL , this readout time may be shorter than the erase pulse interval. In the following figures and embodiments, T _KL is assumed to be equal to the erase pulse interval. Control read pulse 1
5 to 20 have a constant voltage value _UGL . This determines the predetermined threshold voltage of the cell used, which is significantly smaller than the voltage value of the erase pulse shown in FIG. 1b.

FIG. 1d shows the time course of the threshold voltage V _T of the memory cell. The threshold voltage value is erase pulse 1
It decreases during the duration of 0, 11, 12, and descends sequentially from the initial level 21 to levels 22, 23, 24. Level 24 is lower than the pre-given gate voltage U _GL indicated by the dashed line. After reaching the level 24 below _UGL , as shown in FIGS. 1b and d, no erase pulse is applied to the erased cell and the threshold voltage V _T does not change after this point. Figure 1 e
shows the time course of the drain voltage U _D within the erasing time τ. Drain voltage U _D is control readout time T _KL
A relatively low read voltage applied to the drain during
It is equal to U _DD and is at any level within the hatched areas 29, 30, and 31 depending on the control method at the erase pulse time T _L. The drain voltage level during the erase pulse time T _L has no effect on the functionality of the circuit described herein. Threshold voltage V _T
After the voltage drops below U _GL as shown in d, the erased memory cell becomes conductive. As a result, the drain voltage U _{D becomes} 35,
It drops to 37,39. This value is approximately equal to 0V.

FIG. 2 shows a control circuit for a one-transistor memory cell without an insulated diffusion region inside the erase window. The memory cells are 100,2 to simplify the diagram.
Only four, 00, 300 and 400, are shown with their associated control circuits. The nth source conductor 120 connected bit by bit is connected to the memory cell 100.
and the sources of memory cells 400 and 300, and the (n+1)th source conductor 220 connects the sources of memory cells 400 and 200. The n-th drain conducting wire 140 connected in bit units connects the drains of the memory cells 100 and 300 at the potential U _Do , and the n+1-th drain conducting wire 240 connects the drains of the memory cells 100 and 300 at the potential U _Do+1 .
Connect the drains of 00 and 400. Gate conductor 160 with gate voltage U _Gn connects memory cells 100 and 20.
A gate conductor 360 connecting the gates of memory cells 300 and 400 and having a gate voltage U _Gn+1 connects the gates of memory cells 300 and 400. Furthermore, source conductor 120 or 220 is connected to transistors 122 or 222 and 121 or 2.
21, the low voltage at terminal 123 or 223 and the high voltage at terminal 124 or 224 (approximately 25 to 40V)
can be switched between. Source conductor 120 or 22
0 is connected to a low potential when transistor 121 or 221 becomes conductive. The gate of the transistor 121 or 221 is a NAND circuit 125 or 225
is controlled through the output terminal 126 or 226 of.
The input terminal 127 of the NAND circuit 125 or the input terminal 227 of the NAND circuit 225 is led to a voltage corresponding to "1" indicated by the symbol T _L during the erase pulse time T _L , and "0" during the other times. A voltage corresponding to is derived. NAND circuit 125 or 225
The output terminal of a flip-flop 129 or 229 is connected to the second input terminal 128 or 228 of the flip-flop.
One input terminal 130 or 230 of the flip-flop 129 or 229 is set to "1" during the erase time τ.
An electrical signal corresponding to "0" is led at other times, and a signal corresponding to "0" is led at other times. A drain conductor 140 or 240 is connected to the second input terminal 131 or 231 of the flip-flop 129 or 229, and the drain conductor 140 or 240 is connected to the output terminal 132 of the flip-flop.
Alternatively, 232 is connected to an AND circuit β (not shown), and the output terminal of this circuit receives a signal for the erasing process which is applied to the input terminal 130 or 230 in all cells of one matrix row after the erasing process is completed. cut off. The first input 130 or 2 of the flip-flop 129 or 229 during the total erasing time τ
30 always receives "1". In contrast, the second inputs 131 or 2 of these flip-flops
31 receives a positive voltage U _DD of about 5 to 15 V through the load transistor 135 or 235 during the entire erase process. This allows flip-flop output 128
Or 228 sends out "1" until the selected cell of the corresponding bit is erased. The second input terminal 127 or 227 of the NAND circuit 125 or 225 is added with "1" during the erase pulse time T _L and indicates "0" at other times. With this, NAND circuit 1
The output 126 or 226 of 25 or 225 delivers a "0" during the erase pulse and the transistor 12
1 or 221 is blocked and the source conductor 120 or 220 starts from U _P2 and passes through the conducting transistor 12.
2 and 174 or 222 and 174 to a high positive voltage (25-40V). During the erase pulse interval, "0" is introduced to the input terminal 127 or 227,
“1” is output terminal 1 of NAND circuit 125 or 225
26 or 226. This causes transistor 121 or 221 to conduct and a low voltage of approximately 0V is applied to transistor 121 during the erase pulse interval.
or 221 through source conductor 120 or 220
, so a control read is performed with a low voltage on the source and a low positive voltage (U _DD ) on the drain.

When a cell selected by one bit, say the nth bit, is sufficiently erased, the cell becomes conductive. Therefore, the drain voltage U _Do decreases to a small value close to 0 at the next erase pulse interval. From this point on, input 131 of flip-flop 129 receives a "0" and the other input 130 receives a "1" for the entire memory erase time τ. Therefore, the flip
Flop output 132 is switched to "1",
The second output terminal is the input terminal 128 of the NAND circuit 125
Send “0” to “1” appearing on output terminal 132
is transmitted to one input terminal of an AND circuit β (not shown), and the output signal of this circuit sent out when the erase time of the last selected cell ends is used to cut off the signal for the erase time τ. Produce one signal that can be used. Since the output of the NAND circuit 125 always shows "1" for the entire subsequent erasing time, the transistor 121 is always conductive and the source conductor 120 is placed at a potential of approximately 0V during the rest of the erasing process of the memory. In this way, the erase time of each memory cell is individually cut off, and when the erase time of the last cell ends, the AND circuit β cuts off the signal for the erase time τ of the memory cell selected by its output signal. . After the entire erase process is completed, the flip-flop is connected to input terminal 1 during the erase time.
Drain voltage led to flip-flop 129 or 229 simultaneously with zero level of 30 or 230
If U _Do or U _Do+1 has been raised to "1" for at least a short period of time, it will be set back.

Assume that m+1 is the number of the selected memory cell during gate control, and m is the number of the unselected cell. Word selection is performed by a logic "0" from the address decoder. Here input terminal 3
90 is led to "0", transistor 366 becomes conductive through inverter 391, and at the same time transistor 367 is blocked. Thereby, the gate conductor 360 has a gate voltage U _Gn+1 approximately equal to 0 V introduced through the control readout time T _KL and the transistor 170 which is conductively connected by the inverter 172 during the erasing pulse duration T _L. is conducted through transistor 366. This transistor is conducting through inverter 172 during T _KL . This applies a voltage of approximately 0V to the gate conductor of the selected word during the erase pulse duration _TL , while simultaneously applying a high positive voltage of 25 to 40V to the source conductor. On the other hand, since a high positive voltage is applied to the gates of adjacent words that are not selected during the erase pulse interval, no interference from adjacent words occurs during erasing. That is, the input terminal 190 of non-selected words is "1".
In response, the transistor 166 is connected to the inverter 191.
while transistor 16
7 is energized and transistor 168 is blocked by inverter 173 during the erase pulse duration T _L .
As a result, a high positive voltage U _P1 of approximately 25 V is applied to the gate conductor 160 of the non-selected word through the conductive transistor 169, so the gate voltage of the adjacent word has a high positive value, and the potential difference U _S −U _G is 0. ~
The voltage is 15V, which is insufficient to erase adjacent cells. Transistor 169 conducts during the erase pulse duration T _L because transistor 175 is blocked by inverter 176 during this time and transistor 17
4 is caused by conduction through the resistor 177 and a positive voltage U _P2 of about 30 to 40 V being introduced to the gate of the transistor 169.

During the control readout time _TKL performed at the erase pulse interval, the transistor 170 is connected to the inverter 17.
2, so the control read voltage _UGL is applied to the gate conductor 360 of the selected word m+1 through the conduction transistor 171. This voltage can be derived from a potentiometer.

A voltage U _Gn of approximately 0 V is applied to the gate conductor 160 of the non-selected word through transistors 167 and 168 which are conducting (transistor 169 is blocked) during the control readout time T _KL . This prevents adjacent word interference during control reading.

During T _KL , "0" is introduced to the input terminal of the inverter 176 and "1" is sent from its output terminal, so that the transistor 175 becomes conductive and the transistor 1
74 is blocked, and as a result transistor 169 is also blocked.

FIG. 3 shows a control circuit for a floating gate one-transistor memory cell having an isolated charging and discharging region within an erase window. Again, for the sake of clarity, only the memory cells 101, 201, 301, 401 are shown together with their associated control circuits.
Many parts of the control circuit of FIG. 3 correspond to those of the circuit of FIG. Elements that are the same as in FIG. 2 are designated by the same reference numerals.

In FIG. 3, the gate control circuit is the same as that in FIG. 2, so a description thereof will be omitted.

The difference from FIG. 2 is that the memory cells 101, 20
1, 301, 401 are respectively insulated charge/discharge regions 117, 217, 317, 417 from the source.
It is to have. These areas are the charging/discharging conductor 1
Through bits 19 and 219, it is switched bit by bit between a low voltage of about 0V and a high voltage of about 25 to 40V. This is similar to the case in Figure 2, where transistor 1
21, 122 or 221, 222. Source 118,2 isolated from the charging and discharging region
18, 318, and 418 are each grounded. The drain of the memory cell of FIG. 3 is coupled to a drain conductor 140 or 240 which is similarly connected bit by bit as that of FIG. Flip-flop 129 or 229 of FIG.
In the circuit shown in FIG. 3, the function of the NAND circuit 125 or 225 is achieved by a combination of memory cells 101, 301, transistors 112, 113, and inverter 114, or a combination of memory cells 201, 401, transistors 212, 213, and inverter 214. be substituted. As discussed with respect to FIG. 2, the control circuit according to the present invention ensures that the erase voltage of each memory cell is cut off when one of the cells to be erased falls below a particular predetermined threshold voltage. 131 voltage U _Dn or 231 voltage
When U _Do+1 falls, inverter 114 or 21
4, the gate voltage of transistor 112 or 212 increases. Transistor 113 or 213
Since 131 or 231 is in a conductive state due to the application of the signal voltage during the entire erase process, the voltage of 131 or 231 further decreases as transistor 112 or 212 becomes conductive.
When U _Do or U _Do+1 goes below the threshold voltage, the circuit spontaneously moves to the final stable state and U _Do or U _Do+1
becomes almost 0V. Simultaneously with this transition, the transistor 121 or 221 becomes conductive, and the charging/discharging region 11
The erase voltage of 7,217 or 317,417 is reduced to a small value, respectively. In the circuit of FIG. 3, the return to the original state only takes place after the termination of erasure by blocking transistors 113 or 213. In order to interrupt the entire erasing process of the memory, the drain voltage of each selected cell, for example the drain voltage U _Do of the nth bit selected cell, is changed from the output terminal 141 connected to the drain conductor 140 as shown in the figure. Also not shown in the diagram
Leads to NAND circuit β. The drain voltage U _Do+1 for the n+1th bit is similarly processed through the drain conductor 240 from the output 241. When a cell reaches the erased state, it becomes conductive, thereby reducing the drain voltage from its previously high positive value to approximately 0V, so that each erased cell sends a "0" to the output terminal 141. It leads to the connected inverter, and through it leads "1" to one input terminal of the AND circuit β connected to this inverter. After the last cell of the selected word reaches the erased state
“1” is led to all input terminals of AND circuit β,
“1” is sent from the output end. This final signal is used to interrupt the erasure process.

Using the control circuitry and one transistor memory cell shown in FIG. 3, the memory can be erased by pulses as in FIG. As can be seen from the figure, the control circuit of FIG. 3 has fewer components than the one of FIG. 2, and is capable of faster readout. Furthermore, in the control circuit shown in FIG. 3, the memory is not erased by pulses, but can be erased by an erase voltage and controlled reading can be performed at the same time if the memory is continuous in time. In this case, however, it must be taken into account that unselected memory cells, to whose gates a high compensation voltage is applied during the erasing process, are conductive and risk interfering with the control readout. In this case, it would be necessary to add a selection transistor to form a two-transistor memory cell or to construct the memory from a single word.

A memory according to the invention with a control circuit according to FIG. 2 or 3 can be used, for example, as a tuning memory or a number memory in a telephone exchange installation.

[Brief explanation of drawings]

FIG. 1 is a time course diagram of the applied voltage during the erasing time of a memory transistor that is erased by a pulse.
Figure 2 shows a control circuit for a memory composed of a one-transistor memory cell with a charge/discharge region on the source side, and Figure 3 shows a control circuit for a memory composed of a one-transistor memory cell with an isolated charge/discharge region. show. 10 in Figures 2 and 3
0, 200, 300, 400 are memory cells, 12
0 and 220 are source conductors, 140 and 240 are drain conductors, and 160 and 360 are gate conductors.

Claims (1)

[Claims] 1. Memory cells made of MOS transistors that can be programmed by changing threshold voltages are arranged in a matrix, and the gates of each memory cell transistor are connected to a common gate conductor line for each row, and each memory The sources and drains of the cell transistors are connected to common source conductors and drain conductors for each column, and information is erased by applying an erase voltage to the memory cell transistors. An electrically programmable non-volatile device that monitors the threshold voltage of memory cell transistors and cuts off the erase voltage for each column when the monitored threshold voltage reaches a value representing the erased state. In a word-by-word erasing method for memory cells, an erasing voltage is simultaneously applied to a predetermined number of memory cell transistors, and this predetermined number corresponds to the number of bits of one information word to be stored. The threshold voltage of the memory cell transistor is monitored by detecting the drain voltage of the memory cell transistor, and when the monitored drain voltage reaches a drain voltage value that is a measure of the threshold voltage representing the erased state, the predetermined number of A method for erasing a nonvolatile memory, the method comprising individually cutting off an erase voltage for memory cell transistors that have reached an erased state. 2. The method according to claim 1, wherein the erase voltage is applied in the form of a pulsed voltage, and the threshold voltage of the memory cell transistor is monitored during a pulse pause period of the erase voltage. 3. Claim 1, characterized in that the erase voltage is applied in the form of a temporally continuous voltage, and the threshold voltage of the memory cell transistor is monitored during the application of the temporally continuous voltage. Method described.