JPH0146956B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory device that reduces the time required to read and write stored contents. In recent years, various configurations and methods have been proposed to increase the operating speed of semiconductor memory devices.
For example, one of the major causes of slowing down read and write operation speeds in MOS transistor memories is a delay in word line signal transmission time. Therefore, in order to increase the operating speed, methods are used to reduce the resistance value of the word line, reduce the RC time constant, and reduce the signal transmission delay time of the word line. That is, the thickness of the metal material used for the word line is set thick to lower the resistance value, or aluminum wiring having a low resistance value is used in combination.
However, these methods impose restrictions on the element structure of the memory cell, which poses a major obstacle to the simplification or miniaturization of the memory cell. Furthermore, it has the disadvantage that the manufacturing process becomes complicated. This invention was made in consideration of the above circumstances, and its purpose is to simplify the manufacturing process, shorten the time required for reading and writing, and enable the simplification or miniaturization of memory cells. It is an object of the present invention to provide a semiconductor memory device. An embodiment of the present invention will be described below with reference to the drawings. Figure 1 shows the dynamics according to this invention.
FIG. 3 is a diagram showing RAM. That is, in its configuration, word lines 12 for transmitting signals from row decoders 11 are arranged in the horizontal direction, and bit lines 13 are arranged in the vertical direction. A dynamic memory cell section 1 includes a transfer transistor Tm and a capacitor Cm inserted in series between the bit line 13 and the ground point.
4 is provided. Furthermore, the transistor Tm
The gate of the word line 12 is connected to the word line 12. By the way, conventionally, the signal output from the row decoder 11 is directly supplied to the word line 12, and the transfer transistor Tm is controlled on/off to be applied to the bit line 13.
The signal from the capacitor Cm is written to the capacitor Cm or read from the capacitor Cm to the bit line 13. However, in the present invention, the signal output from the row decoder 11 is supplied to the gate of the transistor _T2 via _T1 whose gate is connected to the power _{supply VDD} . Further, the transistor _T2 is inserted between the terminal φ and the word line 12, and a bootstrap capacitor _C1 is connected between its gate and the terminal φ. The end of the word line 12, which has conventionally been open, is connected to the connection point of the transistors T ₃ and T ₄ connected in series between the power supply V _DD and the ground point. The transistors T ₃ and T ₄ are
The gates of the transistors T ₃ and T 4 are connected in common to the power supply V _DD , and the word line 12 is connected between the transistors T 3 and T ₄ so that the potential of the word line 12 is connected to the transistors T ₃ and T 4 .
It is constructed to raise the conductance ratio to _T4 . As the configuration described above, the transistors T ₃ ,
By setting the conductance ratio of T ₄ to an appropriate value, the initial voltage VS of the word line 12 can be set to 0<
It can be set to the desired value within the range of V _S < V _DD . However, if the initial voltage V _S is set higher than the threshold voltage V _T of the transfer transistor Tm, the transistor Tm will always be in the on state, so it is necessary to set O<V _S <V _T. Needless to say, there is. According to such a configuration, when the word line 12 is not selected, the transistor _T2 is turned off, so the word line potential is maintained at _VS. and,
When the word line 12 is selected, the transistor T ₂ is turned on and the voltage at the terminal φ rises from OV to V _DD , so that the gate voltage of the transfer transistor Tm becomes V _S as shown by the solid line 15 in FIG. rises from Therefore, as shown by the broken line 16, the threshold voltage V _T of the transistor Tm is reached in a shorter time than in the conventional dynamic memory where the gate voltage starts to rise from OV, allowing high-speed reading and writing. Further, the semiconductor memory device according to the present invention does not require a new MOS type transistor structure, does not impose any restrictions on the element structure of the memory cell, is easy to manufacture, and allows miniaturization of the memory cell. The basic principle of this invention is explained below.
Taking MOS transistor readout as an example, the second
This will be explained in detail using FIGS. FIG. 2 shows a temporal change in the word line potential from the time when the row decoder output changes stepwise from L to H. Transistor in the device of the present invention shown by solid line 15 in FIG.
The gate voltage V _T of Tm is is given by Here, C is the electric capacitance of the word line, ρ is the membrane resistance of the word line, and A is a constant determined by the distance of a given memory cell from the row decoder and the shape of the word line. Assuming that the threshold voltage of the transfer transistor is V _T , the time Δt from when the H-level voltage V _DD is applied to the word line from the row decoder output section until the memory contents begin to be transferred to the bit line is as follows: As shown in the equation, Δt=AρCln(1+V _T -V _S /V _DD -V _T ), and the relationship between the time Δt until the start of transfer and the initial voltage becomes the curve shown in FIG. In other words, by bringing the initial voltage V _S of the word line close to the threshold voltage V _T of the transfer transistor,
Transfer start time Δt can be reduced. Therefore, according to the present invention, the read operation speed can be increased. Moreover, the film resistance ρ of the word line
If the present invention is applied in combination with the conventional method of speeding up the read operation speed in which the word line signal transmission delay time is shortened by setting the word line to a small value, it is possible to further speed up the read operation. In the above description, reading of an N-channel MOS transistor was used as an example, but it goes without saying that writing is also similar. Further, the same explanation can be applied to a P-channel type MOS transistor. An example of the effects of this invention will be shown below. In a conventional dynamic RAM, in the case of an N-channel configuration in which the power supply voltage is 5V, the initial voltage of the word line is V _S =OV, and the threshold voltage of the enhancement type transistor is 1V, the access time is about 260 ns. Therefore, by applying this invention and setting the initial voltage of the word line to V _S =0.8V, the access time became 190 ns, which made it possible to shorten the read speed. On the other hand, the write time was reduced by about 40ns. Note that the present invention is not limited to the embodiments described above, and may be applied to static RAM. That is, the configuration is as shown in FIG.
3' is placed. A transistor Tr ₁ , a flip-flop 17 , and a transistor Tr ₁ ' are successively inserted between the bit line 13 and the bit line 13'. Further, the gates of the transistors Tr ₁ and Tr ₁ ' are connected to the word line 12. By the way, conventionally, the signal output from the row decoder 11 is directly supplied to the word line 12, and the transfer transistors Tr ₁ and Tr ₁ ' are controlled on and off to write the signals from the bit lines 13 and 13'. , or read out on bit lines 13, 13'. However, in the present invention, the signal output from the row decoder 11 is input to a two-stage buffer inverter circuit 18 comprised of transistors _T5 to _T9 and a bootstrap capacitor _C2 . The output side of this inverter circuit 18 is connected to the word line 12 via a transistor _T10 . The gate of the transistor _T10 is connected to the row decoder 11, and a bootstrap capacitor _C3 is connected between the gate and the output side of the inverter circuit 18. The end of the word line 12, which was conventionally open, is connected between the power supply V _DD and the ground point to the connection point of the transistors T ₃ and T ₄ connected in series, as in the previous example. The gates of the transistors T ₃ and T ₄ are commonly connected and connected to the power supply V _DD , and the transistors T ₃ and T ₄ are connected to the word line 12 so that the potential of the word line 12 is connected to the transistors T ₃ and T 4 . It is configured to raise the conductance ratio to ₄ . Note that the transistor _T10 has a function of maintaining the potential of the word line at _VS when the word line is not selected. With the above configuration, static
Also in RAM, read and write times can be shortened using the same principle as the dynamic RAM explained in the embodiment. An example of the effects of this invention will be shown under the same conditions as the examples. In other words, the power supply voltage
In the case of N-channel configuration with 5V, initial voltage V _S = OV, and threshold voltage of 1V, the access time is
It was 190ns. Therefore, by applying this invention and setting the initial voltage of the word line to V _S =0.8V, the access time became 130 ns, which made it possible to shorten the read speed. On the other hand, the write time was reduced by about 40ns. As described above, according to the present invention, it is possible to obtain a semiconductor memory device whose manufacturing process is easy, the time required for reading and writing can be shortened, and the memory cells can be simplified or miniaturized.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a semiconductor memory device according to an embodiment of the present invention, FIGS. 2 and 3 are characteristic diagrams for explaining the principle of the invention, and FIG. 4 is a diagram showing another embodiment. It is. 11...Row decoder, 12...Word line, 13,1
3'... Bit line, 14... Dynamic memory cell,
18...Two-stage inverter circuit for word line drive, V _DD
...power supply terminal, φ...external input terminal for word line, T ₁ ,
T ₂ , T ₁₀ ... Row decoder/word line isolation transistor, T ₃ , T ₄ ... Word line initial potential setting transistor, C ₁ , C ₂ , C ₃ ... Bootstrap capacitor, Cm... Dynamic memory cell capacitor.

Claims (1)

[Scope of Claims] 1. A memory cell, a word line for selecting the memory cell, a bit line for exchanging data with the memory cell, and a memory cell provided at one end of the word line,
word line initial potential setting means for setting the potential of the word line to an absolute value (not including 0) lower than the absolute value of the threshold voltage of the transfer transistor of the memory cell; A transistor for holding the word line potential which is provided between the terminals which becomes high level when the word line is selected, a bootstrap capacitor provided between the gate of this transistor and the above terminal to boost the gate potential, and the gate of the transistor and the capacitor for boosting the gate potential. Row decoder/word line separation means provided between output terminals of the row decoder, supplying the output of the row decoder to the word line when selected, and cutting off between the output terminal of the row decoder and the word line when not selected; A semiconductor memory device comprising: 2. The word line initial potential setting means includes a first transistor connected between one end of the word line and a power source and whose gate is connected to the power source and set to be conductive;
2. The semiconductor memory device according to claim 1, further comprising a second transistor connected between one end of the word line and a ground point and having a gate connected to a power supply and set to be conductive. 3. The row decoder/word line separation means comprises a transistor provided between the gate of the transistor and the output terminal of the row decoder, the gate of which is connected to a power supply. semiconductor storage device. 4. The row decoder/word line separation means is provided between the gate of the transistor and the output terminal of the row decoder, and comprises a two-stage inverter circuit that supplies the output of the row decoder to the word line. A semiconductor memory device according to claim 1.