JPS6131554B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory device, and particularly to a MOS transistor memory such as a dynamic RAM or a static RAM.

A plurality of memory cells are arranged in a matrix between a plurality of word lines and a plurality of bit lines through transfer transistors, respectively, and a decoder is arranged to select the word line.
In a MOS transistor memory, it is generally known that the read or write operation speed of a memory cell mainly depends on the signal transmission time of the word line. Conventionally, in order to increase the read or write operation speed of a memory cell, for example, by lowering the resistance value of the word line, the RC time constant of the word line is reduced and the signal transmission delay time of the word line is reduced. Alternatively, a method of increasing the write operation speed was commonly used. In this case, in order to reduce the resistance value of the word line, methods are used, such as increasing the thickness of the metal material used for the word line to reduce its low resistance value, or using aluminum wiring with a low resistance value. It was getting worse. However, the use of these methods imposes restrictions on the memory cell element structure and the manufacturing method of the element, which has been a major obstacle to the simplification or miniaturization of memory cells.

The present invention has been made in view of the above circumstances, and the purpose of the invention is to increase the read or write operation speed of a memory cell and to improve the noise resistance of the stored contents in the memory cell. The purpose of the present invention is to provide a semiconductor memory device.

According to the present invention, a plurality of memory cells are arranged in a matrix between a plurality of word lines and a bit line through transfer transistors, and a decoder is arranged to select the word line. When a word line is selected by the decoder, the potential of the word line is set in advance within a range whose absolute value is smaller than the absolute value of the threshold voltage of the transfer transistor. Further, after the word line is selected by the decoder and the read or write operation is completed, means is provided for lowering the potential of the word line to a reference potential (earth potential) or a potential in the vicinity thereof. A semiconductor memory device is obtained.

Further, according to the present invention, in the semiconductor memory device described above, the means for pre-boosting the potential of the word line and the means for lowering the potential of the word line to a reference potential (earth potential) or a potential in the vicinity thereof are each provided with an address range. A semiconductor memory device is obtained in which the output signal of the entry detector is used.

Since the present invention is configured as described above, the word line potential is boosted before the word line is selected within a range where the absolute value of the word line potential is smaller than the absolute value of the threshold voltage of the transfer transistor. Therefore, when a word line is selected, if the word line potential becomes only slightly higher than the boosted potential, it will exceed the gate threshold voltage of the transfer transistor and cause the contents of the memory cell to be transferred to the bit line. Alternatively, the read or write operation speed can be increased by transferring the signal content on the bit line into the memory cell. Furthermore, in the present invention, an address is used as a means for boosting the word line potential before selecting a word line, and as a means for lowering the word line potential to approximately a reference potential (earth potential) after the read or write operation of the word line is completed. By using the output signal of the transient detector, the absolute value of the word line potential is lowered to the reference potential (earth potential) or a potential near it during inactive times when there is no address change. It is possible to prevent changes in the stored content and improve the noise resistance of the stored content.

Next, the basic principle of the present invention will be explained in detail. In the following explanation, an N-channel MOS transistor will be described, but a P-channel MOS transistor can also be considered in the same way. Further, in the following explanation, the read operation of the memory cell will be described, but the write operation can also be explained in the same way.

In the case shown in FIG. 1, a voltage V _S smaller than the threshold voltage V T of the transfer transistor is applied to the word line by the output signal of the address transient detector, and a voltage _H is applied to the word line from the decoder in a stepwise manner. It shows the time change in the voltage applied to the gate of the transfer transistor of one memory cell connected to the word line from the time when the level voltage V _DD is applied. This gate voltage V _(t)
is given by V _(t) =-(V _DD -V _S )e-t/AρC+V _DD (1). Here, C is the capacitance of the word line,
ρ is the membrane resistance of the word line, and A is a constant determined by the distance from the row decoder output of the memory cell of interest and the shape of the word line.

If the threshold voltage of the transfer transistor is V _T , a high level voltage is applied stepwise from the row decoder output section to the word line.
The time Δ from when the level voltage V _DD is applied until the contents of the memory cell begin to be transferred to the bit line
t is as follows.

Δt=AρCln(1+V _T −V _S /V _DD −V _T )…(
2) The relationship between the time Δt until the start of transfer and the initial voltage V _S of the word line given by the output signal of the address transient detector is as shown in FIG. As is clear from FIG. 2, Δt can be reduced by bringing V _S closer to V _T .

On the other hand, in an inactive state where there is no address change, the address transient detector becomes inactive,
Voltage V applied to the gate of the transfer transistor
_(t) becomes V _(t) = 0 (3). Therefore, the word line noise margin, which was V _T -V _S during operation, is greatly improved to V _T (>V _T -V _S ) in this case.

As described above, it is clear that according to the present invention, the read operation speed (or write operation speed) can be increased, and the noise resistance of the stored contents can be improved when there is no address change and there is no activity.

Next, one embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 3 shows a schematic circuit diagram of an embodiment in which the present invention is applied to a dynamic RAM. In Fig. 3, a plurality of memories are arranged in a matrix between a plurality of word lines 1 and bit lines 2 (only one of each is shown in Fig. 3) via transfer transistors Tm. A cell 3 (only one cell is shown in FIG. 3) is provided. A row decoder 4 is connected to the word line 1 and is arranged to select an arbitrary word line. When the word line 1 is selected by the row decoder 4, the potential of the word line 1 is boosted to the initial voltage V _S in advance within a range whose absolute value is smaller than the absolute value of the threshold voltage V _T of the transfer transistor Tm. For example, transistors T 1 , T ₂ , T 3 are connected to the word line 1 as a means for lowering the potential of the word line 1 to approximately the reference potential (earth potential) after the reading or writing operation of the word line ₁ is _completed. and address transient detector 5 are arranged as described later. That is, the transistors T ₁ and T ₂ are the address transient detectors 5 which become H when the address changes.
is controlled by the first output signal φ ₁ of word line 1
It is connected in series between the power supply V _DD and the reference potential (earth potential) so as to boost the initial voltage V _S to the initial voltage V S, and _the connection point thereof is connected to the word line ₁ . The first output signal _φ1 of the address transient detector 5 is input to each gate. Further, the transistor _T3 is connected between the word line 1 and the reference potential (earth potential), and the first output signal _φ1 of the address transient detector 5 goes high and goes low at its gate.
Then, when the read or write operation of the memory cell is completed, the second output signal _φ2 , which becomes H and stops, is input, and the word line 1's V _S and the read or write operation potential are maintained, and the read or write operation of the word line 1 is performed. After the operation is completed, the potential of the word line 1 is lowered to approximately a reference potential (earth potential). The transfer transistor Tm and the capacitor Cm constitute a dynamic memory cell 3, and the transistor _T4 controls the potential of the word line 1 only by the output signal of the address transient detector 5 when the word line 1 is not selected. Transistor _T5 is a transistor that serves to apply a bootstrap voltage to the gate of _T4 through bootstrap capacitor _C1 .

Next, the operation of the embodiment of the present invention shown in FIG. 3 will be explained. In FIG. 3, it is assumed that an arbitrary word line, for example, word line 1, is selected from among a plurality of word lines by an address command. Before the row decoder 4 is activated by the address command, the address transient detector 5 is activated, and its first output signal φ ₁ is output as an H pulse waveform as _shown in _FIG . Input to each gate of T ₂ to turn on T ₁ and T ₂ . On the other hand, as shown in FIG. 4, the second output signal _φ2 of the address transient detector 5 becomes L at the same time as _φ1 becomes H, so the transistor
T ₃ is off. T ₁ and T ₂ are each turned on.
Since T ₃ is turned off, the potential of the word line 1 is boosted to the initial voltage V _S . In this state, after _φ1 becomes L, the word line 1 is selected by the operation of the row decoder 4, and the terminal voltage _φ3 of the transistor T4 connected to the word line ₁ rises from 0V to _VDD .
As a result, the gate voltage of the transfer transistor T _n changes as shown in Figure 1, and T _n turns on.
Reading or writing to the memory cell 3 is performed via the bit line 2. In this case, since the potential of word line 1 has been boosted to V _S before word line 1 is selected, the time Δ until the start of transfer is Δ
t becomes small, and the read or write operation speed of the memory cell 3 can be increased.

When the read or write operation of the memory cell 3 is completed, _φ3 changes from V _DD as shown in FIG.
The voltage becomes 0V, and _φ2 changes from 0V to _VDD , that is, from L to H, and becomes stationary. When _φ2 becomes H, _T3 turns on. As a result, when there is no address change, the potential of the word line 1 is lowered to approximately the reference potential (earth potential) through _T3 . Therefore, the noise resistance of the stored contents of the memory cell 3 is improved for the above-mentioned reason.

Although one embodiment in which the present invention is applied to a dynamic RAM has been described above, the present invention is not limited thereto. FIG. 5 shows an embodiment in which the present invention is applied to a static RAM. In FIG. 5, the constructions of the word line 21, bit lines 22, 22, memory cell 23, row decoder 24, and address transient detector 25 are substantially the same as those in FIG. 3, and therefore their explanation will be omitted. The transistors T ₁ ′ and T ₂ ′ connected to the word line 21 change the potential V _W of the word line 21 by the first output signal φ ₁ ′ of the address transient detector 25, which becomes H due to a change in the address.
is boosted to the initial voltage _VS , and the transistor T ₃ ' is φ
₁ ' becomes H and becomes L, and the memory cell 23
The second output signal of the detector 25 becomes H and stops after the read or write operation is completed.
₂ ' to maintain the initial voltage V _S and read or write operation potential V _DD of the potential of the word line 21, and after these operations are completed, the potential of the word line 21 is lowered to approximately the reference potential (earth potential). What is done is the same as in the embodiment in FIG. Transistors Tm ₁ to _{Tm 6} constitute a static memory cell, in which Tm ₅ is connected to the respective bit lines 22 and 22, and each gate is connected to the word line 21 to constitute a transfer transistor. . A transistor arranged between the row decoder 24 and the word line 21
T ₅ ′ to T ₉ ′ constitute a two-stage inverter circuit for buffering, capacitors C ₁ ′ and C ₂ ′ are bootstrap capacitors, and transistors
T ₄ ' and the word line 21 are designed to have the function of a switching transistor that cuts off the connection between the buffer circuit output and the word line 21 when the word line 21 is not selected. Although the embodiment shown in FIG. 5 is constructed as described above, its operation is substantially the same as that described for the embodiment shown in FIG. 3, so a description thereof will be omitted. Incidentally, FIG. 6 is a timing chart showing the time change of each pulse waveform in one embodiment in FIG. 5.

Next, the results of a comparative experiment between a RAM to which the present invention is applied and a conventional RAM will be shown. In this experiment, the power supply V
This was carried out using a RAM consisting of an N-channel MOS transistor in which _DD = 5V, initial voltage V _S = 0.8V, and the threshold voltage of the enhancement type transistor was 1V. Dynamics to which the present invention is applied
The access times of RAM and static RAM are 200ns and 140ns, respectively, while the conventional ones are 260ns and 190ns, respectively.
Furthermore, in terms of write time, the dynamic RAM and static RAM to which the present invention was applied were 30 ns and 20 ns faster, respectively, than the conventional RAM. In addition, in order to compare the noise resistance of memory contents, we measured the error rate of memory contents in a high frequency, high electric field atmosphere of 10 ⁴ V/m, and found that the error rate of RAM to which the present invention was applied was higher than that of conventional RAM. The percentage ranged from 74% to 98%.

As is clear from the above description, according to the present invention, for example, the output signal of the address transient detector is used to boost the word line potential to a range smaller than the threshold voltage of the transfer transistor before the word line is selected. By setting the word line potential to the reference potential (earth potential) or a potential close to it, the word line potential can be lowered to the reference potential (earth potential) or a potential close to it when there is no address change. This makes it possible to improve the noise resistance of stored contents.

In each of the above embodiments, when selecting a word line, there is a means for boosting the potential of the word line in advance, and after the word line is selected and a read or write operation is performed, the potential of the word line is set to approximately the reference potential (earth potential). ), the present invention is not limited to this, and various modifications and changes can be made. Other output signals having substantially the same function may be used in place of the output signals, and transistors T ₁ to _{T 3} (T ₁ ′ to T ₃ ′) and the output signals φ ₁ and ₂ controlling these transistors
Of course, other circuit configurations having substantially the same function as these may be used in place of (φ ₁ ' and ₂ ').

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the change in word line voltage over time in an embodiment of the present invention, and FIG. 2 is a diagram showing the time Δt until the start of transfer and the initial voltage V in an embodiment of the present invention.
3 is a schematic circuit diagram of an embodiment in which the present invention is applied to a dynamic RAM, FIG. 4 is a timing chart of each pulse waveform in the embodiment of FIG. 3, and FIG. 5 is a diagram showing the _relationship between S and S. State the invention
A schematic circuit diagram of an embodiment applied to a RAM, and FIG. 6 is a timing chart of each pulse waveform in the embodiment of FIG. 5. 1, 21... Word line, 2, 22, 22... Bit line, 3, 23... Memory cell, 4, 24...
Row decoder, 5, 25...address transient detector, _T1 , _T2 , T1 _' , _T2 '...word line initial voltage setting transistor, _T3 , _T3 '...word line potential drop Transistors for T ₄ , T ₄ ′, T ₅ …
...Separation transistor, Tm to Cm...Dynamic memory element, _Tm1 to _Tm6 ...Static memory element, _T5 ' to _T9 '...Buffer circuit for row decoder output, _C1 , _C1 ', C ₂ ′...Bootstrap capacitor.

Claims (1)

[Scope of Claims] 1. A plurality of memory cells arranged in a matrix between a plurality of word lines and a bit line through transfer transistors, and an arbitrary word line from among the plurality of word lines. a row decoder arranged to select a word line; and when a word line is selected by the row decoder, the potential of the word line is set within a range whose absolute value is smaller than the absolute value of the threshold voltage of the transfer transistor. and means for lowering the potential of the word line to a reference potential (earth potential) or a potential in the vicinity thereof after the word line is selected by the row decoder and the read or write operation is completed. A semiconductor memory device characterized by: 2. In the device described in claim 1, the means for pre-boosting the potential of the word line and the means for lowering the potential of the word line to a reference potential (earth potential) or a potential in the vicinity thereof each include: 2. The semiconductor memory device according to claim 1, wherein an output signal of an address transient detector is used. 3. In the first and second claims, the first output signal of the address transient detector is connected in series between a power supply (V _DD ) and a reference potential (earth potential), and The connection point is input to each gate of two transistors connected to the word line, and operates to boost the potential of the word line in advance when the word line is selected. The second output signal is input to the gate of a transistor connected between the word line and a reference potential (earth potential), and after the read or write operation of the word line is completed, the potential of the word line is set to approximately the reference potential (earth potential). 3. The semiconductor memory device according to claim 1, wherein the semiconductor memory device operates to lower the potential to a ground potential.