JPH0147937B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pulse detection circuit using a MOS field effect transistor (hereinafter simply referred to as "MOS transistor"). In particular, the present invention relates to a pulse detection circuit suitable for integrated circuit devices.

Conventionally, a pulse detection circuit that sends out a predetermined output when there are continuous pulses has been required in various integrated circuits or various data receiving devices, and a circuit with the configuration shown in Fig. 1 is known. There is. This circuit consists of MOS transistors 1, 2 and 3,
The capacitor 4 and the diode 5 constitute a differential circuit, and the MOS transistors 6 and 7,
The capacitor 8 constitutes an integrating circuit. V _DD is the supply voltage and V _SS is the negative supply voltage.

FIG. 2 is an operation waveform diagram of the points indicated by the x marks in FIG. 1. Input signal a applied to input terminal 10
Differentiate with the above differentiation circuit. Of this output b, only the positive potential is taken out by a rectifier circuit including a diode 5 and applied as the gate voltage of the MOS transistor 6. The integrator circuit integrates this waveform and stores it in the capacitor 8, so by setting the output level c of the integrator circuit to a negative potential (V _SS level), when continuous pulses arrive at the input terminal 10, the output When V _SS appears at terminal 12 and there is no continuous pulse at input terminal 10, output terminal 12
V _DD appears. Thereby, the presence or absence of continuous pulses is detected.

Incidentally, recent semiconductor integrated circuit devices are required to have smaller chip areas, lower current consumption, and expanded operating voltage ranges. However, in the conventional configuration described above, when the current consumption is reduced, the MOS transistors 3 and 7, which operate as constant current circuits, become dependent on the power supply voltage, and their area becomes large.
If the area of the MOS transistors 3 and 7 is reduced, the current consumption and operating voltage range (especially at high voltages) will deteriorate.

SUMMARY OF THE INVENTION The present invention aims to improve the above-mentioned drawbacks, and aims to provide a pulse detection circuit that reduces both chip area and current consumption and is suitable for semiconductor integrated circuit devices having a wide operating voltage range.

The present invention comprises a differentiating circuit using MOS type field effect transistors, a rectifying circuit which takes the output of this differentiating circuit as an input, and a rectifying circuit which takes the output of this rectifying circuit as an input.
In a pulse detection circuit equipped with an integrating circuit using a MOS type field effect transistor, a drain and a source are coupled between a constant voltage source and an input of the integrating circuit and a common potential point, and a gate is connected to a first voltage source from the constant voltage source. A constant voltage of
It is characterized by comprising a MOS type field effect transistor, and a MOS type field effect transistor whose drain and source are coupled between the integration circuit and the power supply and whose gate is supplied with a second constant voltage from the constant voltage source. do.

The basic configuration of the present invention is to connect a differentiating circuit made up of a MOS transistor, a capacitor, and a constant voltage source, and an integrating circuit made up of another MOS transistor, a second capacitor, and a constant voltage source, It is characterized in that the output of the circuit is used as the detection output.

The present invention will be explained based on the drawings.

FIG. 3 is a block diagram of one embodiment of the present invention. P channel MOS transistor 1 and N channel
The gates of MOS transistors 2 are connected in common,
An input terminal 10 is connected to this connection point. The drains of the P-channel MOS transistor 1 and the N-channel MOS transistor 2 are connected in common, and one end of a capacitor 4 is connected to this connection point. The other end of the capacitor 4 is connected to the drain of the N-channel MOS transistor 3. The sources of this N-channel MOS transistor 3 and the N-channel MOS transistor 2 are commonly connected.

A diode 5 is connected between the drain and source of this N-channel MOS transistor 3. The drain of this N-channel MOS transistor 3 is connected to the gate of an N-channel MOS transistor 6. The source of this N-channel MOS transistor 6 is connected to a terminal 11 that provides a negative power supply voltage V _SS . Also,
The drain of the N-channel MOS transistor 6 and the drain of the P-channel MOS transistor 7 are commonly connected, one end of a capacitor 8 is connected to this connection point, and an output terminal 12 is connected to this connection point. . This P channel
The other end of the capacitor 8 is connected to the source of the MOS transistor 7. This P channel MOS transistor 7 and the above P channel
The sources of MOS transistor 1 are connected in common, and this connection point is connected to terminal 1 which supplies the power supply voltage V _DD .
3 is connected.

Further, a constant voltage source 15 is connected to this connection point. The gate of the N-channel MOS transistor 3 is connected to the terminal 16 that outputs the voltage V ₁ of the constant voltage source 15 . Further, the gate of the P-channel MOS transistor 7 is connected to the terminal 17 that outputs the voltage V ₂ of the constant voltage source 15. Furthermore, this constant voltage source 15 is connected to the terminal 11 mentioned above.

FIG. 4 is an operation waveform diagram of the points indicated by the x marks in FIG. 3. A clock pulse is applied from input terminal 10 as input signal a. If the potential of the clock pulse is now _VDD , the MOS transistor 2 becomes conductive, and the potential at point B in FIG. 3 becomes _VSS . At this time, MOS transistor 6 becomes non-conductive. At this time, the voltage across capacitor 8 is V _C
is V _C = C ₈ V ₀ −∫ ^t1 / ₀ I ₇ dt / C ₈ V ₀ : Voltage across capacitor 8 just before input signal a becomes V _DD I ₇ : Current flowing through MOS transistor 7 t ₁ : Input Time during which signal a is at V _DD C ₈ : Capacity of capacitor 8. This shows that V _C does not change when t ₁ is short. where I ₇ is the supply voltage and
In order to avoid dependence on the threshold voltage of the MOS transistor, a reference constant voltage that takes the threshold voltage of the MOS transistor into consideration is generated within the semiconductor integrated circuit, and the voltage _V2 at the output terminal 17 is set to the gate voltage of the MOS transistor 7. shall be. This allows the MOS
Even if there are manufacturing variations in the transistor 7, the variation in the current _I7 can be reduced and the current can be reduced.

Furthermore, when the potential of the clock pulse given as the input signal a from the input terminal 10 is V _SS ,
MOS transistor 1 becomes conductive. At this time, the minimum potential at point B in Figure 3 is V _B = C ₄ V _DD −∫ ^t2 / ₀ I ₃ dt / C ₄ V _B : Potential difference between point B and V _SS terminal I ₃ : MOS transistor Flowing current C ₄ : Capacity t ₂ of capacitor 4 : Time during which input signal a is at V _SS .

From this, when t ₂ is short, the potential V _B at point B becomes the power supply voltage V _DD and the voltage V _C of the capacitor 8 becomes the negative power supply voltage V _SS .

When the clock pulse widths t ₁ and t ₂ of the input signal a become longer, the voltage V _C of the capacitor 8 and the voltage V _B of the point B approach zero potential, which can be distinguished from the above state, so that a pulse can be detected. Further, by adjusting the reference voltage V ₁ provided from the constant voltage source 15, it is possible to reduce the voltage drop and current when the voltage V _B is high.

In addition, MOS transistor 7 and
Since the gate voltage of the MOS transistor 3 can be adjusted, the size of the MOS transistors 7 and 3 can be designed relatively freely without being affected by the power supply, and the area of the transistors can be reduced. Furthermore, since the input frequency to be detected is not affected by manufacturing variations in the MOS transistors 3 and 7, and the variations in the currents I ₃ and I ₇ are reduced, the detection accuracy of the circuit of the present invention is improved. Furthermore, since the circuit of the present invention makes the currents I ₃ and I ₇ constant currents, it is also possible to detect the power supply voltage if the input frequency is fixed.

As explained above, according to the present invention, the timing of the differentiating circuit and the integrating circuit is adjusted according to the power supply voltage.
Since it no longer depends on the threshold voltage of the MOS transistor, the accuracy of pulse frequency detection can be improved. In addition, the constant voltage source can also be integrated into an integrated circuit, reducing chip area and current consumption.
A pulse detection circuit suitable for a semiconductor integrated circuit device with a wide operating voltage range can be provided.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of a conventional example. FIG. 2 is an operational waveform diagram of the conventional example. FIG. 3 is a configuration diagram of one embodiment of the present invention. FIG. 4 is an operational waveform diagram of the above embodiment. 1, 7...P channel MOS transistor, 2,
3, 6...N channel MOS transistor, 4,
8... Capacitor, 5... Diode, 10... Input terminal, 11, 13, 16... Terminal, 12... Output terminal, 15... Constant voltage source.

Claims (1)

[Claims] 1 A CMOS inverter that receives pulse signals,
a first capacitor connected between a circuit point, the output of the CMOS inverter, and the circuit point;
a first MOS transistor of one conductivity type having first and second power supply terminals, a diode connected between the circuit point and the first power supply terminal, and a source-drain path connected in parallel to the diode; an output terminal, the output terminal and the first
a second MOS transistor of one conductivity type having a source-drain path connected between the power supply terminals of the transistor and a gate connected to the circuit point; and a second MOS transistor connected between the output terminal and the second power supply terminal. a third MOS transistor of an opposite conductivity type having a source-drain path connected in parallel to the second capacitor, and a constant voltage source that generates first and second constant voltages; and a second constant voltage is supplied to the gates of the first and third MOS transistors, respectively.