JPH0149907B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data processing method for digitizing periodic input information obtained by radar, sonar, etc. and processing the data in real time.

[Conventional technology]

Conventionally, the most common signal display method for radar, etc. is to start the sweep current of the cathode ray tube display at the same time as the transmission pulse is sent, and the reflected signals obtained from moment to moment are amplified and then displayed on the cathode ray tube in real time. In addition to this, it also displays target images. Looking at the temporal distribution of the received signal corresponding to one sweep signal in this conventional method, the distance to the target corresponds in proportion to the time from the start of the sweep, so the received data appears one after another as time passes. However, since they disappear one after another,
Here, real-time data display processing is required. Figure 1 shows the transmission waveform A in the radar,
The above relationship can be understood by showing the sweep waveform B and the received signal C over time on the horizontal axis.

However, for example, if the distance range of a radar is switched between multiple ranges from 1/4 mile to 120 miles, the ratio between the minimum and maximum time width of the sweep signal will be 480 times,
If the received signal is displayed as it is in real time, the brightness of the display device in the short range will be significantly lower than that in the long range, and the brightness of the display device will change only by a change within the variable range of the repetition frequency of the transmitted signal. The disadvantage is that it cannot be compensated for.
The reason for this is that the light emitting element of the cathode ray tube does not produce sufficient light output with extremely short-term electron beam energy.

The method that has been devised to date to solve these problems is to convert an analog video signal obtained from an antenna 1 through a receiver 2 into a digital signal using an A/D converter 3, as shown in Figure 2. , this digital data is sequentially written in real time to a storage device 4 such as a shift register in synchronization with the write clock CL1, and when all data writing is completed by continuous writing operation over the writing time period corresponding to the range to be displayed, switching is performed. Read clock CL of a frequency different from write clock CL1 from device 5.
2, read the written data sequentially,
This is added to the display 7 in response to the signal from the sweep signal generator 8 via the amplifier 6 and displayed. In this case, if the read clock CL2 is set to a sufficiently lower frequency than the write clock CL1 in the short range, a received signal extended in time will be supplied to the display 7. However, sufficient brightness can be obtained.
FIG. 3 is a timing waveform diagram for the conventional method shown in FIG. 2, showing each of the transmission waveform A, the received video signal B, the write gate C, the read gate D, the read video signal E, and the sweep signal F with a time axis. . As is clear from Figure 3, the write operation time
The read operation time t ₁ and the read operation time t ₂ are independent and distinct time periods, and have a relationship in which the read operation time starts after the write operation time ends. Therefore, this method requires the sum of the write time t ₁ and the read time t ₂ (t ₁ + t _{2 ), and the repetition interval time of the transmission signal A, that is, the period T of the transmission signal A, is always equal to the time (t 1 +t 2} ). ₁ + t ₂ ). This restriction on the transmission signal period depending on the write time and read time causes a number of other problems. One of them is that the upper limit of the repetition frequency of the transmitted pulse is limited. That is, the repetition frequency is 1/(t ₁ ,
_t2 ) or more cannot be achieved, so it is kept low, and especially when the antenna rotation speed is high, the sweep density on the cathode ray tube becomes coarse and the image quality deteriorates. Part 2
In this case, when it is desired to read data from a storage device and perform necessary data processing due to the need for an anti-collision device or the like, the reading time is limited and the processing cannot be performed quickly.

[Problem to be solved by the invention]

It is an object of the present invention to maintain stable display brightness regardless of changes in the display range, to operate by substantially overlapping the time for writing data to a storage device and the time for reading data from the same device, and to Provided is a data processing method for synchronous input information that is economical and practical and is capable of eliminating interference waves generated by radio wave sources, etc., and realizing faster data processing and improved reliability. It is something.

[Means for solving problems]

This first invention digitizes a received signal periodically obtained as a result of transmitting a periodic transmission pulse using a first sampling frequency having at least one sampling clock within the width of the transmission pulse. A conversion device, a data compression and synthesis device that compresses and synthesizes digital data obtained from the conversion device using a compression ratio corresponding to the number of data, and compressed digital data output from the data compression and synthesis device. The storage device to which writing and reading are performed, and the compressed digital data outputted from the data compression and synthesis device in each data compression cycle are divided into two times, one of which is the retention time of each digital data. A writing device that writes to the storage device and a reading operation of the data stored in the storage device are performed in synchronization with the start of the writing operation of the writing device by time-sharing operation using a second writing frequency. start,
A reading device reads from the storage device by a time-sharing operation at a third reading frequency using the other of the time-divided data retention times that the writing device is not using in the time-sharing writing operation. The first sampling frequency and the second writing frequency are set to have an integer ratio equal to the data compression ratio in the data compression and synthesis device, and the second writing frequency and the third reading frequency are , a write operation using the second write frequency and a read operation using the third read frequency, which are started in synchronization with the input of the periodically obtained received signal, are performed within the period of the periodically obtained received signal. It is characterized in that it is set to be an integer ratio within the range that ends.

The second invention is characterized in that the compression and synthesis apparatus according to the first invention performs compression and synthesis of data by calculating the logical sum of successive data among the digitized data.

〔Example〕

Embodiments of the data processing method according to the present invention will be described below with reference to the drawings.

First, FIG. 4 shows a principle timing waveform diagram in the data processing method of the present invention. That is, the received video signal B received by sending out the sending pulse A with a pulse width τ sent out with a period T is sequentially stored in a random access memory (hereinafter referred to as
The data is written to a storage device such as RAM), and all data writing is completed within the required time _t1 . On the other hand, data previously written from the storage device is sequentially read out over the required time t ₂ by a read signal D starting at approximately the same time as the write signal,
This readout output signal (corresponding to the readout video signal E) is applied to the display together with the sweep signal F to display an image. As a result, it is possible to set the read time t ₂ for all data to overlap the write time t ₁ , and even when the write time t ₁ changes due to a range change, the transmission When the signal period is single, there is no need to change the required reading time _t2 , so that sufficient target display brightness can be obtained on the display. Further, when the device has a plurality of transmission signal periods, a plurality of readout required times _t2 can be set correspondingly to maintain uniformity of display brightness.

FIG. 5 is a block diagram showing a specific embodiment of the present invention using a RAM such as SN74S200 manufactured by Texas Instruments Inc. as a storage device, and FIG. 6 shows its basic timing waveform. .

In FIGS. 5 and 6, the analog received signal is converted into a 1-bit or multiple-bit digital quantity by an analog-to-digital converter (hereinafter referred to as an AD converter). As a specific example of an AD converter,
By setting a reference threshold level in the voltage comparator 10 and outputting a logic level "1" when this threshold level is exceeded, and obtaining a logic level "0" output when the voltage is below the threshold, a 1-bit digital signal can be generated. Convert to quantity. In actual equipment, multiple voltage comparators with different threshold levels are used to obtain a digital quantity with an arbitrary number of bits, but to simplify the explanation below, we will use an example of converting to a 1-bit digital quantity. Take.

Next, the output of the voltage comparator 10 is input to a latch flip-flop (hereinafter referred to as latch FF) 12 together with a sample clock pulse A (FIG. 6A).
Sample data B (6th
Figure B) is obtained. For the sample clock pulse A used here, in order to write the received video signal obtained corresponding to each distance range into the storage device 14 in real time, one or more frequencies are selected based on a standard.

The first criterion is that the number of sample data B is a constant quantity or an integral multiple of this, that is, 1, 2, 3, ..., n
The frequency of the sample clock pulse is determined so that the frequency is close to double or 1/2, 1/3, . . . , 1/n, etc. This is because it is desirable that the storage capacity of the storage device 14 be constant or an integral multiple thereof for each distance range.

The second criterion is to determine the sample clock frequency so that when these sample data are displayed on a cathode ray tube together with a sweep signal, the number of sample data is large enough not to deteriorate the image.

The third criterion is that the repetition time width tsc of the sample clock A is set to the transmission pulse width τ
(See Figure 4) It is preferable that it be smaller. To explain in detail, for example, suppose that a transmission radio wave with a pulse width τ is emitted. In this case, the time width of the received radio wave with the smallest time width is approximately τ. Such received radio waves include, for example, reflected signals from a very thin burlap board. Therefore, in order to sample the received signal with the minimum time width using the sample clock pulse, it is necessary to
If τ=f ₀ , the frequency f of the sample clock pulse must be selected to be greater than f ₀ , and according to the sampling theorem, it is desirable that f<2f ₀ . The standards shown in FIG. 3 are required from the above-mentioned viewpoints. Furthermore, if the frequency f of the sample clock pulse is made smaller than the above f ₀ and the repetition time width tsc is made larger than the transmission pulse width τ, the received signal with the minimum time width may not be sampled. .

The bits of the sample data latched by the sample clock A selected based on the above criteria are now designated as D0, D1, D2, . . . , _Do. These data are sequentially written into corresponding addresses of the memory device 14 under the supply of an address signal throughout the time of the write gate signal. Write gate C is activated by sample clock A and terminates after half the repetition time of sample clock A, tsc/2. That is, the write gate signal C is valid only during the first half of the sample data holding time. In terms of circuit,
A write clock having the same cycle as the sample clock A is input to the write address counter 16, and the AND circuit 18 extracts the logical product of the address data taken out from the output thereof and the write gate signal C, and stores it via the OR circuit 20. Connect to address input terminal A of device 14.

In this example, RAM (74S200) is used as the storage device.
The memory capacity is 256 bits, and an address can be specified using 8-bit address data. However, if a larger memory capacity is required, multiple RAMs are used and an address counter is used. 16 upper bits (9 bits or more)
If you connect the inverted signal of the decoded output to the CS terminal (chip selection terminal) of the RAM, the corresponding
It is now possible to select the RAM IC chip.

Furthermore, data writing to RAM as the storage device 14 is performed using WE (Write Enable) in addition to address specification.
The timing and time width of the WE signal are specified by each RAM standard, and the WE signal in Figure 6 is required.
As shown in signal D, the required setup time t _WS until the WE signal is input, the hold-up time t _WH of the address signal that needs to be continued even after the WE signal is invalidated, and the required time t _WE of the WE signal. Each of these is determined to meet the standards of the RAM being used. Thus, the data to be written D0,
The signals from the address counter 16 specifying the addresses corresponding to D1, _D2 , . RAM
digitized received video signals are sequentially written in real time.

Next, reading of written data will be explained with reference to FIGS. 5 and 6. Data reading from the storage device 14 is performed at a frequency different from the writing frequency. Read gate E, data output F, latch clock G and latch output H in FIG.
(Write data time width) / (Read data time width) = (Latch clock G frequency) / (Sample clock A frequency) = n When the ratio is 1:1, 1:2, 1:3 The features of this invention are these two
The ratio n of the two data time widths is 1, 1/2, 1/3,
... can be set to any integer ratio, and as a result, the display time of data read in real time can be extended to any integer multiple and displayed on the CRT, so the distance range can be increased. Even if it is small, it can provide sufficient brightness for images displayed on a cathode ray tube.

Now, to explain the case where the time ratio of both data is 1:2 as an example, the read clock frequency is half of the write clock frequency, this read clock is supplied to the read address counter 22, and the output side is a storage device. The address data specifying the read address No. 14 is extracted by applying the read gate signal E ₂ generated subsequent to the write gate C to the AND circuit 24 and is supplied to the memory device 14 . That is, the read gate signal _E2 starts in synchronization with the end of the write gate signal C, and ends with the generation of the next sample clock A, with a time width tsc/
2, and its rate of occurrence is proportional to the period of the read clock. As a result, the read gate signal is valid only in the second half of the sample data B holding time tsc. Looking at this with respect to read gate _E2 , first, read gate signal to read address “0”
E ₂ occurs in the second half of the time when sample data D ₀ is held, with a time width of approximately tsc/2, and the next “1”
Address read gate signal E ₂ is sample data
This occurs sequentially with a time width of approximately tsc/2 in the latter half of the time when D ₂ is held.

Upon generation of read gate signal E ₂ , AND circuit 2
When read address data is supplied from 4 to the memory circuit 14 via the OR circuit 20, after a certain period of time _TAA (address access time) has elapsed from the start of the read gate signal _E7 , the data at the specified address is read from the memory device 14. is read, producing data output _F2 . That is, for address “0” designation, data D ₀
However, for the "1" address designation, data _D1 is sequentially read out. This output data _F2 is latch FF
26 with latch clock _G2 to hold the data read from storage 14 until the next latch clock is input. As a result, the latch output _H2 of the latch FF26 is the sample data B
The data is sent out as data extended to twice the retention time.

As described above, in the data processing method of the present invention, received video data written in real time can be extended to an arbitrary time width by appropriately selecting the ratio between the write frequency and the read frequency for the storage device. The write and read cycles can be performed in substantially overlapping time periods. Therefore, a signal with the video reception time width extended to any multiple can be supplied to the display.
Images can be displayed with sufficient brightness on the cathode ray tube, and since the write time and read time can essentially overlap, data can be read and utilized using a processor, that is, after the end of the write gate signal C. This is because the latter half of the time is left open for reading, so reading during a write operation can be performed by specifying an arbitrary address at an arbitrary timing. For example, in the timing waveform of FIG. 6 where the ratio of write/read data time width is 1:2,
Since the latter half of the time period corresponding to sample data _D1 is bright, it is possible to read the write data using this bright time by an interrupt operation or the like.

Next, a method according to another embodiment that is improved using the basic method of the present invention will be described. As is clear from the timing waveforms in FIG. 6, in the embodiment shown in FIG. 5, the write gate signal C for supplying the write address signal to the storage device 14 is This is only tsc/2 in the first half of the sample data retention time. This is to avoid duplication of the two since the latter half of tsc/2 time is used for supplying the read address. Therefore, only the timing of tsc/2 in the first half of the sample data can be used as input data, and the sample data in the second half of tsc/2 is not effectively utilized.

Therefore, the latch FF1 in the embodiment of FIG.
By replacing 2 with the circuit configuration shown in FIG. 7, it becomes possible to effectively utilize the entire sample data holding time tsc, and FIG. 8 shows timing waveforms of each part when the circuit configuration of FIG. 7 is used.

That is, in FIG. 7, the input data digitized by the voltage comparator is input to the sampling clock A.
and the first latch FF28, and the latch FF
28 and sampling clock A are connected to the second latch FF30, and the outputs of the latches FF28 and 30 are connected to
The configuration is such that each output is taken out as a data output by an OR circuit 32.

Therefore, the operation will be explained with reference to FIG. 8, which shows the case where the sampling clock frequency is twice the write gate frequency. First, digitized input data is input to the latch FF28, and the sampling clock is input to the latch FF28. It is latched by the lock A to produce data output B of D ₀ , D ₁ , D ₂ , . . . at the output terminal, and is input to the OR circuit 32. On the other hand, Latsuchi
Output B of FF28 is input to latch FF30 and latched by clock pulse A, and at its output terminal, D ₀ , D ₁ , D ₂ , . . .
. . generates data output C, which is similarly input to the OR circuit 32. As a result, the OR circuit 32 outputs D ₀ +
The signals D ₁ , D ₁ + D ₂ , D ₂ + D ₃ , D ₃ + D ₄ , D ₄ + D ₅ ... are sent, and the write gate E is set to D ₀ + D ₁ , D ₂ +
By generating the signals D ₃ , D ₄ +D ₅ , . . . at the timing when they are held, all data can be effectively written while leaving the time required for the read gate signal F. In FIG. 8, the time ratio between the write gate E and the read gate F is 1:2. Normally, for reflected signals from targets in radar or sonar, if the number of samplings is large enough, it is rare to obtain an individual target signal of only one unit, and in many cases data is collected over a sampling interval of multiple units. In order to avoid the loss of data, there is no problem in extracting a signal obtained by compressing and combining multiple data signals by sampling, and the latch method using the OR circuit shown in Figure 7 has a practical effect, so it can be fully used. .

In addition, in this embodiment, the frequency of the sampling clock is initially set high enough to sample a large number of data with good distance resolution to ensure that no data is dropped, and then these data are compressed and synthesized. do. For example, reduce the amount of data by 1/
Second, the memory capacity of the storage element can be reduced and the response frequency can be lowered, and the circuit can be constructed economically using a small amount of inexpensive elements.

Figure 9 does not perform a logical sum operation, but divides the input data into even numbered data and odd numbered data at each fixed time interval.
FIG. 10 is a block diagram showing another embodiment of the present invention in which data is separated into series data and written and read from separate storage devices, and FIG. 10 shows timing waveforms of each part. In FIG. 9, parts common to the embodiment of FIG. 5 are designated by the same reference numerals, and their explanations will be omitted.

In FIG. 9, latch FFs 34 and 36, storage device 14-1, latch FF 26-1, and AND circuit 40-1 constitute an even-numbered data processing sequence, latch FF 38, storage device 14-2, and latch FF 26-1.
-2 and AND circuit 42 constitute an odd-numbered data processing series.

To explain the operation of FIG. 9 with reference to FIG. 10, the digital input A is connected to the latch FF34, 3.
8 can be added to both. A sample clock φ ₁ for latching only even-numbered data is added to latch FF 34 _, and a sample clock φ ₂ for latching only odd-numbered data is added to latch FF 38. The period of ₂ is the same,
The phase of sample clock φ ₂ lags behind φ ₁ by half a period. As a result, even number data D ₀ , D ₂ , D ₄ , D ₆ , D ₈ , ... are latched in the latch FF 34,
In addition, the latch FF38 has odd number data D ₁ , D ₃ ,
D ₅ , D ₇ , D ₉ , . . . are latched to produce latch FF 34 output D and latch FF 38 output E, respectively. Furthermore, the output D of latch FF34 is
Since it is half a cycle ahead of the output E of 8, the latch
In addition to FF 36, the latch is latched by sample clock φ ₂ to obtain a latch output F that is in phase with the output E of latch FF 38. Thus, the output F of the latch FF36 is sent to the even storage device 14-1, and also to the latch FF
The outputs E of 38 are respectively input in parallel to the odd number storage device 14-2. Storage device 14-1, 14-
To write even number data and odd number data to 2, the address signal from the write address counter 16 is sent to the write gate G to the AND circuit 18.
The data are taken out at the timing of , and simultaneously executed under the write permission condition by the WE signal, and the operation is the same as that of the embodiment shown in FIG.

Also, data reading is performed using latch output data E,
Utilizing the timing in the second half of the holding time of F, it is sufficient to operate at a read clock frequency corresponding to the read time extended with respect to the write time. 1st
In the timing waveform of FIG. 0, the case where the time ratio is 1:2 is shown in detail, and the case where the time ratio is 1:4 is partially omitted.

Therefore, to explain the read operation using a case where the time ratio is 1:2 as an example, the storage devices 14-1, 14-2
For reading, read address counter 22
The address signal of
0, data outputs K2 and L2 are read out in common to each storage device 14-1, 14-2 and delayed by the address access time, and the respective latches are read out.
The data added to FFs 26-1 and 26-2 and read by latch clock P2 is held.
Next, in order to convert the parallel data signals up to the latches FF26-1 and FF26-2 into serial data signals, the even signal Q is given to the AND circuit 40-1, and the odd number signal is given to the AND circuit 40-2 and taken out alternately. , a composite signal R is obtained from the OR circuit 42.

In the embodiment of FIG. 9, the storage device 14
Since the parallel data read from -1, 14-2 is converted into serial data, the time width magnification of writing and reading is 1:1, 1:2, 1:4,...
The ratio is 1:2n, and the ratio cannot be an odd number. However, for example, the distance range of radar etc. often uses an even multiple such as 3 miles, 6 miles, 12 miles, or 24 miles, so even if the extended readout time ratio is limited to an even multiple, the display brightness will be reduced. Sufficient uniformity was obtained and there were no practical problems.

The practical advantages of the embodiment shown in FIG. 9 are as follows. In order to sample data received over a short range such as radar with good range resolution, it is necessary to increase the sampling frequency. For example 50MHz
If a sampling frequency of about 100% was applied to the device shown in Figure 5, general-purpose TTL elements would have problems with response, and extremely expensive high-speed elements (memory elements and logic elements) such as ECL would be required.

However, even if such a sampling frequency is applied to the device shown in FIG. 9, it operates with two sample clocks φ ₁ and φ ₂ that are half the original clock speed, that is, 25 MHz, as shown in FIG. 10. Since a memory element or the like can be used, it is possible to use a general-purpose and inexpensive element, and an extremely economical circuit configuration can be achieved, which has a large practical effect in terms of economics.

In addition, in the above embodiment, if it is desired to make the writing and reading time ratio an odd number multiple, it is sufficient to execute processing using the timing waveform shown in FIG. 11, and the difference from the timing waveform in FIG. 0 is as follows. Next 3
It becomes a point.

The first point is to write the output D of the latch FF 34 as it is to the even number storage device 14-1, and the second point is to write the output D of the latch FF34 to the even number storage device 14-1.
Two types of gates are required: G _EV and write gate G _OD for odd numbers, and the third point is that the read gate also has J _EV for even numbers and J _OD for odd numbers, and a latch clock for holding read data is also required for even numbers. P _EV and P _OD for odd numbers
Both types are required. Other timing operations are exactly the same as in the case of FIG. Also,
The circuit configuration for realizing the operation shown in FIG. 11 includes bypassing or removing the latch FF36 in the embodiment shown in FIG. 9 and directly connecting the output of the latch FF34 to the storage device 14-1; Address system for each storage device 14
This can be easily accomplished by making some changes, such as providing separate locations for each of -1 and 14-2.

Furthermore, the circuit configuration may be such that the time ratio can be selected as an even multiple or an odd multiple, and for example, the circuit configuration can be linked to changes in the distance range of radar etc., and the circuit configuration can be automatically changed according to the selected distance range. It can also be changed to obtain any ratio.

In the above embodiments, the ratio of the data read time to the data write time is an integral multiple, but it is also possible to set the ratio to be a fraction of an integral number. The reason for reducing the data read time compared to the data write time is that when the long distance range is set, the data read time also becomes longer in proportion to the data write time, and the brightness of the display becomes higher than necessary. Therefore, it is necessary to keep this display brightness uniform over the entire distance range. This is especially suitable when the radar screen is installed in a dark room or the like. Specifically, after data is written, the data written in the previous cycle is read in the next cycle.

Next, as another embodiment of the data processing method according to the present invention described above, a method in which interference wave processing is added will be described.

In general, in radar, sonar, etc., signals transmitted from other nearby ships produce interference waves such as vortices.
Removal of this interference wave is required, and the data processing method of this embodiment achieves uniformity of display brightness and removal of aperiodic interference waves.

FIG. 12 is a block diagram showing an embodiment of the present invention in which interference waves are removed by determining the correlation between received video data one cycle before and current received video data, and FIG. 13 is a block diagram showing an embodiment of the present invention. The timing waveforms of each part are shown. In FIG. 12, parts common to the embodiments shown in FIGS. 5 and 9 described above are denoted by the same reference numerals to simplify the explanation. Also,
#0 attached to transmission pulse A in FIG.
The numbers #1, #2, ... indicate the transmission numbers of the transmission pulses, and the even signal B is a signal for even/odd identification that is generated by the even number transmission pulse and ends with the odd number transmission pulse. storage device 14-1
A write gate signal C and a read gate signal D for the odd number storage device 14-2, a write gate signal E and a read gate signal F for the odd number storage device 14-2, a sweep signal G, and a correlation output signal H are shown, respectively.

The operation will be explained with reference to FIGS. 12 and 13. Now, when the first transmission pulse #0 is sent out and this received video signal is obtained, the even number storage device Data is written to and read from 14-1. However, for this first received video, since there is no past data on which correlation should be determined by the correlation circuit 50, the sweep signal G and the correlation output H are not generated. Next, when the #1 transmission pulse is sent out and the received video is obtained, the odd number storage device 14 -
Writing and reading of data to and from 2 is performed. At exactly the same timing as reading the odd numbered data from the storage device 14-2, the even numbered data obtained with the previous #0 transmission pulse is read from the storage device 14-1, and each readout output is a separate The signals are latched by the latches FF26-1 and FF26-2, and a correlation output signal H of both signals is obtained by the correlation circuit 50, which is added to the display together with the sweep signal G to be displayed.

As one specific example of the correlation circuit 50, an arithmetic circuit that calculates the product of both signals can be used.
Looking at this arithmetic circuit mathematically, if the time interval of one cycle is τ, then x(t)·x(t−τ), that is, an operation to obtain the product by multiplying both digital signals is executed. As another specific example, interference waves can be easily removed by using an AND circuit that simply takes out the AND of both signals as a digital logic operation, and the display brightness can be easily removed as in the above embodiment. can be controlled.

In the embodiment shown in FIG. 12, the even numbered video data and the odd numbered video data are written to the storage device 14-1 by applying the even numbered signal B to the AND circuit 44-1 for the even numbered data from the latch FF12. Odd-numbered data is alternately applied to the data input terminal of the storage device 14-1, and odd-numbered data is applied alternately to the data input terminal of the storage device 14-2 by an odd-numbered signal to the AND circuit 44-2.
Writing to 1 and 14-2 is performed by the write address counter 16, AND circuit 18, and OR circuit 20.
AND circuits 46-1, 46-2 that enable writing of the address signal and each data obtained through
This is done through the supply of the WE signal which is added below the even signal B and odd signal generation. Further, data reading from each of the storage devices 14-1 and 14-2 is also executed by the read address counter 22, AND circuit 24, and OR circuit 20 in the same manner as in the previous embodiment.

In addition, in the embodiments shown in FIGS. 12 and 13, for convenience of explanation, the case where the correlation with the received signal of one period before was calculated was explained. It is also possible to determine the correlation between a plurality of read signals from the previous cycle. For example, as a storage device, three series of RAM 1, 2, 3
Suppose that data is written periodically from RAM1 to RAM2 to RAM3 using The data before the cycle is also stored in RAM.
2 to 1 cycle ago, and these three data x(t-2τ), x(t-τ), and x
(t) By finding the correlation between each other,
It becomes possible to remove interference waves, and the effect is further improved.

Furthermore, if we focus on the fact that in order to remove interference waves, it is sufficient to read the received data in the past reception cycle and write the corresponding data in the current reception cycle, then using one series of RAM,
It turns out that it is sufficient to first read the data in the past reception cycle and then write the data in the current reception cycle. In the previous embodiments, the data write phase precedes the data read phase in all cases, but this phase relationship may be reversed. In other words, when the digital data retention time is divided into two, it is possible to write data using one of the two times and read data using the remaining time, either of which can be selected. It is determined whether it is desired to read data in the current cycle or data in a past reception cycle.

In the embodiment shown in FIG. 14, in order to eliminate interference waves, data of the past reception cycle is read from the storage device (RAM) in the first half of the digital data retention time, and data of the current reception cycle is written in the second half. Fig. 15 shows the timing waveforms of each part. In FIG. 14, the Andres counter 16 is used as a shared counter for specifying read and write addresses, and in FIG. 15, sample data D _o0 , D _o1 , D _o2 , D _o3 ,
... is the current n-th cycle data, and is also the read data that is the output of latch FF26-2.
D _(o-1)0 , D _(o-1)1 , D _(o-1)2 , . . . are data written in the (n-1)th cycle, which is one cycle before.

Its operation will become clear by referring to the timing waveforms in FIG. That is, the data at the address specified by the address counter 16 is sent to the latch FF 26-2 by the read gate D that occurs in the first half of the holding time of the sample data B, and the data at the address specified by the address counter 16 is sent to the latch FF 26-2, and by the write gate E that occurs following the end of the read gate D. , the sample data of the current cycle is written to the same location of the storage device 14 where data reading has been completed. On the other hand, sample data B given by the output of latch FF12 is simultaneously applied to latch FF26-1, and the sample data and read data are latched in latch FF26-1 and 26-2 according to the timing of latch clock F, and output from latch FF. G, H are supplied to the correlation circuit 50,
This is to obtain a correlation output of both data. Furthermore, the first
In FIG. 4, a processing system for writing and reading gate signals D and E to the storage device 14 is omitted.

The above embodiments were mainly explained using radar reception signals as an example, but the present invention is not limited to radar, and is applicable to periodic input signals such as sonar and ultrasonic flaw detectors. It can also be applied directly to signal processing.

〔Effect of the invention〕

As explained above, the data processing method of the present invention uses a first clock having at least one sampling clock within the width of the transmission pulse to receive a reception signal periodically obtained as a result of transmitting periodic transmission pulses. Digitized by sampling frequency,
Compressing and synthesizing the digital data using a compression ratio corresponding to the number of data,
Each compressed digital data output in each data compression cycle is divided into two times, and one of the two times is used to divide the retention time of each digital data into two.
data stored in the storage device is started in synchronization with the start of the writing operation of the writing device, and the writing device performs the time-sharing writing operation. The data is read from the storage device by a time-division operation using the third read frequency using the other of the time-divided data retention times that are not used.

Therefore, the effect of improving target object detection performance, which can detect short-time reflected signals from small targets that were sometimes not sampled when conventionally performing high-brightness display, and the data writing and reading operation for high-brightness display. The present invention has the economical effect that operations can be performed on the same storage device in substantially overlapping time periods, and that this can be achieved using fewer storage devices than in the past.

Further, since the data write time period and the data read time period substantially overlap, restrictions on selection of the frequency of the periodic signal are relaxed. After one display unit of data is read from the storage device, a considerable amount of time is left until the next display unit of data is read. Therefore, complex signal processing can be performed even on periodic signals of considerably high frequency.
For example, it performs various types of processing, such as using correlation processing to effectively eliminate interference signals caused by the mixing of aperiodic signals from nearby interference sources, and transmitting and receiving data in real time when used in conjunction with a collision prevention system. be able to.

As described above, the present invention not only prevents a decrease in display brightness on a display device such as a cathode ray tube by changing the data readout time, but also has the effect of speeding up data processing and improving the reliability of display data. .

[Brief explanation of drawings]

Fig. 1 is a waveform diagram showing real-time data from radar, etc. Fig. 2 is a block diagram showing a conventional data processing method using a storage device, and Fig. 3 is a timing waveform diagram of each part in the conventional method shown in Fig. 2. , 4th
The figure is a timing waveform diagram for explaining the principle of the data processing method of the present invention, Figure 5 is a block diagram showing an embodiment of the invention, and Figure 6 is the timing of each part in the embodiment of Figure 5. Waveform diagrams; FIG. 7 is a block diagram showing the OR operation section that can be replaced with latch FF12 in FIG. 5; FIG. 8 is a timing waveform of each part when the block in FIG. 7 is used in the embodiment shown in FIG. 5. 9 is a block diagram showing another embodiment of the present invention in which digital data is divided into two streams of even numbered data and odd numbered data, and FIG. 10 is a timing diagram of each part in the embodiment of FIG. 9. FIG. 11 is a timing waveform diagram when the ratio of read time to write time is an odd number, and FIG. 12 shows another embodiment of the present invention equipped with a correlation circuit for removing interference waves. FIG. 13 is a block diagram showing timing waveforms of various parts in the embodiment shown in FIG. 12. FIG. 14 is a block diagram showing another embodiment of the present invention for removing interference waves.
The figure is a timing waveform diagram of each part in the embodiment of FIG. 14. 1...Antenna, 2...Receiver, 3...AD converter,
4...Storage device, 5...Switcher, 6...Amplifier, 7...Display device, 8...Sweep signal generator, 10...Voltage comparator,
12, 26, 26-1, 26-2, 28, 303
4, 36, 38... Latch flip-flop (latch FF), 14, 14-1, 14-2... Storage device (random access memory/RAM), 16...
Write address counter, 22...Read address counter, 18, 24, 40-1, 40-2, 4
4-1, 44-2, 46-1, 46-2,...AND circuit, 20,32,42...OR circuit, 50...correlation circuit.

Claims (1)

[Claims] 1. Digitizing a received signal periodically obtained as a result of transmitting a periodic transmission pulse using a first sampling frequency having at least one sampling clock within the width of the transmission pulse. a conversion device; a data compression and synthesis device that compresses and synthesizes digital data obtained from the conversion device using a compression ratio corresponding to the number of data; compressed digital data output from the data compression and synthesis device; A storage device to which data is written and read, and each compressed digital data outputted from the data compression/synthesis device in each data compression cycle is divided into two time periods, one of which is the retention time of each digital data. a writing device that writes to the storage device, and a reading operation of data stored in the storage device, in synchronization with the start of the writing operation of the writing device, by a time-sharing operation using a second writing frequency. and the writing device reads from the storage device by a time-division operation at a third read frequency using the other of the time-division data holding times that are not used in the time-division write operation. a reading device, the first sampling frequency and the second writing frequency are set to have an integer ratio equal to the data compression ratio in the data compression and synthesis device, and the second writing frequency and the third The read frequency means that a write operation using the second write frequency and a read operation using the third read frequency, which are started in synchronization with the input of the periodically obtained received signal, are performed in synchronization with the input of the periodically obtained received signal. A data processing method characterized in that the data processing method is set to be an integer ratio within a range that ends within a period of . 2. The data processing system according to claim 1, wherein the compression and synthesis device performs compression and synthesis of data by calculating a logical sum of preceding and succeeding data among digitized data.