JPH0255752B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data processing device that digitizes periodic input information obtained from radar, sonar, etc. and processes the data in real time.

Conventionally, the most common signal display device for radar etc. starts the sweep current of the cathode ray tube display device at the same time as the transmission pulse is sent.
The reflected signals obtained from time to time are amplified and then added to the display device to display a target object image in real time. Looking at the temporal distribution of the received signal corresponding to one sweep signal in this conventional device,
The distance to the target corresponds to the elapsed time from the start of the sweep,
Since received data appears and disappears one after another as time passes, real-time data display processing is required.
FIG. 1 shows the transmission waveform A, sweep waveform B, and reception signal C in the radar over time on the horizontal axis, so that the above relationship can be understood.

However, for example, if the distance range of a radar is switched to multiple ranges from 1/4 mile to 120 miles, the ratio between the minimum and maximum time width of the sweep signal will be 450 times as large. If you display the received signal as it is in real time,
The brightness of the display device in the short range is significantly lower than that in the long range, and there is a drawback that this change in the brightness of the display device cannot be compensated for only by changing the repetition frequency of the transmission signal within the variable range. The reason for this is that the light emitting element of the cathode ray tube does not produce sufficient light transmission under very short electron beam energy.

The method that has been devised to date to solve these problems is to convert an analog video signal obtained from an antenna 1 through a receiver 2 into a digital signal using an A/D converter 3, as shown in Figure 2. , this digital data is sequentially written in a storage device 4 such as a shift register in real time in synchronization with the write clock CL1, and when all data writing is completed by continuous writing operation over a writing time period corresponding to the distance range to be displayed, The data written in the storage device 4 is sequentially read out from the switch 5 in synchronization with the read clock CL2, which has a frequency different from the write clock CL1, and is passed through the amplifier 6 to correspond to the sweep signal from the sweep signal generator 8. It is added to the display 7 and displayed. In this case, if the read clock CL2 is set to a sufficiently lower frequency than the write clock CL1 in the short range, a received signal extended in time will be supplied to the display 7. However, sufficient brightness can be obtained. FIG. 3 is a timing waveform diagram of the conventional device shown in FIG. 2, with transmission waveforms A,
Each of the received video signal B, write gate C, read gate D, read video signal E, and sweep signal F is represented with the horizontal axis as the time axis. As is clear from FIG. 3, the write operation time t ₁ and the read operation time t ₂
are separate and independent time periods in which the read operation time starts after the write operation time ends. Therefore, with this method, the writing time is
The sum of time (t ₁ + t ₂ ) of t ₁ and readout time t ₂ is required, and the repetition interval time of transmission signal A, that is, the period T of transmission signal A, must be larger than time (t ₁ + t ₂ ). There is. This restriction on the transmission signal period depending on the write time and read time causes a number of other problems. One of them is that the upper limit of the repetition frequency of the transmitted pulse is limited. That is, since the repetition frequency cannot exceed 1/(t ₁ +t ₂ )), it is kept low, and especially when the antenna rotation speed is high, the sweep density on the cathode ray tube becomes coarse and the image quality deteriorates. Second, when it is desired to read data from a storage device and perform necessary data processing due to the need for a collision prevention device, etc., the reading time is limited and the processing cannot be performed quickly.

An object of the present invention is to quantize a received signal from a radar, etc., temporarily store it in a storage device, and then read out the stored data and display it on a display device.
In addition to preventing echoes from falling off from small targets, which tend to occur in the past, the time required to write data to the rotating device and the time to read data from the same device are essentially overlapped, and the display brightness remains stable regardless of changes in the display distance range. An object of the present invention is to provide a data processing device designed to improve display image quality.

Embodiments of a data processing apparatus according to the present invention will be described below with reference to the drawings.

First, FIG. 4 shows a principle timing waveform diagram in the data processing apparatus of the present invention. That is, the received video signal B received by transmitting the transmitting pulse A having the pulse width τ transmitted at the period T is compressed in the number of data after quantization, and is compressed by the write signal C that starts with the generation of the transmitting pulse A. Sequential random access memory (hereinafter referred to as RAM)
All data compression and writing operations are completed during the reception time (i.e., the time required for writing) _t1 corresponding to the distance range to be displayed. On the other hand, the data previously written from the storage device is read out sequentially over the sweep time of the display device (i.e., the required reading time) t ₂ by the read signal D that starts at almost the same time as the write signal, and The output signal (corresponding to the reproduced video signal E) is applied to the display device together with the sweep signal F to display an image. As a result, it is possible to set the read time _t2 for all data to overlap the write time _t1 , and even when the write time _t1 changes due to a range change, the transmission signal When the period is single, there is no need to change the required readout time _t2 , so that sufficient target display brightness can be obtained on the display device. Further, when the device has a plurality of transmission signal periods, a plurality of readout required times _t2 can be set correspondingly to maintain uniformity of display brightness.

In the present invention, the reception signal obtained as a result of transmitting the periodic transmission pulse is stored in a digital storage device such as a RAM,
Since it is stored in an SN74S200 or the like, it is first converted from an analog signal to a digital signal by a quantization device. Further, this quantization device quantizes both the signal amplitude and the time direction of the input analog signal.

FIG. 5 is a block diagram showing an embodiment of a quantization device and a data number compression device according to the present invention, and FIG. 6 shows its basic timing waveform.

In FIG. 5, in order to quantize the input signal amplitude, the analog received signal is converted into a one-bit or multiple-bit digital quantity by an analog-to-digital converter (hereinafter referred to as an A/D converter). As a specific example of an A/D converter, a reference threshold level is set in the voltage comparator 10, and when this threshold level is exceeded, a logic level "1" is output.
Further, when the value is below the threshold value, a logic level "0" is obtained, thereby converting it into a 1-bit digital quantity. In actual equipment, multiple voltage comparators with different threshold levels are used to obtain a digital quantity of an arbitrary number of bits, but to simplify the explanation below, we will take the case of conversion to a 1-bit digital quantity as an example. explain.

Next, in order to quantize the input signal in the time direction, the output of the voltage comparator 10 is inputted to a latch flip-flop (hereinafter referred to as latch FF) 28 together with a sample clock pulse A (FIG. 6A). From the output of FF28, quantized data d ₀ , d ₁ , d ₂ ,
Data B (Fig. 6B) consisting of d ₃ ... is obtained. For the sample clock pulse A used here, in order to quantize the received video signal obtained corresponding to each distance range in real time, one or more types of frequencies are selected according to the following criteria.

The first criterion is that the repetition time width _tSC of sample clock A must be smaller than the transmission pulse width τ (see Figure 4) in order to sufficiently capture and display short-time reflected signals from small targets. This is desirable. To explain in detail, for example, suppose that a transmission radio wave with a pulse width τ is emitted. In this case, the time width of the received radio wave with the smallest time width is approximately τ. Such received radio waves include, for example, a signal reflected from a very thin tin plate. Therefore, in order to sample the received signal with the minimum time width using the sample clock pulse, if 1/τ = f ₀ , the frequency f of the sample clock pulse must be selected to be larger than f ₀ . According to the sampling theorem, it is desirable that f>2f ₀ . The first criterion is required from the above viewpoint. Furthermore, if the frequency f of the sample clock pulse is made smaller than the above f ₀ and the repetition time width t _SC is made larger than the transmission pulse width τ, the received signal with the minimum time width may not be sampled. Become.

The second criterion is that the number of sample data B obtained for each measurement distance range is a fixed quantity or an integral multiple of this, that is, 1, 2, 3..., N times, or 1/2, 1/3,...
The purpose is to determine the frequency of the sample clock pulse so that it becomes 1/N, etc. This is because when the data is then compressed and stored in the storage device, it is desirable that the storage capacity of the storage device be constant or an integral multiple of the same for each distance range.

The third criterion is to determine the sample clock frequency so that when these sample data are finally displayed on the cathode ray tube together with the sweep signal, the number of data is large enough to avoid deterioration of the image.

The number of sample data latched by sample clock A selected based on the above criteria is:
The number differs depending on each measurement distance range. On the other hand, the amount of data required for display on a display device is a fixed number determined by the size of the display screen and the resolution of display pixels. Further, the number of data stored in the storage device may be the same as the number of data required for this display. Generally, in medium and long distance ranges, the number of quantized data quantized by sample clock A according to the first criterion is greater than the number of data required for display (i.e., the number of data stored in the storage device). It often happens.

Therefore, in the present invention, the ratio between the number of quantized data and the number of data stored in the storage device is set such that n is 1,
Set the number of data to be stored/number of quantized data = 1/n, where n is a natural number of 2, 3, etc. The number of data is compressed according to natural numbers (1, 2, 3, etc.).

With reference to FIGS. 5 and 6, the compression operation of the number of data will be explained by taking as an example the case where the number of quantized data is twice the number of stored data (ie, n=2). As explained above, the output of the latch FF 28 produces the data output B of the quantized data d ₀ , d ₁ , d ₂ , d ₃ . is input. On the other hand, Latsuchi FF
The output B of FF 28 is input to the latch FF 30 and latched by the clock pulse A.
Sequentially d ₀ , d ₁ , d ₂ , d ₃ ... with a delay of one cycle.
A data output C is produced and similarly inputted to the other side of the OR circuit 32. As a result, the OR circuit 32 outputs d ₀
Signals D of +d ₁ , d ₁ +d ₂ , d ₂ +d ₃ , d ₃ +d ₄ , d ₄ +d ₅ , . . . are transmitted. Therefore, a latch clock F for latching the output signal D of the OR circuit 32 or a write gate E for directly storing it in a memory device is required.
The write data D ₀ is generated at the timing when the signals d ₀ + d ₁ , d ₂ + d ₃ , d ₄ + d ₅ , ... are held.
= d ₀ + d ₁ , D ₁ = d ₂ + d ₃ , D ₂ = d ₄ + d ₅ , etc. can be generated.

By compressing the number of data in this way, the information originally held by the quantized data is not lost.
That number can be compressed in half and effectively written to storage. When n is another natural number, the number of data is compressed in exactly the same way. However, the number of data is not compressed only when n=1. Further, when the value of the quantized data is a plurality of bits, the number of data is compressed by outputting the largest data among the plurality of data values.

Furthermore, by setting the ratio between the number of quantized data and the number of data to be stored as n:1, the ratio between the sample clock frequency and the data writing frequency naturally becomes n:1.

In this way, in the quantization device and data compression device of the present invention, the frequency of the sampling clock is initially set high enough, and a large number of data with good distance resolution are sampled to ensure that the data is consistent. After that, the number of quantized data is compressed and synthesized to the number of data to be stored in the storage device (i.e., the number of data required to be displayed on the display device) so as not to lose the information held by these data. are doing. Therefore, it is possible to reduce the memory capacity and response frequency of the storage device in which data is to be stored, and there is an advantage that the circuit can be constructed economically by using a small amount of inexpensive elements.

FIG. 7 is a block diagram showing an embodiment of a storage device, a writing device, and a reading device according to the present invention, and FIG. 8 is a basic timing waveform diagram thereof.

In FIG. 7, 12 and 26 are latch FF, 1
4, 14' are digital storage devices such as RAM, 16
is a write address counter, 18 and 24 are AND circuits, and 20 is an OR circuit 22 is a read address counter.

Now, the compressed quantized data from the output of the OR circuit 32 in FIG. 5 is input to the latch FF12 in FIG.
In addition, the latch clock A with the period t _LC (in FIG. 6, t _LC = 2×t _SC ) shown in FIG. 8 also latches.
As a result of being input to FF12, the output of latch FF12 is the data latched by latch clock A.
D ₀ , D ₁ , D ₂ , D ₃ ...D _o are obtained. These data D ₀ to _{D o} are obtained within the reception time corresponding to the distance range to be displayed after generation of a periodic transmission pulse from a radar or the like. These data D ₀ to _{D o} are sequentially written to the corresponding addresses of the memory device 14 under the supply of the address signal over the time of the write gate signal. Write gate C is activated by latch clock A and terminates after half the repetition time of latch clock A, t _LC /2. That is, the write gate signal C is valid only during the first half of the latch data holding time. In terms of circuit,
A write clock having the same cycle as latch clock A is input to the write address counter 16, and the AND circuit 18 extracts the logical product of the address data taken out from the output thereof and the write gate signal C. Connect to address output terminal AI.

In this example, RAM (74S200) is used as the storage device.
The memory capacity is 256 bits, and an address can be specified using 8-bit address data. However, if a larger memory capacity is required, multiple RAMs are used and an address counter is used. 16 upper bits (9 bits or more)
If you connect the inverted signal of the decoded output to the RAM CS terminal (chip selection terminal), the corresponding
It is now possible to select the RAM IC chip.

Furthermore, data writing to RAM as the storage device 14 is performed using WE (Write Enable) in addition to address specification.
The WE signal timing and time width are specified by each RAM standard, and the WE signal shown in Figure 8 is required.
As shown in signal D, the required setup time t _WS until the WE signal is input, the hold-up time t _WH of the address signal that needs to be continued even after the WE signal is invalidated, and the required time t _WE of the WE signal. Each of these is determined to meet the standards of the RAM being used. Thus, the data to be written D ₀ ,
The signals from the address counter 16 specifying the addresses corresponding to D ₁ , D _{2 ,} . The compressed and quantized received video signal is sequentially written in real time by supplying it to the RAM as a quantized video signal.

Next, reading of written data will be explained with reference to FIGS. 7 and 8. Data reading from the storage device 14 is performed at a read frequency that is the same as or different from the write frequency.

In the present invention, the ratio between the write frequency and the read frequency is set to m:1 or 1:m, where m is a natural number of 1, 2, 3, . . . . Note that since frequency and time have a reciprocal relationship, the relationship between the data write time and data read time and the write and read frequencies is as follows: data write time/data read time = read frequency/write frequency.

In the present invention, since both the data write operation and the data read operation to the storage device 14 are started from the generation of a periodic transmission pulse, the data write time is started immediately after the generation of the transmission pulse, and the data write time is started immediately after the transmission pulse is generated. It ends with the expiration of the receive time corresponding to the range, and the data read time begins immediately after a transmit pulse occurs and ends before the next transmit pulse occurs. Therefore, within the constraints of the data write time and read time, the write frequency and read frequency should be at a ratio of m:1.
Or 1:m (where m is a natural number of 1, 2, 3,...)
It can be determined that

Generally, when the display range is a short distance range and the data writing time is short, the ratio of the writing frequency to the reading frequency is set to m:1. When displaying the data written from the received signal to the storage device in real time, for example, set m = 2, 3, 4, etc., and expand the time by m times and display it on the display screen of the display device. Even if the distance range is small,
This is because the brightness of the image displayed on the display screen can be made sufficient.

Generally, when the display range is a long distance range and the data writing time is long, the ratio of the writing frequency to the reading frequency is set to 1:m. In this case m=
Even if it is 1, the real-time data writing time is long, so even if the data reading time is made equal to the writing time, sufficient display brightness of the display device can be obtained. Also m
If =2, the data read time is 1/2 of the data write time, so the same data can be read out twice, and the image quality can be improved by increasing the number of sweeps of the display device. In this case, data written in the previous cycle is read out and displayed in the current cycle.

In FIG. 8, for read gate E, data output F, latch clock G, and latch output H, the ratio of data write time/data read time=frequency of latch clock G/frequency of latch clock A is 1/1, respectively. The cases of 1/2 and 1/3 are shown.

Now the ratio of data write time to read time is 1/
Taking case 2 as an example, the read clock frequency is half the write clock frequency.
This read clock is the read address counter 2.
The address data specifying the read address of the storage device 14, which is supplied to the AND circuit 24, and the read gate signal _E2 generated subsequent to the write gate C are input to the AND circuit 24, and this output signal is sent to the storage device 14. 14. That is, the read gate signal
E ₂ is a signal having a time width t _LC /2 that starts in synchronization with the end of the write gate signal C and ends with the generation of the next latch clock A, and its generation rate is proportional to the period of the read clock. As a result,
The read gate signal is the holding time of latch data B.
t Valid only in the second half of _LC . Read this gate
Regarding _E2 , first, the readout gate signal _E2 for reading out the "0" address is generated with a time width of approximately _tLC /2 in the latter half of the time when the latch data _D0 is held.
The read gate signal _E2 at the next address "1" is generated approximately in the latter half of the time when the latch data _D2 is held.
These occur sequentially with a time width of t _LC /2.

Upon generation of read gate signal E ₂ , AND circuit 2
When read address data is supplied from 4 to the memory circuit 14 via the OR circuit 20, after a certain period of time _TAA (address access time) has elapsed from the start of the read gate signal _E2 , the data at the specified address is read from the memory device 14. is read, producing data output _F2 . That is, for address “0” designation, data D ₀
However, for the "1" address designation, data _D1 is sequentially read out. This output data _F2 is latch FF
26 with latch clock _G2 to hold the data read from storage 14 until the next latch clock is input. As a result, the latch output _H2 of the latch FF 26 is sent out as data extended to twice the holding time of the latch data B.

As described above, in the storage device, writing device, and reading device of the present invention, the ratio of the writing frequency to the reading frequency for the storage device is m:1 or 1:m (where m is a natural number of 1, 2, 3, etc.). By doing so, the compressed quantized data written in real time can be expanded to m times the time or reduced to 1/m time and read out, and the video can be displayed with sufficient brightness and good image quality on the display device. can.

In addition, since the writing time and reading time of data to the storage device can substantially overlap, while the received data of the current transmission cycle is being written to the display device, the written received data of the current cycle can be simultaneously written. can be read and displayed. Therefore, data that is not delayed by one cycle can be displayed. Note that since the latter half of the time after the end of the write gate signal C is left open for reading, interrupt reading is also possible at a timing when the read gate E for reading data for display is not generated. For example, when the ratio of data write time to data read time is 1/3, by specifying an arbitrary address using the timing in the latter half of the holding time of latch data _D1 and _D2 , it is possible to Interrupt read operation becomes possible.

In the explanation of the embodiment shown in FIGS. 7 and 8, it was explained that the data is written at the timing of the first half of the holding time of latch data B, and the data is read at the timing of the latter half. It is also possible to reverse it. That is, the reception data may be read using the transmission pulse of the previous cycle at the timing of the first half of the holding time of latch data B, and the reception data may be written using the transmission pulse of the current cycle at the timing of the second half. In this case, since the received data of the same distance one cycle before can be read during the holding time of the received data of the current cycle, it is possible to perform correlation processing on the data of the two cycles to remove interference waves.

As explained above, the data processing device of the present invention converts a received signal obtained as a result of transmitting a periodic transmission pulse into a signal amplitude using a sampling frequency having at least one sampling clock within the transmission pulse width. Quantize in the time direction,
The number of quantized data obtained as a result is compressed to the number of data that should be stored in the storage device before being stored, which improves the reliability of display data by preventing echoes from falling off from small targets, and improves the reliability of display data. This has the effect of reducing the cost of the device by reducing the memory capacity of the device and lowering the response frequency.

In addition, the writing time and reading time of data to the storage device are made to substantially overlap, and the ratio of the writing time and reading time is set to 1:m or m:1 (where m is 1,
2, 3, etc.), the display brightness is improved by increasing the readout time in the short distance display range, and the display image quality is improved by increasing the number of sweep circuits in the long distance display range.

[Brief explanation of drawings]

Figure 1 is a waveform diagram showing real-time data from radar, etc. Figure 2 is a block diagram showing the configuration of a conventional data processing device using a storage device, Figure 3 is the timing of each part in the conventional device shown in Figure 2. A waveform diagram, FIG. 4 is a timing waveform diagram for explaining the principle of the data processing device of the present invention, and FIG. 5 is a block diagram showing an embodiment of the quantization device and data number compression device according to the present invention. 6 is a timing waveform diagram of each part in the embodiment of FIG. 5, FIG. 7 is a block diagram showing an embodiment of a storage device, a writing device, and a reading device according to the present invention, and FIG.
FIG. 4 is a timing waveform diagram of each part in the illustrated embodiment. In the figure, 1...antenna, 2...receiver,
3...A/D converter, 4...Storage device, 5...Switcher, 6...Amplifier, 7...Display device, 8...Sweep signal generator, 10...Voltage comparator, 12, 26 …
...Latch flip-flop (Latch FF), 14,
14'...Storage device (random access memory, RAM), 16...Write address counter,
22...Read address counter, 18, 24...
...AND circuit, 20,32...OR circuit.

Claims (1)

[Claims] 1. A received signal obtained as a result of transmitting a periodic transmission pulse is quantized in the signal amplitude and time direction using a sampling frequency having at least one sampling clock within the width of the transmission pulse. A quantization device; Compressing the number of data for the quantized data obtained from the quantization device using a ratio of n:1 where n is a natural number to obtain the number of quantized data to be written to the storage device. a compression device; a storage device into which compressed quantized data outputted from the compression device is written and read; The compressed quantized data output from the compression device is
a writing device that writes to the storage device at a writing frequency; and a writing device that writes compressed quantized data written to the storage device in a time period from after transmission of the periodic transmission pulse to before transmission of the next transmission pulse. , a reading device that reads data from the storage device at a reading frequency, and the sampling frequency and the writing frequency are defined by a ratio between the number of quantized data obtained from the quantization device and the number of data to be written to the storage device. A data processing device characterized in that the write frequency and the read frequency are set to have an equal ratio, and the write frequency and the read frequency are set to have a ratio of m:1 or 1:m, where m is a natural number.