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JPH0150098B2 - - Google Patents
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JPH0150098B2 - - Google Patents

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Publication number
JPH0150098B2
JPH0150098B2 JP58020593A JP2059383A JPH0150098B2 JP H0150098 B2 JPH0150098 B2 JP H0150098B2 JP 58020593 A JP58020593 A JP 58020593A JP 2059383 A JP2059383 A JP 2059383A JP H0150098 B2 JPH0150098 B2 JP H0150098B2
Authority
JP
Japan
Prior art keywords
film
titanium
metal
diffusion layer
silicide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP58020593A
Other languages
Japanese (ja)
Other versions
JPS59150421A (en
Inventor
Katsuya Okumura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP58020593A priority Critical patent/JPS59150421A/en
Publication of JPS59150421A publication Critical patent/JPS59150421A/en
Publication of JPH0150098B2 publication Critical patent/JPH0150098B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/01Manufacture or treatment
    • H10D64/011Manufacture or treatment of electrodes ohmically coupled to a semiconductor

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  • Electrodes Of Semiconductors (AREA)

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明は、半導体基板の拡散層或いは半導体
基板上の上部膜として形成された半導体層の低抵
抗化を図るために半導体部に金属シリサイドが形
成された半導体装置の製造方法に関する。
[Detailed Description of the Invention] [Technical Field of the Invention] This invention relates to a method in which metal silicide is formed in a semiconductor portion in order to lower the resistance of a semiconductor layer formed as a diffusion layer of a semiconductor substrate or an upper film on a semiconductor substrate. The present invention relates to a method of manufacturing a semiconductor device.

〔発明の技術的背景〕[Technical background of the invention]

近年の半導体装置の高集積化、性能の高度化に
伴つて装置の高速化が要求され、半導体基板に形
成された拡散層やポリシリコン(多結晶シリコ
ン)膜などのシート抵抗を低減させることが必要
となつている。
In recent years, as semiconductor devices have become more highly integrated and their performance has become more sophisticated, higher speed devices are required, and it is becoming increasingly important to reduce the sheet resistance of diffusion layers and polysilicon (polycrystalline silicon) films formed on semiconductor substrates. It has become necessary.

このような要請に対処するため、拡散層や上部
膜としてのポリシリコン膜上に高融点金属のシリ
サイドを形成させる手段がいくつか提案されてい
る。
In order to meet these demands, several methods have been proposed for forming silicide of a high melting point metal on a polysilicon film serving as a diffusion layer or an upper film.

その中の代表的な手段の概略は次のようなもの
である。まず半導体(シリコン)基板上にフイー
ルド酸化膜およびゲート酸化膜を形成すると共に
基板内に所定の拡散層を形成し、ゲート酸化膜上
にはゲート電極としてポリシリコン配線を形成す
る。続いてこのような半導体基板上にチタン膜を
被着する。その後、この半導体基板に500℃〜600
℃で熱処理を施すと、チタン膜中のチタンとチタ
ン膜下に接触しているシリコンとが反応し、ポリ
シリコン配線上および拡散層上にチタンシリサイ
ド層が形成される。また、酸化シリコンとチタン
とは反応しないため、酸化膜と接している部位の
チタン膜はチタンシリサイドにはならずにチタン
膜として残る。
An outline of the representative means is as follows. First, a field oxide film and a gate oxide film are formed on a semiconductor (silicon) substrate, a predetermined diffusion layer is formed in the substrate, and a polysilicon wiring is formed as a gate electrode on the gate oxide film. Subsequently, a titanium film is deposited on such a semiconductor substrate. After that, this semiconductor substrate is heated to 500℃~600℃.
When the heat treatment is performed at .degree. C., the titanium in the titanium film reacts with the silicon that is in contact with the bottom of the titanium film, and a titanium silicide layer is formed on the polysilicon wiring and the diffusion layer. Further, since silicon oxide and titanium do not react, the titanium film in the portion in contact with the oxide film does not become titanium silicide but remains as a titanium film.

次いで拡散層およびポリシリコン配線層上のチ
タンシリサイド膜が分離するように化学エツチン
グなどにより半導体基板上に残つた未反応のチタ
ン膜を除去する。このようにしてそれぞれ拡散層
上およびポリシリコン配線層上にチタンシリサイ
ド膜を形成し、これら拡散層およびポリシリコン
配線層のシート抵抗を低減せしめる。
Next, the unreacted titanium film remaining on the semiconductor substrate is removed by chemical etching or the like so that the titanium silicide film on the diffusion layer and the polysilicon wiring layer is separated. In this way, a titanium silicide film is formed on the diffusion layer and the polysilicon wiring layer, respectively, and the sheet resistance of these diffusion layers and the polysilicon wiring layer is reduced.

〔背景技術の問題点〕[Problems with background technology]

従来のこのような金属シリサイド膜による素子
高速化対策には次のような問題点があつた。すな
わち、第1図aに示すように半導体基板11に形
成された拡散層13に一部重なるようにゲート酸
化膜12Gとポリシリコン層14とが積層形成さ
れているものにチタン膜15を被着した後熱処理
を行なうと、ゲート酸化膜12Gが極めて薄いた
めゲート酸化膜12Gの側面に被着した側壁チタ
ン膜15aに拡散層13およびポリシリコン膜1
4からシリコンが拡散してしまう。そして、この
シリコンと側壁チタン膜15aとが反応してチタ
ンシリサイド膜となり、その後未反応チタンの除
去工程を行なつても除去できずに残り、結果的に
ポリシリコン膜14と拡散層13とが電気的に短
絡してしまう確率が極めて高いものであつた。
Conventional measures to increase device speed using metal silicide films have the following problems. That is, as shown in FIG. 1a, a titanium film 15 is deposited on a stacked structure of a gate oxide film 12G and a polysilicon layer 14 so as to partially overlap a diffusion layer 13 formed on a semiconductor substrate 11. When heat treatment is performed after this, since the gate oxide film 12G is extremely thin, the diffusion layer 13 and the polysilicon film 1 are formed on the sidewall titanium film 15a deposited on the side surface of the gate oxide film 12G.
Silicon diffuses from 4. Then, this silicon reacts with the sidewall titanium film 15a to form a titanium silicide film, which remains unremoved even after a subsequent step of removing unreacted titanium, and as a result, the polysilicon film 14 and the diffusion layer 13 are The probability of an electrical short circuit was extremely high.

また、熱処理中に拡散層13中のシリコンがフ
イールド酸化膜12Fの段差部に被着した側壁チ
タン膜15bを経てフイールド酸化膜12F上の
チタン膜15にまで拡散し続け、拡散層13中の
シリコンが不足して第1図bの13aに示すよう
についにはチタンシリサイドがこの拡散層13を
つき抜け拡散層13のPN接合を破壊してしまう
場合があつた。
Furthermore, during the heat treatment, the silicon in the diffusion layer 13 continues to diffuse into the titanium film 15 on the field oxide film 12F through the sidewall titanium film 15b deposited on the stepped portion of the field oxide film 12F, and the silicon in the diffusion layer 13 continues to diffuse into the titanium film 15 on the field oxide film 12F. In some cases, the titanium silicide eventually penetrated through the diffusion layer 13 and destroyed the PN junction of the diffusion layer 13, as shown at 13a in FIG. 1B.

〔発明の目的〕[Purpose of the invention]

この発明は上記のような点に鑑みなされたもの
で、その目的とするところは拡散層や半導体基板
上に形成されたポリシリコン膜などへ簡易な手段
によりそれぞれ低抵抗化を図るべき領域ごとに金
属シリサイドを分離して形成でき、歩留りの向上
と装置の高速化とを両立できる半導体装置の製造
方法を提供しようとするものである。
This invention was made in view of the above points, and its purpose is to apply simple means to the diffusion layer, the polysilicon film formed on the semiconductor substrate, etc. in each region where the resistance should be reduced. It is an object of the present invention to provide a method for manufacturing a semiconductor device in which metal silicide can be formed separately and which can both improve yield and increase the speed of the device.

〔発明の概要〕[Summary of the invention]

すなわちこの発明に係る半導体装置の製造方法
では、急峻な段差部あるいは逆テーパ状の段差部
に金属膜を蒸着形成すると段差部面の蒸着粒子が
いわゆる斜め蒸着といわれるように粗に堆積した
り、蒸着粒子の付着しないいわゆる異常に蒸着し
た部分ができ、この異常に蒸着した部分の金属膜
のエツチング速度が平坦部に蒸着した金属膜より
も速くなる現象を利用してあらかじめこの部分の
金属を除去するものである。すなわち、まずフイ
ールド酸化膜やポリシリコン膜などの上部膜を
RIE(反応性イオンエツチング)法やスパツタ法
などの急峻な段差が得られるエツチング法により
エツチングした半導体基板上に、金属シリサイド
となり得る例えばチタン、モリブデンなどの金属
膜を形成する。続いて上記金属膜を例えばウエツ
トエツチングにより段差部における金属膜が除去
されるまでエツチングし、上記金属膜を基板表面
の段差部に沿つてそれぞれ独立した金属膜に分割
する。この後熱処理を行ない拡散層或いはポリシ
リコン膜上などシリコン上に形成された金属膜を
シリサイド化した後適宜シリサイド化されなかつ
た金属膜を除去するものである。
That is, in the method for manufacturing a semiconductor device according to the present invention, when a metal film is formed by vapor deposition on a steep step portion or a reversely tapered step portion, vapor deposition particles on the surface of the step portion may be deposited coarsely as in so-called oblique vapor deposition. A so-called abnormally deposited area is created where no deposited particles adhere, and the metal in this area is removed in advance by taking advantage of the phenomenon that the etching rate of the metal film in this abnormally deposited area is faster than that of a metal film deposited on a flat area. It is something to do. That is, first, the upper film such as field oxide film or polysilicon film is
A metal film of titanium, molybdenum, or the like, which can be a metal silicide, is formed on a semiconductor substrate that has been etched by an etching method capable of forming steep steps, such as RIE (reactive ion etching) or sputtering. Subsequently, the metal film is etched, for example, by wet etching until the metal film at the step portion is removed, and the metal film is divided into independent metal films along the step portion on the surface of the substrate. Thereafter, a heat treatment is performed to silicide the metal film formed on the silicon, such as on the diffusion layer or the polysilicon film, and then the metal film that has not been silicided is appropriately removed.

〔発明の実施例〕[Embodiments of the invention]

以下図面を参照してこの発明の一実施例を説明
する。第2図において半導体基板11の一部領域
に接合深さが約0.2μmの拡散層13を形成すると
共に、半導体基板11上には上部膜として約1μm
の膜厚のフイールド酸化膜12F、約200Åの膜
厚のゲート酸化膜12Gおよび膜厚が約4000Åの
ポリシリコン膜14をそれぞれ形成する。これら
の複数の上部膜のパターニングは急峻な段差が得
られるように例えばRIE法を用いる。
An embodiment of the present invention will be described below with reference to the drawings. In FIG. 2, a diffusion layer 13 with a junction depth of about 0.2 μm is formed in a part of the semiconductor substrate 11, and an upper film with a depth of about 1 μm is formed on the semiconductor substrate 11.
A field oxide film 12F with a thickness of approximately 200 Å, a gate oxide film 12G with a thickness of approximately 200 Å, and a polysilicon film 14 with a thickness of approximately 4000 Å are respectively formed. For patterning these plurality of upper films, for example, RIE method is used so as to obtain steep steps.

なお、現在では集積回路装置におけるパターニ
ングは、装置の高集積化、微細化を図るためRIE
法やスパツタ法などエツチング断面が略垂直にエ
ツチングでき横方向エツチングの殆んど生じない
異方性エツチングが広く用いられている。
Currently, patterning in integrated circuit devices is performed using RIE to achieve higher integration and miniaturization of devices.
Anisotropic etching methods such as the etching method and the sputtering method, in which the etching cross section can be etched substantially vertically and almost no lateral etching occurs, are widely used.

続いて、この基板11の上表面に、基板11の
温度を10℃〜15℃に冷却した状態でチタン膜15
を膜厚がおよそ1500Åとなるように蒸着する。こ
の際にチタンの蒸着粒子ができるだけ基板表面に
垂直に入射するようにする。このように、基板1
1を10℃〜15℃に冷却し蒸着粒子を基板表面に平
均して略垂直に飛ばして蒸着を行なうと、急峻な
段差部面においていわゆる斜め蒸着と言われるよ
うに蒸着金属が粗く異常成長し、異常成長部Aが
形成される。
Next, a titanium film 15 is formed on the upper surface of this substrate 11 while the temperature of the substrate 11 is cooled to 10°C to 15°C.
is deposited to a thickness of approximately 1500 Å. At this time, the titanium vapor deposition particles are made to be incident as perpendicularly to the substrate surface as possible. In this way, the substrate 1
1 is cooled to 10°C to 15°C and the evaporated particles are averaged and evaporated almost perpendicularly to the substrate surface for evaporation. This causes the evaporated metal to grow coarsely and abnormally on steeply stepped surfaces, which is referred to as oblique evaporation. , an abnormal growth part A is formed.

次いでこの蒸着されたチタン膜15をエチレ
ン・ジアミンテトラアセテイツク・アシツド
(EDTA)を主成分としたエツチヤントで約500
Åエツチングする。
Next, this vapor-deposited titanium film 15 is treated with an etchant containing ethylene diamine tetraacetate acid (EDTA) as a main component for approximately 500% of the titanium film 15.
Å Etching.

ここで、上記異常成長部Aは正常に密に形成さ
れたチタン膜15に比らべ約5倍〜10倍のエツチ
ング速度でエツチングされる。
Here, the abnormally grown portion A is etched at an etching speed about 5 to 10 times that of the normally densely formed titanium film 15.

従つて、エツチング後は第2図bに示すように
前記異常成長部Aが完全に除去され、フイールド
酸化膜12FF上、拡散層13上およびポリシリ
コン膜14上のそれぞれに形成されたチタン膜1
5が分割された状態で残る。
Therefore, after etching, as shown in FIG. 2b, the abnormal growth part A is completely removed, and the titanium film 1 formed on the field oxide film 12FF, the diffusion layer 13, and the polysilicon film 14 is removed.
5 remains in a divided state.

続いて400℃〜500℃で上記半導体基板11を熱
処理し、拡散層13上およびポリシリコン膜14
上のチタン膜15をシリサイド化させ、第2図c
に示すように拡散層13およびポリシリコン膜1
4上のそれぞれにチタンシリサイド膜16を形成
する。ここで、段差部にはチタン膜が残存してい
ないため、拡散層13上とポリシリコン膜14上
のチタンシリサイド膜16との連結や、拡散層1
3中のシリコンがフイールド酸化膜12F上のチ
タン膜15に拡散する現象は生じない。また、フ
イールド酸化膜12F上のチタン膜15はシリコ
ンと接していないため、シリサイド反応を起こさ
ない。
Subsequently, the semiconductor substrate 11 is heat-treated at 400° C. to 500° C., and the polysilicon film 14 and the top of the diffusion layer 13 are heated.
The upper titanium film 15 is silicided, and as shown in FIG.
As shown in FIG.
A titanium silicide film 16 is formed on each of the layers 4 and 4. Here, since no titanium film remains in the stepped portion, the connection between the titanium silicide film 16 on the diffusion layer 13 and the polysilicon film 14, and the
The phenomenon that silicon in 3 diffuses into the titanium film 15 on the field oxide film 12F does not occur. Furthermore, since the titanium film 15 on the field oxide film 12F is not in contact with silicon, no silicide reaction occurs.

続いて、フイールド酸化膜12F上の未反応の
チタン膜15を化学的に除去すれば、拡散層13
やポリシリコン層14など半導体部上にチタンシ
リサイド膜16が、半導体基板上の段差部に沿つ
て分割された状態で形成される。
Subsequently, by chemically removing the unreacted titanium film 15 on the field oxide film 12F, the diffusion layer 13
A titanium silicide film 16 is formed on a semiconductor portion such as a polysilicon layer 14 in a divided state along a step portion on a semiconductor substrate.

以上のように例えば拡散層13およびポリシリ
コン膜14は互いにシヨートすることなくシート
抵抗値を著しく低減されたものとなる。
As described above, for example, the diffusion layer 13 and the polysilicon film 14 do not shoot each other and have a significantly reduced sheet resistance value.

ここで、上記実施例では段差部においてチタン
膜15を斜め蒸着させ平坦部ではチタン粒子が密
に蒸着するようにさせ、軽いエツチングにより段
差部に付着したチタン膜15のみを選択的に除去
する。また拡散層13或いはポリシリコン膜14
は、所定のパターンの拡散層13の領域やポリシ
リコン膜14となるように酸化膜やポリシリコン
層をパターニングして形成するため必ず上記拡散
層13やポリシリコン膜14のパターンに沿つて
段差が形成される。従つて、上記チタン膜15の
異常成長部Aのエツチング工程において、マスク
パターンなどを必要とせずに丁度上記拡散層13
やポリシリコン膜14のパターンに沿いセルフア
ラインでチタン膜15が各領域ごとに分割され
る。
Here, in the above embodiment, the titanium film 15 is obliquely deposited on the stepped portion, titanium particles are densely deposited on the flat portion, and only the titanium film 15 attached to the stepped portion is selectively removed by light etching. In addition, the diffusion layer 13 or the polysilicon film 14
Since the oxide film or the polysilicon layer is patterned to form the region of the diffusion layer 13 or the polysilicon film 14 in a predetermined pattern, there is always a difference in level along the pattern of the diffusion layer 13 or the polysilicon film 14. It is formed. Therefore, in the etching process for the abnormally grown portion A of the titanium film 15, the diffusion layer 13 can be etched without the need for a mask pattern.
The titanium film 15 is divided into regions by self-alignment along the pattern of the polysilicon film 14.

なお、上記実施例では拡散層13やポリシリコ
ン膜14と金属シリサイドを形成させる金属して
チタンを用いる場合につき述べたが、これはチタ
ンの代りにモリブデン、タングステン、タンタ
ル、白金、コバルト、アルミニウムなどシリコン
と反応し金属シリサイドを形成するものであれば
他のものでも良い。
In the above embodiment, titanium is used as the metal for forming the metal silicide with the diffusion layer 13 and the polysilicon film 14, but molybdenum, tungsten, tantalum, platinum, cobalt, aluminum, etc. can be used instead of titanium. Other materials may be used as long as they react with silicon to form metal silicide.

また、上記実施例では段差部を急峻にして段差
部側面のチタン膜15を斜め蒸着する場合につき
述べたが、例えば第3図に示すようにチタンシリ
サイド膜を分離した状態で形成させるべき部位の
段差部Bを逆テーパ状にして以下前述と同様の手
順で分離したチタンシリサイド膜を形成すること
ができる。この場合には、チタン膜15が図のよ
うに段切れを起こし易く、段差部Bの側面にチタ
ンが充分に被着しないため、前記実施例と同様に
チタンの軽いエツチングによつて段差部B付近の
チタン膜を完全に除去することができ、金属シリ
サイド膜間のシヨートやPN接合部の接合破壊な
どの発生を防止できる。
In addition, in the above embodiment, the case where the step part is made steep and the titanium film 15 on the side surface of the step part is obliquely vapor-deposited is described, but for example, as shown in FIG. After forming the stepped portion B into a reverse tapered shape, a separated titanium silicide film can be formed in the same manner as described above. In this case, the titanium film 15 is likely to break off as shown in the figure, and since titanium is not sufficiently adhered to the side surfaces of the stepped portion B, the stepped portion B is etched by light etching of titanium as in the previous embodiment. The nearby titanium film can be completely removed, and the occurrence of shorts between metal silicide films and junction breakdown at the PN junction can be prevented.

〔発明の効果〕〔Effect of the invention〕

以上のようにこの発明によれば、金属シリサイ
ドを形成する金属の金属膜を半導体基板の平坦部
において密に被着させ、段差部において異常被着
させて後、この異常被着部の金属膜を除去し、熱
処理を行なうことにより、例えば拡散層やポリシ
リコン膜等の低抵抗化を図るべき各領域ごとに分
割された金属シリサイド膜をシリコンの露出した
半導体基板上に形成することができ、簡易な手段
により歩留りの向上と装置の高速化とを両立でき
る半導体装置の製造方法を提供することができ
る。
As described above, according to the present invention, after a metal film of a metal forming metal silicide is densely deposited on the flat portion of a semiconductor substrate and abnormally deposited on the step portion, the metal film in the abnormally deposited portion is deposited. By removing the metal silicide film and performing heat treatment, it is possible to form a metal silicide film divided into regions such as a diffusion layer or a polysilicon film where low resistance is to be achieved on the semiconductor substrate where silicon is exposed. It is possible to provide a method for manufacturing a semiconductor device that can both improve the yield and increase the speed of the device using simple means.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の半導体装置の製造方法を説明す
る断面図、第2図はこの発明の一実施例に係る半
導体装置の製造方法を説明する断面図、第3図は
この発明の他の実施例を説明する断面図である。 11……半導体基板、12F……フイールド酸
化膜、12G……ゲート酸化膜、13……拡散
層、14……ポリシリコン膜、15……チタン
膜、16……チタンシリサイド膜、A……異常成
長部、B……段差部。
FIG. 1 is a cross-sectional view explaining a conventional method for manufacturing a semiconductor device, FIG. 2 is a cross-sectional view explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention, and FIG. 3 is a cross-sectional view explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention. It is a sectional view explaining an example. 11... Semiconductor substrate, 12F... Field oxide film, 12G... Gate oxide film, 13... Diffusion layer, 14... Polysilicon film, 15... Titanium film, 16... Titanium silicide film, A... Abnormality Growth part, B... step part.

Claims (1)

【特許請求の範囲】 1 段差部を有する半導体基板表面に金属シリサ
イドを形成する金属を上記半導体基板に対して略
垂直に蒸着させ、上記半導体基板表面に上記金属
から成る金属膜を段差部において異常に、平坦部
において密に形成させる工程と、上記段差部に形
成された金属膜を除去する工程と、上記半導体基
板を熱処理し上記平坦部に形成された金属膜をシ
リサイド化させる工程とを具備することを特徴と
する半導体装置の製造方法。 2 上記金属シリサイドを形成する金属としてモ
リブデン、タングステン、タンタル、コバルト、
チタン、白金、アルミニウムのいずれかを用いる
ことを特徴とする特許請求の範囲第1項記載の製
造方法。
[Scope of Claims] 1. A metal forming metal silicide is deposited on the surface of a semiconductor substrate having a stepped portion substantially perpendicularly to the semiconductor substrate, and a metal film made of the metal is deposited on the surface of the semiconductor substrate at the stepped portion. The method includes a step of forming the metal film densely on the flat portion, a step of removing the metal film formed on the stepped portion, and a step of heat-treating the semiconductor substrate to silicide the metal film formed on the flat portion. A method for manufacturing a semiconductor device, characterized in that: 2 The metals forming the metal silicide include molybdenum, tungsten, tantalum, cobalt,
The manufacturing method according to claim 1, characterized in that titanium, platinum, or aluminum is used.
JP58020593A 1983-02-10 1983-02-10 Manufacture of semiconductor device Granted JPS59150421A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58020593A JPS59150421A (en) 1983-02-10 1983-02-10 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58020593A JPS59150421A (en) 1983-02-10 1983-02-10 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS59150421A JPS59150421A (en) 1984-08-28
JPH0150098B2 true JPH0150098B2 (en) 1989-10-27

Family

ID=12031549

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58020593A Granted JPS59150421A (en) 1983-02-10 1983-02-10 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS59150421A (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6068612A (en) * 1983-09-26 1985-04-19 Oki Electric Ind Co Ltd Manufacture of semiconductor element
JP2598780B2 (en) * 1986-04-07 1997-04-09 日本電装株式会社 Semiconductor device and manufacturing method thereof
KR930004295B1 (en) * 1988-12-24 1993-05-22 삼성전자 주식회사 Connecting method of low resistance
GB9105943D0 (en) * 1991-03-20 1991-05-08 Philips Nv A method of manufacturing a semiconductor device

Also Published As

Publication number Publication date
JPS59150421A (en) 1984-08-28

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