JPH0151012B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a circuit for driving a so-called latching relay that self-maintains the switching state of a relay switch even if the relay coil is once energized and then the energized state is released.

A certain prior art is a series circuit consisting of one relay coil and one switching NPN transistor of a so-called two-wound latching relay.
and a series circuit consisting of the other relay coil and the other switching NPN transistor,
They are connected in parallel between both output terminals of a power supply, and the base of the other switching transistor is connected to the connection point between the one relay coil and the one switching transistor. By applying a signal to the base of the one switching transistor to cut it off, the other switching transistor becomes conductive, thereby exciting the other relay coil. Further, by making the one switching transistor conductive, the one relay coil is excited. In such prior art, current is supplied to the base of the other switching transistor via the one relay coil. Therefore, the base current of the other transistor oscillates during a transient period, and therefore, the excitation current for the other relay coil, which is amplified by this oscillating base current, fluctuates greatly. Therefore, the switching mode of the latching relay does not respond accurately to the input signal, resulting in malfunction.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a drive circuit so that the switching aspects of a latching relay can accurately respond to input signals.

FIG. 1 is an electrical circuit diagram of an embodiment of the present invention. The so-called two-winding latching relay 1 is
It has relay coils 2 and 3 and relay switches 4 and 5. Once one relay coil 2 of the latching relay 1 is energized, the relay switch 4 is self-maintained in a conductive state even after the energization is released. Once the other relay coil 3 is energized, the relay switch 4 is self-maintained in the cut-off state even after the other relay coil 3 is de-energized. The relay switch 5 is for external connection, and is connected to the relay coils 2 and 3.
The switching state is changed and self-maintained by the excitation of . Transistors 6 and 7 as switching elements are connected in series to the relay coils 2 and 3, respectively. These two transistors 6 and 7 are respectively connected to a reset output and a set output Q of a flip-flop 8 made of a semiconductor element such as a transistor. An AND gate 9 and an OR gate 10 are connected to the set input of the flip-flop 8, and an AND gate 11 and an OR gate 12 are connected to the reset input. A connection point between the relay coil 2 and the transistor 6 is connected via a relay switch 4 to an inverting circuit 13 consisting of a transistor. The output from the inverting circuit 13 is sent to the inverting circuit 14.
is applied to one input of AND gate 9 via
It is applied to one input of AND gate 11.
The other inputs of the AND gates 9 and 11 are supplied with a pulse from a pulse generating circuit 17 via a line 16. Pulse generating circuit 17 is responsive to a signal on line 19 from Schmitt circuit 18. Line 20, commonly connected to relay coils 2, 3, is connected to line 22 via a power control switching element 21 responsive to an output via line 19 from Schmitt circuit 18.

FIG. 2 is a specific electrical circuit diagram of the pulse generation circuit 17, the power control switching element 21, and the Schmitt circuit 18. Schmitt circuit 18
In this case, the Zener diode 23 becomes conductive when the input signal inputted through the line 22 exceeds a predetermined discrimination level. This causes transistor 24 to shut off. With transistor 24 turned off, transistor 25 becomes conductive.

Therefore, the transistor 26 is cut off and the collector potential of the transistor 26 is increased.

Power control switching element 21 includes a transistor 90 and a resistor 27. transistor 90
A resistor 27 is connected between the collector and base of. The base current of the transistor 90 during cut-off is:
It flows from the collector side to line 20 via resistor 27, base and emitter.

The pulse generation circuit 17 is ANDed with the delay circuit 28
It consists of a gate 29. The delay circuit 28 includes three transistors 30, each acting as an inverting circuit.
Including 31 and 32. When the waveform shown in FIG. 3 is derived from the transistor 26 of the Schmitt circuit 18 to the line 19, the collector of the transistor 30 becomes low level after a delay time T1 as shown in FIG. 2. Therefore, transistor 31
As shown in FIG. 3, the collector of the transistor 31 becomes high level after a delay of time T2. Transistor 32 responds to the output from the collector of transistor 31 to
After the delay time T3 than the operation in step 1, Figure 3.4
A waveform shown as follows is derived to the collector of the transistor 32. AND gate 29 includes transistor 33 receiving the collector output of transistor 32, transistor 34 receiving the output from line 19, diodes 35, 36, and transistor 37. The output from the collector of transistor 37 is shown in FIG. 3 and has a pulse width of (T1+T2+T3). In this manner, when the input signal shown in FIG. 3 is applied to the Schmitt circuit 18, a pulse having a pulse width of time (T1+T2+T3) is derived on the line 16 of the pulse generating circuit 17.

Referring again to FIG. 1, the signal via switch 38 and diode 39 is provided on line 22. Also, each signal from lines 40 and 41 is
line 2 via diodes 42 and 43, respectively.
given to 2. The output from switch 40 is
Forces flip-flop 8 to reset via OR gate 12. Further, the signal from the switch 41 is passed through the OR gate 10 to the flip-flop 8.
force to set.

Referring to FIG. 4, assume that an input signal having a waveform shown in FIG. 4 is applied to the line 22 by pressing the switch 38 or the like. The Schmitt circuit 18 derives a waveform shown in FIG. 4 on a line 19, and when this line 19 is at a high level, the power control switching element 21 becomes conductive.
The pulse generating circuit 17 derives the waveform shown in FIG. 4 in response to the output from the Schmitt circuit 18.
Here, it is assumed that the flip-flop 8 is in the reset state and therefore the relay switch 4 is cut off. As a result, the output of the inverting circuit 13 becomes high level, the output of the inverting circuit 14 becomes low level, and the output of the inverting circuit 15 becomes high level. The output waveform from the inverting circuit 15 is shown in FIG. The pulse shown in FIG. 4 is derived from the AND gate 11, thereby resetting the flip-flop 8. The output waveform of the reset output is shown in FIG. In this way, the transistor 6 becomes conductive, the relay coil 2 is excited, the switching states of the relay switches 4 and 5 change, and the relay switch 4 becomes conductive. A switching mode of the relay switch 4 is shown in FIG. 4 and 7. When the relay switch 4 becomes conductive, the output of the inverting circuit 13 becomes a low level, and the output of the inverting circuit 14 becomes a high level. The output waveform from this inversion circuit 14 is shown in FIG.
is shown. By shutting off switch 38, power control switching element 21 is shut off, thereby de-energizing flip-flop 8 and relay coils 2,3. At this time, the switching mode of relay switches 4 and 5 is self-maintained.

When the switch 38 is turned on again, the output of the inverting circuit 14 is at a high level because the relay switch 4 is turned on as described above. Therefore, the output from the pulse generating circuit 17 is derived through the AND gate 9 as shown in FIG. 4, thereby setting the flip-flop 8. The set output Q of flip-flop 8 is shown in FIG. As a result, transistor 7 becomes conductive, relay coil 3 is energized, relay switch 4 is cut off, and the switching state of relay switch 5 is changed. After that, when the switch 38 is cut off, the excitation of the relay coil 3 is canceled, but after that, the relay switch 4,
The switching mode of No. 5 is self-maintained.

FIG. 5 is a specific electrical circuit diagram of the Schmitt circuit 18 and the power control switching element 21. The Schmitts circuit 18 includes a Zener diode 44 that breaks down when the input signal input from the line 22 becomes high level, a transistor 45 that becomes conductive due to the conduction of the Zener diode 44, and a transistor 45 that becomes conductive due to the conduction of the Zener diode 44. a Zener diode 47 that breaks down in response to the cutoff of the transistor 46 and the high level of the input signal on the line 22; a transistor 48 that becomes conductive when the Zener diode 47 is conductive; The transistor 49 is cut off by the conduction of the transistor 48. By cutting off the transistor, the transistor 90 of the power control switching element 21 becomes conductive.

FIG. 6 is another specific electrical circuit diagram of the pulse generation circuit 17. In the pulse generating circuit 17 shown in FIG. 6, the signal from the line 19 is applied to one input of the AND gate 50. The signal from line 19 is also inverted by inverting circuit 51 and applied to time constant circuit 93 consisting of resistor 52 and integrating capacitor 53. capacitor 53
The output from is applied to the other input of AND gate 50.

When a signal having the waveform shown in FIG. 71 is applied to line 19, the output from capacitor 53 is delayed by a predetermined time as shown in FIG. 72. Therefore, the pulse shown in FIG. 7 will be derived from the AND gate 50 on the line 16.

FIG. 8 is an electrical circuit diagram of another embodiment of the present invention. This embodiment is similar to the previous embodiment, but the notable feature is the latching relay 54.
is a so-called single winding type, and has a single relay coil 55, and when a current flows through the relay coil 55 in the direction of an arrow 56, a relay switch 57 becomes conductive and self-maintains. Further, when current flows through the relay coil 55 in the opposite direction of the arrow 56, the relay switch 57 shuts off and maintains itself. The latching relay 54 is a relay switch 5 for external connection.
Contains 8. One terminal of the relay coil 55 is connected to a mutual connection point of transistors 59 and 60 connected in series. The other terminal of the relay coil 55 is connected to a transistor 6 connected in series.
1,62 are connected to each other's connection points. Relay switch 57 is connected to line 20 via diode 63 and resistor 64. diode 6
The connection point between 3 and the resistor 64 is input to the AND gate 9 via the inverting circuit 65, and
AND gate 1 through two inverting circuits 66.
1 is input.

When the switch 38 is operated to apply an input signal to the line 22, the Schmitt circuit 18 outputs the input signal to the line 19.
A signal is derived from the switching element 2 for power control.
1 is made conductive, and the pulse generating circuit 17 is activated to output a pulse to the line 16. Here, it is assumed that flip-flop 8 is reset by operating switch 40 in advance, and its reset output turns on transistors 59 and 62, so that relay switch 57 of latching relay 54 is turned on. This causes diode 63
The connection point between and the resistor 64 is at a low level, so the output of the inverting circuit 65 is at a high level.
The output of the inverting circuit 66 becomes low level. Therefore, a pulse is applied from the AND gate 9 to the flip-flop 8 via the OR gate 10. The set output Q of flip-flop 8 is connected to transistor 60,
61 is made conductive. Therefore, current flows through the relay coil 55 in the opposite direction of the arrow 56 via the transistors 60 and 61. Therefore, relay switch 57
switches and shuts off. Even after the excitation current of the relay coil 55 is cut off by cutting off the switch 38, the switching mode of the relay switch 57 is self-maintained. Relay switch 58
Similarly, the switching mode is changed and self-maintained.

When the switch 38 is turned on again, the inverting circuit 65
A low-level signal from the gate will be given to the AND gate 9. Further, the inversion circuit 66 outputs a high level signal. This resets the flip-flop 8. Therefore, transistors 59 and 62 become conductive, and current flows through relay coil 55 in the direction of arrow 56. In this way, the relay switch 57 becomes conductive and self-maintained. The other relay switch 58 also changes its switching mode and becomes self-holding.

FIG. 9 is a partial electrical circuit diagram of an embodiment of the present invention. This switching circuit has the great advantage that it can be used commonly for two-turn and one-turn latching relays.
Transistor 7 is connected between line 20 and ground.
A series circuit of transistors 0 and 71 is connected, and a series circuit of transistors 72 and 73 is also connected. The set output Q of flip-flop 8 is applied to the base of transistor 74. When transistor 74 becomes conductive, transistor 75 becomes conductive.
conducts, thereby causing transistor 70 to conduct. The set output Q of flip-flop 8 is also applied to transistor 73, causing transistor 73 to conduct. The reset output of flip-flop 8 causes transistor 76 to conduct, which causes transistor 77 to conduct. As transistor 77 becomes conductive, transistor 72 becomes conductive. The reset output of flip-flop 8 also causes transistor 71 to conduct. A terminal 78 is provided at the connection point between the transistors 70 and 72. A terminal 79 is provided at the connection point between the transistors 72 and 73. The line 20 has a terminal 80,
81 is provided.

The latching relay is set to 2 as shown in Figure 1.
In the case of a wound type, one relay coil 2 is connected between terminals 78 and 80, and the other relay coil 3 is connected between terminals 79 and 81. When the set output Q of the flip-flop 8 becomes high level, the transistor 73 becomes conductive, thereby causing the relay coil 3 connected to the terminals 79 and 81 to
is excited. At this time, transistors 74, 7
Since terminals 5 and 70 are conductive and transistor 71 is cut off, relay coil 2 connected between terminals 78 and 80 is not excited.

When the reset output of flip-flop 8 becomes high level, transistor 71 becomes conductive, thereby energizing relay coil 2 connected between terminals 78 and 80. At this time, transistor 7
6, 77, and 72 are conductive, and the transistor 7
3 is cut off, so the relay coil 3 connected between the terminals 79 and 81 is not excited.

The latching relay is 1 as shown in Figure 8.
In the case of a wound type, the relay coil 55 is connected between terminals 78 and 79. When the set output Q of flip-flop 8 is at a high level, transistor 73 is conductive, and transistors 74, 75, and 70 are also conductive. In this way, an excitation current path is formed via the line 20, the transistor 70, the terminals 78 and 79, and the transistor 73. Therefore, an exciting current flows through the relay coil 55 in the opposite direction of the arrow 56. When the reset output of flip-flop 8 becomes high level, transistor 71 becomes conductive and transistor 7
6, 77, and 72 are electrically connected. As a result, an excitation current path is formed via the line 20, the transistor 72, the terminals 79 and 78, and the transistor 71. As a result, the relay coil 55 has an arrow mark 5.
Excitation current flows in direction 6.

The switching circuit shown in FIG. 9 can be commonly used for two-turn and one-turn latching relays, as described above. Therefore, it can be realized by an integrated circuit, and the terminals 78 to 81 may be provided on the semiconductor chip. This increases productivity and eases handling. Note that only one of the terminals 80 and 81 may be provided.

As described above, according to the present invention, the level of the input signal is discriminated by the level discrimination circuit, a pulse is generated thereby to change the stable state of the flip-flop, and the latching relay is activated according to the output of the flip-flop. Since the switching mode of the relay switch is changed, malfunctions do not occur due to the adverse effects of the inductance of the relay coil of the latching relay, and the switching mode can be changed in response to an input signal accurately.

[Brief explanation of drawings]

Fig. 1 is an electrical circuit diagram of an embodiment of the present invention;
The figure shows a specific electrical circuit diagram of the pulse generation circuit 17, the Schmitt circuit 18, and the power control switching element 21, and FIG. 3 shows the delay circuit 2 shown in FIG.
A waveform diagram for explaining the operation of 8, Figure 4 is the waveform diagram of 1
5 is another specific electrical circuit diagram of the Schmitt circuit 18, FIG. 6 is another specific electrical circuit diagram of the pulse generating circuit 17, and FIG. 7 is a waveform diagram for explaining the operation of the pulse generating circuit 17 shown in FIG. 6, FIG. 8 is an electric circuit diagram of another embodiment of the present invention, and FIG. 9 is related to the latching relays 1 and 54. FIG. 7 is another specific electrical circuit diagram of the switching circuit. 1...Two-winding latching relay, 2, 3, 5
5...Relay coil, 6,7,59-62,70
~77...transistor, 8...flip-flop, 9,11...AND gate, 10,12...
OR gate, 13-15, 65, 66...inversion circuit, 17...pulse generation circuit, 18...Schmitt circuit, 21...power control switching element,
54... Single winding latching relay.

Claims (1)

[Claims] 1. A switching circuit is connected in connection with the relay coil of the latching relay, and the switching circuit changes the switching mode of the relay switch of the latching relay in response to each of the two stable states of the flip-flop. a level discrimination circuit that excites the relay coil and receives an input signal; a power control switching element that supplies power to the switching circuit during a period in which the input signal exceeds a discrimination level of the level discrimination circuit; a circuit that responds to the output of the relay switch and generates a pulse immediately after the input signal exceeds the discrimination level; 1. A latching relay drive circuit comprising: a logic circuit for changing the stable state of a flip-flop so that the flip-flop is in a stable state;