JPH0151066B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit device including ECL (emitter coupled logic) or CML (current mode logic).

Traditionally, ECL (or
CML) circuits are known.

In this circuit, a differential type transistor
Q ₁ to Q ₃ constitute a logic block. Transistor receiving logic threshold voltage V _BB
Transistors Q ₂ and Q ₃ that operate differentially with respect to Q ₁
Input logic signals A and B are applied to the bases of .

The collector of the transistor Q ₁ and the collectors of the shared transistors Q ₂ and Q ₃ are
Load resistors R _L1 and R _L2 are provided to form an output X. The common emitters of the differential transistors Q ₁ to Q ₃ are provided with a constant current source composed of a transistor Q ₄ that forms a constant current I _CS and an emitter resistor _RE . This constant current I _CS
To form the base of transistor Q ₄ ,
Reference voltage V _CS is applied.

In such an ECL circuit, the above constant current I _CS
plays an important role in defining the signal amplitude of the output X.

When the above ECL circuit is configured with a semiconductor integrated circuit, the voltage supply line that supplies the power supply voltage -V _EE is
Since it has distributed resistance, due to the voltage drop,
A voltage difference occurs in the power supply voltage -V _EE supplied to each ECL circuit in accordance with the distributed resistance of the voltage supply line.

If there is a difference in the power supply voltage -V _EE of each ECL circuit in this way, a difference will occur in the constant current _ICS , so
The signal amplitude differs between ECL circuits.

Therefore, in the conventional ECL circuit, by providing a large number of reference voltage generation circuits that form the reference voltage _V This was to form a reference voltage V _CS corresponding to −V _EE . As a result, for each logic gate block, its power supply voltage -V _EE and reference voltage V _CS
Since the voltage difference between
The signal amplitudes of all logic gates in the semiconductor integrated circuit device can be made constant.

However, in this case, a large number of reference voltage generation circuits are required within the semiconductor integrated circuit device, which significantly reduces the actual degree of integration of the logic gates and also increases the power consumption per logic gate. be.

An object of the present invention is to provide a semiconductor integrated circuit device with improved degree of integration and power consumption.

Other objects of the invention will become apparent from the following description and drawings.

Hereinafter, this invention will be explained in detail together with examples.

FIG. 2 shows a schematic layout diagram of a semiconductor integrated circuit showing an embodiment of the present invention.

Although not specifically controlled, in this example the ECL
A digital control circuit made up of circuits constitutes a so-called custom logic integrated circuit in which connections between logic gates are made by a master slice method.

A pair of wiring lines L ₁₁ and L ₁₁ ' arranged vertically along the left and right sides of the semiconductor chip IC are connected to external terminals and receive a power supply voltage -V _EE . Note that, in order to prevent a voltage difference between the two, the pair of wires L ₁₁ and L ₁₁ ′ are short-circuited by a pair of wires L ₁₂ and L ₁₂ ′ along the upper and lower sides. This wiring L ₁₁ ,
L ₁₁ ′ is, for example, a second layer wiring, and is separated from circuit lines forming reference voltage generation circuits V _CS -G ₁ , V _CS -G _2, etc., which will be described later, via an insulating film.

Ladder-shaped wires L ₂₁ to L _2o are formed to connect the pair of wires L ₁₁ and L ₁₁ ′ in the horizontal direction.

A power supply voltage -V _EE is supplied from these wirings L ₂₁ to L _2o to a logic gate group ECL, buffer amplifier groups BA ₁ and BA _2, etc., which will be described later.

In this embodiment, each logic gate of the logic gate group ECL uses an ECL circuit as shown in FIG.

In addition, in this embodiment, in order to improve the practical integration density and power consumption of logic gates, a small number of reference voltage generation circuits V _{CS −G 1} , V It is installed around _{the CS} - _G2 semiconductor chip IC.

The reference voltage V _CS applied to the base of the constant current source transistor Q ₄ of each logic gate is formed as follows.

First, among the many logic gates, the above wiring L ₁₁ ,
Focusing on the fact that there is a difference between the voltage at the electrically far end and the voltage at the near end from L ₁₁ ' due to the impedance of the wiring, two representative voltages are selected. In this embodiment, as the voltage at the far end, a voltage -V _EE1 is extracted from the middle point of the central wiring L _2n among the wirings L ₂₁ to L _2o , and this voltage -V _EE1 is received as a reference voltage. The first forming the voltage V _CS1
Reference voltage generating circuits V _CS -G ₁ are provided at the upper and lower center portions of the semiconductor chip IC, respectively.

In addition, as the voltage at the near end, the above wiring
A second voltage source that extracts the voltage -V _EE2 from the left and right ends of L _n and receives this voltage -V _EE2 to form the reference voltage V _CS2 .
Reference voltage generating circuits V _{CS -G2} are provided at the upper and lower ends of the semiconductor chip IC, respectively.

In the center of the semiconductor chip IC,
A buffer amplifier group _BA1 consisting of _a plurality _of buffer amplifiers _BA11 , _{BA12 ,} . Each buffer amplifier BA ₁₁ , BA ₁₂ , . . . , BA _1o in this buffer amplifier group BA ₁ is for receiving the reference voltage V _CS1 and amplifying its current.

On the other hand, buffer amplifier groups _BA2 similar to those described above are arranged in the vertical direction at the ends of the semiconductor chip corresponding to the vicinity of the left and right ends of the wiring _Ln . Each buffer amplifier BA ₂₁ in these buffer amplifier group BA ₂ ,
BA ₂₂ , . . . , BA _2o (not shown) are for receiving the reference voltage V _CS2 and amplifying its current.

Among the buffer amplifiers in the buffer amplifier groups BA ₁ and BA ₂ , wiring L ₃₁ to L _3o are connected between the output terminals of the buffer amplifiers located at corresponding positions.
(L ₃₁ ′ to L _3o ′).

The logic gate group ECL arranged between the buffer amplifier groups BA and BA ₂ is connected to the power supply voltage −V _EE and the reference voltage V from the wirings L ₂₁ , L ₃₁ , L ₃₁ ′, etc. at the shortest distance, respectively. It is subject to _CS .

Note that the ground potential line and external input/output terminals for the logic gates are omitted in the figure because they are not directly related to the present invention.

FIG. 3 shows the reference voltage generation circuit V _CS −G ₁ ,
A circuit diagram of one embodiment of V _CS -G ₂ is shown.

In the transistors Q ₁ and Q ₂ that have a common base, the emitter area of transistor Q ₂ is formed to be large, so the base-emitter voltage V _BE of transistor Q ₂ is smaller than that of transistor Q ₁ . . Therefore, a constant current flows through the emitter resistor _R1 of the transistor _Q2 in accordance with the constant voltage difference between the base and the emitter.

This constant current flows through transistor Q ₂ to its collector resistor R ₂ . Since the collector voltage of the transistor _Q2 is made constant by the voltage between the base and emitter of the transistor _Q3 , the reference voltage V _CS is formed by the resistor _R2 . This reference voltage V _CS is raised in level through the emitter and base of the transistor _Q4 , and lowered in level through the base and emitter of _the transistor _Q5 whose base is shared with the transistor _Q4 . The emitter voltages of the transistors _{5 and 5} become approximately equal, forming low-impedance output reference voltages V _CS1 and V _CS2 .

Note that a resistor _R6 is provided between the emitter of the transistor _Q5 and the collector of the diode-shaped transistor _Q1 . Further, a resistor _R5 is provided at the collector of the transistor _Q5 . On the other hand, the collector of transistor _Q3 has
Resistors R ₃ and R ₄ are provided in series, and these resistors R ₃ and
The connection point of _R4 is connected to the bases of the transistors _Q4 and _Q5 .

The above reference voltage V _CS is the voltage between the base and emitter of transistor Q ₃ plus the voltage drop of resistor R ₂ , so its power supply voltage -V _EE2 , -V _EE1
The voltage will be according to .

FIG. 4 shows the buffer amplifier groups BA ₁ and BA ₂ .
A circuit diagram of one embodiment of each buffer amplifier in the circuit is shown.

In this embodiment, for example, a pair of buffer amplifiers BA _1n and BA _2n corresponding to the power supply voltage line L _2n is shown.

The buffer amplifier BA _1n is composed of a differential transistor circuit receiving the reference voltage V _CS1 and an emitter follower output circuit, and since it is 100% negative fed back, it functions as a voltage follower circuit. Therefore, its output voltage is equal to the reference voltage above.
V becomes equal to _CS1 . In addition, the buffer amplifier mentioned above
In order to operate BA _1n as a current pushing circuit, no load resistance is provided between the emitter of the emitter follower output transistor Q ₈ and the power supply voltage -V _EE1 .

On the other hand, buffer amplifier BA _2n uses the above reference voltage.
It consists of a differential transistor circuit receiving V _CS2 and an emitter follower output circuit, and also has 100% negative feedback, so it acts as a voltage follower circuit and makes its output voltage equal to the reference voltage V _CS2 . Since this buffer amplifier BA _2n operates as a current sink circuit, a load resistor R ₁₃ is provided between the emitter of the emitter follower output transistor Q ₁₁ and the power supply voltage -V _EE2 .

The output terminals of the buffer amplifiers BA _1n and BA _2n are connected by wires L _3n and L _3n ' having a predetermined distributed resistance R.

As shown in the figure, the above power supply voltage −V _EE1 , −
A voltage difference occurs in V _EE2 due to its wiring resistance.

Therefore, the voltage at each point of the power supply voltage line _L2 also changes approximately in accordance with the voltage difference and the wiring resistance ratio at each point.

On the other hand, the reference voltages V _CS1 and V _CS2 formed according to the power supply voltages -V _EE1 and -V _EE2 also have a voltage difference commensurate with the above voltage difference. Therefore,
The voltage at each point of the wires L _3n and L _3n ′ that connect the two also changes in the same way as the voltage at each point of the power supply voltage line L _2n .

As a result, a constant constant current ICS can be passed through each logic gate that receives the power supply voltage -V _EE and _the reference voltage V _CS from corresponding points of the wirings L _2n , L _3n , and L _3n ′. Therefore, the signal amplitude can also be kept constant.

In this example, 6
Since only one reference voltage generating circuit is provided, the degree of integration can be greatly improved.

For example, when configuring an ECL circuit consisting of 1500 gates, if one reference voltage generation circuit was provided for every few gates as in the past, 150 to 300 reference voltage generation circuits would be required. It is. Since more logic gates can be formed by reducing the number of reference voltage generating circuits, the degree of integration can be greatly improved.

Furthermore, since power consumption can be reduced in the reference voltage generation circuit, power consumption per logic gate can also be significantly reduced.

Furthermore, when lowering the power supply voltage -V _EE to about -3 volts to reduce power consumption,
It is necessary to reduce the resistance value of the logic gate resistor R _E. When the resistance value of the resistor _RE is reduced in this way, the rate of change (sensitivity) of the constant current _ICS with respect to a change in the power supply voltage -V _EE increases. However, by applying this embodiment, the reference voltage V _CS also changes as the power supply voltage -V _EE changes, so the constant current
_ICS can be kept constant.

Therefore, even when the absolute value of the power supply voltage -V _EE is lowered, the power consumption can be effectively reduced.

Furthermore, as mentioned above, since the signal amplitude of each logic gate is compensated to a constant value, the margin of the signal amplitude can be reduced, so the signal amplitude can be lowered and high-speed operation can be achieved. .

The invention is not limited to the above embodiments.

The ECL or CML circuit is the circuit shown in Figure 1.
An emitter follower output transistor may be provided. In this case, the load of the emitter follower output transistor may be connected to a low power supply voltage of, for example, -2 volts.

In addition, the wiring layout for supplying the power supply voltage -V _EE can be modified in various ways, and the electrically far end voltage extraction point and near-end voltage extraction point are selected according to this wiring layout. It will be done. and,
Wiring between the buffer amplifiers is also provided according to the wiring layout.

Furthermore, in the embodiment shown in FIG. 2, the reference voltage generating circuit is configured as a set of two in order to reduce variations in the output reference voltage. Therefore, in principle, under the above-mentioned wiring layout, the upper or lower three
Only one reference voltage generation circuit is sufficient.

Furthermore, the specific configurations of the reference voltage generation circuit and buffer amplifier can take various embodiments.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing an example of ECL (or CML), Fig. 2 is a schematic layout diagram showing an embodiment of the present invention, and Fig. 3 is an embodiment of the reference voltage generation circuit. Circuit diagram FIG. 4 is a circuit diagram showing one embodiment of the buffer amplifier.

Claims (1)

[Scope of Claims] 1. A large number of logic gate circuits each including a constant current source each composed of a transistor and an emitter resistor, a voltage supply line for supplying a power supply voltage to each of the logic gate circuits, and a voltage supply line for supplying a power supply voltage to each of the logic gate circuits. a first circuit that supplies a reference voltage to a first connection point located on the far end side with respect to a voltage at a point electrically far from an external power supply terminal of a power supply voltage line that supplies voltage to the above-mentioned resistor; , a second circuit that provides a reference voltage for a voltage at a point electrically proximate to the external power supply terminal of the power supply voltage line to a second connection point located on the proximal end side; and the first connection. resistor means provided between the point and the second contact point to divide the voltage between the first connection point and the second connection point, and a resistor means for dividing the voltage between the first connection point and the second connection point; A semiconductor integrated circuit device, characterized in that the voltage is applied to the base of a transistor constituting a constant current source in a logic gate circuit. 2. The first circuit includes a first reference voltage generation circuit that receives a voltage from the far end of the power supply voltage line to form a reference voltage, and a reference voltage generation circuit that receives a reference voltage from the first reference voltage generation circuit. a first buffer amplifier that provides an output to the first connection point, and the second circuit includes a second reference voltage generation circuit that receives a voltage from the near end of the power supply voltage line and forms a reference voltage. , a second circuit that receives the reference voltage from the second reference voltage generation circuit and provides an output to the second connection point.
2. A semiconductor integrated circuit device according to claim 1, comprising a buffer amplifier. 3. The semiconductor integrated circuit device according to claim 1 or 2, wherein the resistance means comprises a wiring having a distributed resistance value. 4. Claims 2 or 3, characterized in that the output circuit of the first buffer amplifier is constituted by an emitter follower circuit whose load is the wiring and the load resistance of the second buffer amplifier. The semiconductor integrated circuit device described above. 5 The power supply voltage line is provided in parallel to both opposing peripheral parts of the semiconductor chip, and includes a first wiring pair of relatively low impedance and a relatively high impedance wiring line that connects the first wiring pair in a ladder shape. Claim 1, characterized in that the first wiring pair is connected to an external power supply terminal, and the second wiring group supplies voltage to each logic gate. The semiconductor integrated circuit device according to any one of items 1 to 4.