JP3078699B2 - Active terminator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active terminator connected to the end of a bus and enabling reliable operation of the bus.

[0002]

2. Description of the Related Art Conventionally, an active terminator is mounted at the end of a bus in order to achieve a reliable operation of a bus for transmitting a signal. As shown in FIG. 4, the active terminator connects a plurality of buses SUCSI1 to SUCSIIn to a regulator 10 that outputs a predetermined voltage via predetermined impedance resistors r1 to rn. Note that the capacitor 12 is for stabilizing the voltage.

[0003] Therefore, each bus receives power from the active terminator, and the bus is reliably pulled up.
Also, the change to a high level is fast enough. Also, the change of the bus to a low level is performed at a high speed because it is usually performed by turning the transistor on to drop the bus to the ground potential. Therefore, by providing an active terminator, high-speed operation of the bus becomes possible.

[0004]

In such an active terminator, if the capacity of the regulator 10 is made sufficiently large, each bus can receive sufficient power. However, if the regulator 10 is too large, its internal circuit must have a large capacity.
When an active terminator is integrated into an IC, its area becomes large. In addition, when the power supply amount is increased, power consumption during operation increases, and various problems occur.

On the other hand, if the capacity of the regulator 10 is made small, the high level and the low level of the bus are affected by changes in the levels of other buses. For example, if many other buses change to a high level at once, the effect is that the level of the remaining high-level buses drops. When the active terminator is formed of a semiconductor integrated circuit, the internal wiring of the integrated circuit is formed of aluminum wiring (usually formed by vapor deposition). Since the aluminum wiring has a relatively high electric resistance, if the capacity of the regulator 10 is small, there is a problem that the voltage drop cannot be ignored and the operation of the bus becomes slow.

The present invention has been made to solve the above problems, and has as its object to provide an active terminator that enables high-speed operation of a bus.

[0007]

SUMMARY OF THE INVENTION The present invention is an active terminator attached to the end of a bus and supplying a predetermined power to a plurality of buses, comprising a regulator for generating a predetermined voltage, and an output from the regulator. Distributing means for distributing to a plurality of lines, and buffer amplifiers provided on each of the lines after distribution for holding the voltage of each line, respectively, wherein an output of the buffer amplifier is connected to each bus. .

[0008]

As described above, the buffers connected to the respective buses are provided with the buffer amplifiers. Therefore, even if the capacity of the regulator itself is small, sufficient power can be supplied to each bus by the buffer amplifier. Further, since the buffer amplifiers are arranged corresponding to the respective buses, the respective buses can be effectively isolated.
Thus, high-speed operation and reliable operation of the bus can be achieved.

[0009]

Embodiments of the present invention will be described below with reference to the drawings.

[Overall Configuration] FIG. 1 is a block diagram showing the overall configuration of the embodiment, which comprises a regulator 20, a capacitor 22, buffer amplifiers BUF1 to BUFn, and resistors R1 to Rn. The regulator 20 in this embodiment has a relatively small current capacity. This output is output to each bus SUCSI1 to SUCSI.
Input to buffer amplifiers BUF1 to BUFn corresponding to In. The buffer amplifiers BUF1 to BUFn are amplifiers that output the input voltage as it is. The capacitor 22 is for holding a voltage, as in the conventional example.

According to such a configuration, each bus SUCS
I1 to SUCSIn must be buffer amplifiers BUF1 to BUF1.
It is connected to the regulator 20 via BUFn. Therefore, each of the buses SUCSI1 to SUCSIIn can be supplied with sufficient power by the buffer amplifiers BUF1 to BUFn. Also, buffer amplifiers BUF1 to BUF1
The buses SUCSI1 to SUCSIn are isolated from each other by the UFn. Therefore, each bus SUCS
I1 to SUCSI are other buses SUCSI1 to SUCSI
It is not affected by the change in the level of In.

The buffer amplifiers BUF1 to BUFn
Is configured using transistors and the like, and can be easily incorporated into a semiconductor integrated circuit. Further, by turning off the operation of the buffer amplifiers BUF1 to BUFn, it is easy to disconnect the active terminator from the bus, and power can be supplied only to the necessary bus.

[Buffer Amplifier] FIG. 2 shows a configuration example of the buffer amplifiers BUF1 to BUFn. A PNP transistor Q1 whose collector and base are short-circuited is connected to the upper side of a constant current source CS for flowing a current toward the ground, and the emitter of the transistor Q1 is connected to a power supply VCC. Therefore, a current determined by the constant current source CS flows through the transistor Q1. The base of the transistor Q1 has a PNP transistor Q2,
The bases of Q8 and Q11 are connected, and the emitters of these transistors Q2, Q8 and Q11 are connected to power supply VCC. Therefore, the transistors Q2, Q8, Q11
Constitutes a current mirror with the transistor Q1,
These transistors Q2, Q8 and Q11 flow the same current as the transistor Q1, that is, the same current as the current flowing to the constant current source CS.

Below the transistor Q2, two PNs
The emitters of P transistors Q3 and Q4 are connected, and the collectors of these transistors Q3 and Q4 are respectively NPN.
It is connected to ground via transistors Q6 and Q7. The bases of the transistors Q6 and Q7 are connected, and the collector and the base of the transistor Q6 are short-circuited. For this reason, the transistors Q6 and Q7 form a current mirror, and both pass the same current. Therefore, Q3 and Q4 perform a differential operation. Therefore, the transistors Q2, Q3, Q4, Q6, and Q7 form a differential amplifier having the bail of the transistors Q3 and Q4 as two input terminals.

The base of the transistor Q15 is connected to the collector of the transistor Q11 through which a constant current flows. The collector of the transistor Q15 is connected to the power supply VCC, and the emitter is connected to the output terminal OUT. Therefore, the transistor Q15 operates as an output transistor on the source side of the buffer amplifier.

On the other hand, the emitter of a PNP transistor Q9 is connected to the lower side of the transistor Q8 for flowing a constant current,
The collector of this transistor Q9 is connected to ground,
The base is connected to a connection point between the collectors of the transistors Q4 and Q7. Therefore, the transistor Q9 operates according to the operation of the transistor Q4.

The base of an NPN transistor Q10 is connected to the connection point between the collectors of the transistors Q8 and Q9, and the collector of the transistor Q10 is connected to the power supply V.
The emitter is connected to ground via a resistor Ra. Therefore, the transistor Q10 operates according to the current amount of the transistor Q9, that is, the input voltage applied to the base of the transistor Q4. And
The emitter of this transistor Q10 is the transistor Q1
4 are connected to the base. Therefore, transistor Q
The base potential of 14 is determined by the amount of current of transistor Q10. The collector of the transistor Q14 is connected to the output terminal OUT via an NPN transistor Q16 whose base collector is short-circuited. Therefore, this transistor Q14 operates as a sink-side output transistor.

Further, the collector of the transistor Q14 is connected to the collector of the transistor Q11 (base of the transistor Q15) via NPN transistors Q13 and Q12 whose two base collectors are short-circuited. Therefore, the potential of the collector of the transistor Q14 becomes
The voltage becomes lower than the base of the transistor Q15 by 2VBE (the voltage between the base and the emitter of the transistor), and the potential of the output terminal OUT becomes higher by 1VBE than this.

The output terminal OUT is connected to the transistor Q3
Connected to the base. Therefore, when the input signal IN changes, this change is caused by the transistors Q9 and Q10.
To the transistor Q14 via the output terminal O
The signal is output to the UT, but since this output is fed back to the transistor Q3, the output terminal OUT
Follows the voltage of the input IN.

In this circuit, the signal applied to the input IN is a constant voltage from the regulator 20, and the output terminal OUT is also a constant voltage. When the potential of the output terminal OUT tries to change, this voltage is fed back to the base of the transistor Q3, and the transistor Q3
The amount of current 14 changes, and the output terminal OUT is held at a constant voltage.

For example, when the voltage at the output terminal OUT rises, the current amount of the transistor Q3 decreases, the current amount of the transistor Q4 decreases, the current of the transistor Q9 increases, and the current of the transistor Q10 decreases. , The current of the transistor Q14 decreases, the potential of the output OUT decreases, and is maintained at a constant voltage.

The output terminal OUT is connected to a bus SUCSI via a predetermined impedance resistor R.
A predetermined voltage is supplied to UCSI.

The capacitor C1 is for stabilizing the operation, and the resistor Rb and the capacitor C2 are for suppressing the influence of the fluctuation of the power supply VCC.

[Operation when Buffer Amplifier is Off] In this buffer amplifier, when it is desired to disconnect the regulator and the bus SUCSI, the current of the constant current source CS is set to 0. Since the current of CS of the constant current source becomes 0, the current of transistor Q2 also becomes 0. Therefore, transistors Q3 and Q4
Also goes off. Further, since the transistors Q3 and Q4 are turned off, the currents of the transistors Q9 and Q10 also become 0, and the transistor Q14 is turned off. Since the current of the transistor Q11 becomes 0, the transistor Q15 is turned off. Thus, the transistors Q3, Q15,
Q14 is turned off, and the output terminal OUT floats. Therefore, even if this active terminator is connected, there is no adverse effect on the level conversion of the bus SUCSI. Therefore, by keeping the active terminator connected to all the buses and turning off the buffer amplifiers for the buses to which the active terminator does not need to be connected, the active terminator for that bus can be disconnected.

Further, consider the case where the power supply VCC of the active terminator is turned off, and the power supply drops to the ground potential. First, the PNP transistor is, as shown in FIG.
An N-type well is formed in a P-type substrate (SUB), a P-type collector region and an emitter region are formed therein, and an N-type region between the two is a base. Therefore, when the emitter and the base fall to the ground potential, a current flows from the collector toward the base.

In this circuit, the transistor Q11
Is a PNP transistor, the collector of which falls to ground, so that the base of the output transistor Q15 falls to ground and this output transistor Q15 is turned off. Further, since the power supply VCC drops to the ground potential, power supply to the resistor Ra via the transistor Q10 is stopped, and the transistor Q10 is turned off.
The base of the transistor 14 drops to the ground potential, and the transistor Q
14 turns off. As described above, in the present circuit, both the output transistors Q14 and Q15 are constituted by NPN transistors, and when the power supply VCC drops to the ground potential, the base potential of these becomes the ground potential. Therefore, the output transistor can be kept off by turning off the output transistor. Further, a pair of transistors Q3 and Q4 forming the differential circuit are formed by PNP transistors.
Further, since the emitters of the transistors Q3 and Q4 also fall to the ground potential, the transistors Q3 and Q4 do not turn on. Therefore, the output terminal OUT can be maintained in the floating state.

Accordingly, the output end of this buffer amplifier is in a floating state when the power supply drops to the ground potential. Thus, even if the power supply to the buffer amplifier is turned off, there is no adverse effect on the operation of the bus connected to the output terminal OUT.

As the constant current source CS, conventionally known various circuits can be adopted. In these circuits, it is easy to set the current to 0 by turning off a predetermined transistor. Can be achieved.

[0029]

As described above, according to the active terminator of the present invention, each line connected to each bus is provided with a buffer amplifier. Therefore, by reducing the capacity of the regulator, sufficient power can be supplied to each bus, and the buses can be effectively isolated. Thus, high-speed operation and reliable operation of the bus can be achieved.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of an embodiment.

FIG. 2 is a circuit diagram showing a configuration of a buffer amplifier.

FIG. 3 is a diagram showing a configuration of a PNP transistor.

FIG. 4 is a diagram showing a configuration of a conventional active terminator.

[Explanation of symbols]

 20 Regulator BUF1 to BUFn Buffer amplifier R1 to Rn Resistance

Claims (1)

(57) [Claims] 1. An active terminator attached to an end of a bus and supplying predetermined power to a plurality of buses, a regulator for generating a predetermined voltage, and distribution means for distributing an output from the regulator to a plurality of lines. An active terminator, comprising: a buffer amplifier provided on each of the lines after distribution, for holding a voltage of each line; and an output of the buffer amplifier connected to each bus.