JPH0154797B2 - - Google Patents

Description

Detailed Description of the Invention The present invention provides a complementary MOS field effect transistor (hereinafter referred to as CMOS) static RAM.
This relates to the improvement of semiconductor sense amplifiers such as (Random Access Memory).

As shown in Figure 1, the semiconductor sense amplifier of current CMOS static RAM is a P-channel MOS field effect transistor (hereinafter referred to as PMOS).
) F ₁ , F ₂ and N-channel MRS field effect transistors (hereinafter referred to as N-MOS) F ₃ , F ₄ are connected in a differential amplification format, and the sources of N-MOS F ₃ and F ₄ are connected to a constant current. This is connected to the drain of the source N/MOS/ _F5 .

The operation of this circuit will be explained.

The PMOS turns off when the input signal is at a high level (hereinafter referred to as H) and turns on when the input signal is at a low level (hereinafter referred to as L). NMOS turns on when it is H, and when it is L
Turns off when .

In Figure 1, an H signal is now applied to the D terminal,
At the same time as inputting the L signal to the D terminal,
When inputting an H signal to gate G of MOS _F5 ,
N・MOS・F ₃ and N・MOS・F ₅ are turned on and the power is turned on.
V _DD is P・MOS・F ₁・N・MOS・F ₃ , N・
Flow current through MOS・_F5 . At this time, P.
Since the drains of MOS・F ₁ and N・MOS・F ₃ are set to L, P・MOS・F ₂ is turned on, but N・MOS・F 3 is turned on.
Since MOS.F ₄ is off, the drains of P.MOS.F ₂ and N.MOS.F ₄ are applied with the power supply V _DD and become H, and the output terminal out outputs an H signal.
Also, if you input an L signal to the D terminal and an H signal to the terminal, and at the same time input an H signal to the gate G of N.MOS.F ₅ , N.MOS.F ₄ and N.MOS.
When _F5 is turned on, a transient current flows through _{N.MOS.F.sub.4} and _{N.MOS.F.sub.5} , and the output terminal out outputs an L signal.

In such _a semiconductor sense amplifier, W/L (W: channel width,
Since the channel length (L: channel length) is increased and used for high-speed applications, there is a drawback that power consumption increases.

The present invention was made to eliminate the above-mentioned drawbacks, and its features are that P-MOS F ₁ , F ₂ and N-MOS F ₃ , F ₄ are connected in a C-MOS inverter format, The reason is that the gate of the constant current source NMOS F ₅ is connected to the drains of PMOS F ₁ and NMOS F ₃ .

The present invention will be described in detail below along with examples. FIG. 2 is a diagram showing the configuration of an embodiment of the present invention, and parts having the same functions as those in FIG. 1 are given the same symbols.

In this embodiment, as shown in FIG.
MOS・F ₁ , F ₂ and N・MOS・F ₃ , F ₄ as C・MOS
Connected to inverter type, constant current source N/
Connect the gate of MOS・F ₅ to P・MOS・F ₁ and N・
This is a semiconductor sense amplifier connected to the drain of MOS _F3 . In the figure, V _DD is a power supply, D is an input terminal for opposing signals, and out is an output terminal.

Next, the operation of this embodiment will be explained.

The P-MOS turns off when the input signal is H and turns on when the input signal is L. The N-MOS turns on when the input signal is H and turns off when the input signal is L.

In Fig. 2, we are now applying an H signal to the D terminal,
When inputting the L signal to the D terminal, P.
MOS・F ₁ and N・MOS・F ₄ D are off, P・
MOS・F ₂ and N・MOS・F ₃ are turned on, but P・
Since MOS・F ₁ is off, the power supply V _DD is P・
No voltage is applied to the drains of MOS・F ₁ and N・MOS・F ₃ , the drains remain at L, and the N・MOS・F
_F5 doesn't turn on. As a result, the drains of P・MOS・F ₂ and N・MOS・F ₄ become H, and the output terminal
out outputs an H signal. Next, when inputting an L signal to the D terminal and an H signal to the terminal, P.
MOS・F ₁ and N・MOS・F ₄ are turned on, and P・
MOS・F ₂ and N・MOS・F ₃ are turned off. As a result, the power supply V _DD is applied to the drains of P・MOS・F ₁ A and N・MOS・F ₃ and become H, so the drains of P・MOS・F 1 A and N・MOS・F 3 become H.
MOS・_F5 turns on and current flows. At this time, the drains of P・MOS・F ₂ and N・MOS・F ₄ are P・MOS・F 2 and N・MOS・F 4.
Since MOS·F ₂ is turned on and power supply V _DD is not applied, it becomes L, and the output terminal out outputs an L signal.

As explained above, according to the present invention, P.
Since the current flows only when the MOS・F ₁ and N・MOS・F ₃ drains become H, the current consumption can be reduced. This is especially effective when outputting RAM data in parallel, as multiple semiconductor sense amplifiers are provided in parallel.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a circuit configuration of a semiconductor sense amplifier connected in a differential amplification format, and FIG. 2 is a diagram showing a circuit configuration of an embodiment of the present invention. F ₁ , ₂ ... P・MOS, F ₃ , F ₄ ... N・MOS,
V _DD ...Power supply, _F5 ...N-MOS for constant current source, D,
D...Reciprocal signal input terminal, out...Output terminal.

Claims (1)

[Claims] 1. A first gate to which an input signal is supplied between gates;
a 2MOS field effect transistor, an output point to which an output from the drain of the first MOS field effect transistor is given, a load means provided on the drain side of the first and second MOS field effect transistors, and a load means provided on the drain side of the first and second MOS field effect transistors; and a third MOS field effect transistor provided on the source side of the field effect transistor, and the conduction state of the third MOS field effect transistor is controlled by the drain output of the second MOS field effect transistor. A semiconductor sense amplifier featuring: 2. The first to third MOS field effect transistors are first channel type MOS field effect transistors, and the load means includes a gate,
A patent claim comprising a second channel type MOS field effect transistor whose drains are coupled together, and a second channel type MOS field effect transistor whose gate and drain are coupled to the gate and drain of the second MOS field effect transistor. The semiconductor sense amplifier according to item 1.