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JPH0154874B2 - - Google Patents
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JPH0154874B2 - - Google Patents

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Publication number
JPH0154874B2
JPH0154874B2 JP54169268A JP16926879A JPH0154874B2 JP H0154874 B2 JPH0154874 B2 JP H0154874B2 JP 54169268 A JP54169268 A JP 54169268A JP 16926879 A JP16926879 A JP 16926879A JP H0154874 B2 JPH0154874 B2 JP H0154874B2
Authority
JP
Japan
Prior art keywords
film
thickness
plating
conductor
thin film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP54169268A
Other languages
Japanese (ja)
Other versions
JPS5694684A (en
Inventor
Kaoru Oomura
Takeo Kimura
Tetsuhiro Kususe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Asahi Chemical Industry Co Ltd
Original Assignee
Asahi Chemical Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Asahi Chemical Industry Co Ltd filed Critical Asahi Chemical Industry Co Ltd
Priority to JP16926879A priority Critical patent/JPS5694684A/en
Priority to US06/219,155 priority patent/US4392013A/en
Priority to NLAANVRAGE8006987,A priority patent/NL183380C/en
Priority to GB8041120A priority patent/GB2066583B/en
Priority to DE3048740A priority patent/DE3048740C2/en
Publication of JPS5694684A publication Critical patent/JPS5694684A/en
Publication of JPH0154874B2 publication Critical patent/JPH0154874B2/ja
Granted legal-status Critical Current

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  • Electroplating Methods And Accessories (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Description

【発明の詳細な説明】[Detailed description of the invention]

本発明は高密度、高信頼性の厚膜フアインパタ
ーンの製法に関するものである。 厚膜フアインパターンは、電流値が必要とされ
る小型コイル、高密度コネクター、高密度配線な
どの分野で要求されている。例えば、コイルの製
造法には、通常、巻き線方式が用いられている
が、この方法では小型のコイルを製造することは
困難であり、かつ巻き線の状態にバラツキが生じ
る。また、35μm銅箔をエツチングしたいわゆる
プリントコイルは、サイドエツチングのためフア
インパターンは得られず、たかだか2〜3本/mm
の線密度のパターンしか得られずこの方法も小型
のコイルを製造することはむつかしい。しかしな
がら、近年モーターの小型化にともない、10〜20
本/mmのフアインパターンを有するフアインコイ
ルの開発が要望されている。 本発明は、先ず膜厚0.1〜10μmの薄膜導電体を
形成した後、陰極の電流密度5〜15A/dm2の条
件でピロリン酸銅メツキ液をを用いて電解メツキ
して厚付けすることにより、線密度5本/mm以上
の高線密度、高信頼性の厚膜フアインパターンが
得られることを見い出したものである。 すなわち、本発明は、フイルム基板上に予め形
成した薄膜導電体膜にマスク法またはエツチング
法を適用して形成した薄膜導電体パターン上に、
金属パターン導体路を電解メツキにより形成する
回路パターンの製造において、薄膜導電体の膜厚
が0.1〜10μm(無電解メツキ薄膜導電体膜の場合
には、1〜10μm)であり、電解メツキがピロリ
ン酸銅メツキ液を用いて、陰極の電流密度5〜
15A/dm2の条件である線密度5本/mm以上で厚
さ20μm以上の導体を有する厚膜フアインパター
ンの製法である。 薄膜パターン上に厚さ20μm以上の線密度5
本/m以上の回路パターンを厚付けするために
は、ピロリン酸銅メツキ液を用いて、電解電流密
度5A/dm2の下で電解メツキすることが肝要で
ある。 第1図及び第2図は、ピロリン酸銅メツキ液を
用いて陰極電流密度2A/dm2と5A/dm2下で電
解メツキしたときの場合の電解メツキ層(厚付け
層)の断面成長を示すもので、スパツタリング法
により厚さ0.3μmの薄膜導電体膜を形成した後、
エツチング法によつて形成した幅85μm、間隔
40μm(線密度8本/m)の薄膜導電体パターン上
に電解メツキにより厚付け層を成長させた場合の
例で示す。 陰極電流密度が2A/dm2の電解メツキでは、
電解メツキ層の幅方向は厚み方向の約2倍の速さ
で成長し、厚さ方向で20μm成長させたとき幅方
向の太りのために隣接のメツキ層と衝突した短絡
してしまう(第1図)のに対し、陰極電流密度が
5A/dm2の電解メツキでは逆にメツキ層の厚さ
方向の成長は、幅方向の2倍に近い速さで成長す
る(第2図)。 第3図は、第1図、第2図で説明した手法で得
た電解メツキ層の幅方向の成長長さ(線の幅方向
の長さ)に対して成長厚さ方向の長さをプロツト
して得た電解メツキ層の成長曲線で、ピロリン酸
銅メツキ液を用いる電解メツキでは、厚さ方向の
メツキ層成長速度が幅方向のメツキ層成長速度よ
りも著しく大きいという異方向性のメツキ層成長
が陰極電流密度5A/dm2以上で生じることを示
している。 ピロリン酸銅メツキ液を用いて陰極電流密度
5A/dm2以上で電解メツキすることは、線密度
5本/mm以上で厚さ20μm以上の導体を有する厚
膜フアインパターンを線間短絡を生じせしめるこ
となく製造する上で不可欠の条件である。特に好
適な陰極電流密度条件は5A/dm2〜15A/dm2
である。 20A/dm2以上の場合は、膜幅の増加に対する
膜厚の増加がより大きくなるがやけが生じる様に
なる。 本発明の目的とする高線密度の厚膜フアインパ
ターンは無電解メツキ法により得ることができな
い。無電解メツキ法では厚付けをしても膜厚方向
の成長以上に幅方向の太りが生じ短絡を生じてし
まう。 本発明において厚付けパターンは、フイルム基
板の片面だけに形成しても、必要に応じて両面に
形成してもよい。両面に形成する場合はフイルム
基板に穴あけし、スルーホール接続を行う必要が
ある。1枚のフイルム基板の上に複数のパターン
を形成する場合は、フイルム基板の両面にパター
ンを形成しスルーホール接続した方がつなぎ込み
が容易であり好ましい。 本発明に使用される半導体基板としては、ポリ
エステルフイルム、エポキシフイルム、ポリイミ
ドフイルム、ポリパラバン酸フイルム、トリアジ
ンフイルムなどフイルム状のものはすべて使用出
来るが、可撓性、耐熱性の点からポリイミドフイ
ルム、ポリパラバン酸フイルム、トリアジンフイ
ルムが好ましい。フイルム基板の膜厚は、高密度
化という意味では出来るだけ薄いものが好ましい
が、余り薄過ぎると作業性が悪くなり、膜厚とし
ては5〜50μ、特に10〜25μmが好ましい範囲であ
る。 また、必要に応じて、フイルム基板と導電体の
接着性を向上する為に、フイルム基板上に接着層
を設けても良い。接着剤としては、ポリエステル
―イソシアネート系、フエノール樹脂―ブチラー
ル系、フエノール樹脂―ニトリルゴム系、エポキ
シ―ナイロン系、エポキシ―ニトリルゴム系など
があり、耐熱性、耐湿性、接着性の優れたものが
好まく、特にエポキシ―ニトリルゴム系接着剤が
好ましい。接着剤の膜厚は高密度化、接着性の点
から、1〜20μm、特に2〜10μmが好ましい範囲
である。 本発明に使用される薄膜導電体としては、導電
性のものであれば何でも良いが、銀、金、銅、ニ
ツケル、スズなどが好ましく、特に導電性、経済
性の点から銅が好ましい。 本発明でフイルム基板上に予め膜厚0.1〜10μm
の薄膜導電体膜を形成する方法としては、蒸着、
スパツタリング、イオンプレーテイングなどの方
法、無電解メツキによる方法、銅薄膜を貼る方法
などがある。 本発明は直接パターン状に薄膜導電体を形成す
るものではなく、まず基板の全面に薄膜を形成す
るために、膜厚として0.1μm(無電解メツキによ
る場合は1μm以上)以上あれば均一な連続膜が得
られる。 この薄膜導電体膜は、従来公知のフオトエツチ
ング法などにより、電解メツキ前にフアインパタ
ーン状にパターニングするか、また薄膜導電体膜
上にフオトレジストでパターン状にマスクして薄
膜導電体のフアインパターンを形成した後に電解
メツキを行なう。後者の場合フアインパターン以
外の薄膜導電体膜をエツチングなどにより除去さ
れる。 薄膜導電体膜の膜厚が、0.1μm以下では均一な
電解メツキがむつかしく、10μm以上ではフアイ
ンパターンの製造が困難であり、0.1〜10μm、特
に電解メツキ適用前に薄膜導電体のエツチングに
よる高線密度パターンの形成や電解メツキ適用後
に電解メツキ層パターン外の残つた薄膜導電体の
エツチング除去が容異な0.2〜5μmが好ましい範
囲である。 銅の電解メツキとしては、シアン化銅メツキ、
ピロリン酸銅メツキ、硫酸銅メツキ、ホウフツ化
銅メツキなどがあるが、本発明は特に中性領域で
のメツキが可能なピロリン酸銅メツキを用いる。
ピロリン酸銅メツキ液は硫酸銅メツキ液に比べて
フイルム基板上の薄膜導電体を損傷しにくい。 フアインパターンを電解メツキする場合、重要
な因子としては陰極の電流密度があり、陰極電流
密度が小さい場合は、膜厚方向以上に幅方向への
太りが生じ、かつメツキ膜厚が不均一になり易
く、陰極電流密度としては、5A/dm2以上、特
に5〜15A/dm2が好ましい範囲である。除極電
流密度が5A/dm2以下の場合は幅方向への太り
が生じ陰極電流密度が20A/dm2以上になるとや
けが生じる様になる。電解メツキ膜厚は設計値に
より異なるが、10〜50μmが好ましい範囲である。 また、より信頼性を向上する為に、必要に応じ
て、電解メツキ後熱処理或いは金、スズ、ハンダ
又はポリマーからなる保護層を設けるなどの処理
が行われる。 以上に示した発明により、厚膜フアインパター
ンの回路、たとえば10〜20本/mm、膜厚20〜
50μm、特に驚くべきことには今まで不可能視さ
れていた35μm以上の回路を提供することができ
る。 以下に本発明の態様を一層明確にする為に、実
施例を挙げて説明するが、本発明は以下の実施例
に限定されるものではなく、種々の変形が可能で
ある。 実施例 1 デユポン社製がポリイミドフイルム「カプト
ン」(膜厚25μm)上に、表面処理、無電解銅メツ
キ(膜厚5μm)、フオトエツチングで膜厚5μmの
薄膜導電体パターンを形成し、次いで、ハーシヨ
ウ村田社製ピロリン酸銅メツキ液を用いて、陰極
電流密度14A/dm2の条件で銅を20μm厚電解メ
ツキを行つて、膜厚25μmで12.5本/mmのフアイ
ンパターンを得た。 実施例 2 エツソ化学社製ポリパラバン酸フイルム「トラ
ドロン」(膜厚25μm)の両面に、ボスチツク社製
エポキシ―ニトルゴム系接着剤「XA―564―9」
を乾燥後片面膜厚が5μm塗布し、穴あけ、銅蒸着
して得られた膜厚0.3μmの薄膜導電体を、フオト
レジスト(膜厚5μm)でパターン以外をマスク
し、次いで、ハーシヨン村田社製ピロリン酸銅メ
ツキ液を用いて、陰極電流密度7A/dm2の条件
で銅35μm厚電解メツキを行い、その後パターン
以外の薄膜銅をエツチング除去して、膜厚35μm
で10本/mmのフアインパターンを得た。 実施例 3 銅を50μm厚電解メツキする以外は、実施例2
と同様に処理して、膜厚50μmで7.4本/mmのフア
インパターンを得た。 比較例 1〜2 陰極電流密度を第1表に示す如くする以外は、
実施例1と同様に処理した。その結果を第1表に
示す。
The present invention relates to a method for manufacturing a thick film fine pattern with high density and high reliability. Thick film fine patterns are required in fields such as small coils, high-density connectors, and high-density wiring that require high current values. For example, a wire winding method is usually used to manufacture coils, but this method makes it difficult to manufacture small coils and causes variations in the state of the windings. In addition, so-called printed coils made by etching 35 μm copper foil cannot obtain a fine pattern due to side etching, and only 2 to 3 coils/mm are etched at most.
This method also makes it difficult to manufacture small-sized coils. However, with the miniaturization of motors in recent years,
There is a demand for the development of a fine coil having a fine pattern of 1/mm. The present invention first forms a thin film conductor with a thickness of 0.1 to 10 μm, and then thickens it by electrolytically plating it using a copper pyrophosphate plating solution at a cathode current density of 5 to 15 A/ dm2 . It has been discovered that a thick film fine pattern with a high linear density of 5 lines/mm or more and high reliability can be obtained. That is, in the present invention, on a thin film conductor pattern formed by applying a mask method or an etching method to a thin film conductor film previously formed on a film substrate,
In the production of circuit patterns in which metal pattern conductor paths are formed by electrolytic plating, the film thickness of the thin film conductor is 0.1 to 10 μm (1 to 10 μm in the case of electroless plating thin film conductor film), and the electrolytic plating is performed using pyrroline. Using acid copper plating solution, the current density of the cathode is 5~
This is a method for producing a thick film fine pattern having a conductor with a line density of 5 lines/mm or more and a thickness of 20 μm or more, which is the condition of 15 A/dm 2 . Line density 5 with a thickness of 20 μm or more on a thin film pattern
In order to thicken a circuit pattern with a thickness of more than 1/m, it is important to perform electrolytic plating using a copper pyrophosphate plating solution at an electrolytic current density of 5 A/dm 2 . Figures 1 and 2 show the cross-sectional growth of an electrolytically plated layer (thick layer) when electrolytically plated using a copper pyrophosphate plating solution at cathode current densities of 2 A/dm 2 and 5 A/dm 2. After forming a thin conductive film with a thickness of 0.3 μm using the sputtering method,
Width 85μm, spacing formed by etching method
An example is shown in which a thick layer is grown by electrolytic plating on a thin film conductor pattern of 40 μm (linear density 8 lines/m). In electrolytic plating with a cathode current density of 2A/ dm2 ,
The electroplated layer grows at about twice the speed in the width direction as in the thickness direction, and when it grows by 20 μm in the thickness direction, it collides with the adjacent plating layer due to the thickening in the width direction (first ), whereas the cathode current density is
In the case of electrolytic plating at 5 A/dm 2 , on the contrary, the plating layer grows at a rate nearly twice as fast in the thickness direction as in the width direction (Figure 2). Figure 3 plots the length in the growth thickness direction against the growth length in the width direction (length in the width direction of the line) of the electroplated layer obtained by the method explained in Figures 1 and 2. The growth curve of the electrolytically plated layer obtained using the copper pyrophosphate plating solution shows an anisotropic plating layer in which the growth rate of the plating layer in the thickness direction is significantly higher than the growth rate of the plating layer in the width direction. It is shown that growth occurs at cathodic current densities of 5 A/dm 2 or higher. Cathode current density using copper pyrophosphate plating solution
Electrolytic plating at 5A/dm2 or more is an essential condition for producing thick film fine patterns with conductors of 20μm or more in thickness and with a line density of 5 lines/mm or more without causing line-to-line short circuits. be. Particularly suitable cathode current density conditions are 5A/dm 2 to 15A/dm 2
It is. In the case of 20 A/dm 2 or more, the increase in the film thickness with respect to the increase in the film width becomes larger, which causes burns. The thick film fine pattern with high linear density, which is the object of the present invention, cannot be obtained by electroless plating. In the electroless plating method, even if the film is thickened, the film thickens in the width direction more than the film grows in the thickness direction, resulting in a short circuit. In the present invention, the thickening pattern may be formed on only one side of the film substrate, or may be formed on both sides as necessary. When forming on both sides, it is necessary to drill holes in the film substrate and make through-hole connections. When forming a plurality of patterns on one film substrate, it is preferable to form the patterns on both sides of the film substrate and connect them through through holes, since this makes connection easier. As the semiconductor substrate used in the present invention, all film-like materials such as polyester film, epoxy film, polyimide film, polyparabanic acid film, and triazine film can be used. Acid film and triazine film are preferred. The film thickness of the film substrate is preferably as thin as possible in the sense of high density, but if it is too thin, workability deteriorates, so the film thickness is preferably in the range of 5 to 50 μm, particularly 10 to 25 μm. Further, if necessary, an adhesive layer may be provided on the film substrate in order to improve the adhesion between the film substrate and the conductor. Adhesives include polyester-isocyanate, phenolic resin-butyral, phenolic resin-nitrile rubber, epoxy-nylon, and epoxy-nitrile rubber, which have excellent heat resistance, moisture resistance, and adhesive properties. Epoxy-nitrile rubber adhesives are preferred, particularly epoxy-nitrile rubber adhesives. The thickness of the adhesive is preferably 1 to 20 μm, particularly 2 to 10 μm, from the viewpoint of high density and adhesive properties. The thin film conductor used in the present invention may be any conductive material, but silver, gold, copper, nickel, tin, etc. are preferred, and copper is particularly preferred from the viewpoint of conductivity and economy. In the present invention, the film thickness is 0.1 to 10 μm on the film substrate in advance.
Methods for forming thin conductor films include vapor deposition,
Methods include sputtering, ion plating, electroless plating, and pasting a copper thin film. The present invention does not directly form a thin film conductor in a pattern, but first forms a thin film on the entire surface of the substrate, so if the film thickness is 0.1 μm or more (1 μm or more in the case of electroless plating), it will be uniform and continuous. A membrane is obtained. This thin film conductor film is patterned into a fine pattern before electrolytic plating using a conventionally known photo-etching method, or by masking the thin film conductor film in a pattern with a photoresist. After forming the ink pattern, electrolytic plating is performed. In the latter case, the thin conductive film other than the fine pattern is removed by etching or the like. If the film thickness of the thin film conductor film is 0.1 μm or less, it is difficult to perform uniform electrolytic plating, and if it is 10 μm or more, it is difficult to produce a fine pattern. The preferable range is 0.2 to 5 μm, which makes it difficult to remove thin film conductors remaining outside the electrolytically plated layer pattern by forming a linear density pattern or electrolytically plating. Examples of copper electrolytic plating include cyanide copper plating,
There are copper pyrophosphate plating, copper sulfate plating, copper borofluoride plating, etc., but the present invention particularly uses copper pyrophosphate plating which can be plated in a neutral region.
Copper pyrophosphate plating solution is less likely to damage thin film conductors on film substrates than copper sulfate plating solution. When electrolytically plating fine patterns, an important factor is the current density of the cathode. If the cathode current density is small, the film will become thicker in the width direction than in the thickness direction, and the plating film thickness will become non-uniform. The cathode current density is preferably 5 A/dm 2 or more, particularly 5 to 15 A/dm 2 . When the depolarizing current density is 5 A/dm 2 or less, thickening occurs in the width direction, and when the cathode current density is 20 A/dm 2 or more, burning occurs. The electrolytic plating film thickness varies depending on the design value, but is preferably in the range of 10 to 50 μm. Further, in order to further improve reliability, heat treatment after electrolytic plating or treatment such as providing a protective layer made of gold, tin, solder, or polymer is performed as necessary. With the invention described above, thick film fine pattern circuits, for example, 10 to 20 lines/mm, film thickness 20 to
It is possible to provide circuits of 50 μm, and most surprisingly, 35 μm or more, which was previously considered impossible. EXAMPLES In order to further clarify aspects of the present invention, examples will be described below, but the present invention is not limited to the following examples, and various modifications are possible. Example 1 A thin film conductor pattern with a thickness of 5 μm was formed on a polyimide film “Kapton” (film thickness: 25 μm) manufactured by DuPont by surface treatment, electroless copper plating (film thickness: 5 μm), and photo etching, and then, Using a copper pyrophosphate plating solution manufactured by Hershiyo Murata Co., Ltd., copper was electrolytically plated to a thickness of 20 μm at a cathode current density of 14 A/dm 2 to obtain a fine pattern of 12.5 lines/mm with a film thickness of 25 μm. Example 2 Epoxy-nitrile rubber adhesive "XA-564-9" manufactured by Bostik Co., Ltd. was applied to both sides of polyparabanic acid film "Tradron" (film thickness 25 μm) manufactured by Etsuo Chemical Co., Ltd.
After drying, one side was coated with a film thickness of 5 μm, holes were made, and copper vapor deposition was performed to obtain a thin film conductor with a film thickness of 0.3 μm. The area other than the pattern was masked with photoresist (film thickness of 5 μm). Using a copper pyrophosphate plating solution, electrolytically plate copper to a thickness of 35 μm at a cathode current density of 7 A/dm 2 , and then remove the thin copper film other than the pattern by etching to a film thickness of 35 μm.
A fine pattern of 10 lines/mm was obtained. Example 3 Example 2 except that the copper is electrolytically plated to a thickness of 50 μm.
A fine pattern of 7.4 lines/mm with a film thickness of 50 μm was obtained by processing in the same manner as above. Comparative Examples 1-2 Except that the cathode current density was as shown in Table 1,
It was treated in the same manner as in Example 1. The results are shown in Table 1.

【表】 比較例 3〜4 薄膜導電体の膜厚を第2表に示す如くする以外
は、比較例3は実施例2と、比較例4は実施例1
と同様に処理した。その結果を第2表に示す
[Table] Comparative Examples 3 to 4 Comparative Example 3 is the same as Example 2, and Comparative Example 4 is the same as Example 1, except that the film thickness of the thin film conductor is as shown in Table 2.
processed in the same way. The results are shown in Table 2.

【表】 比較例 5 電解メツキ液として硼弗化銅メツキ液を用いる
以外は、実施例2と同様に処理した。その結果、
短絡が生じた。
[Table] Comparative Example 5 The same process as in Example 2 was carried out except that a copper borofluoride plating solution was used as the electrolytic plating solution. the result,
A short circuit has occurred.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、2A/dm2の陰極電流密度で電解メ
ツキを行つた場合の電解メツキ層の成長状況を示
す図、第2図は、5A/dm2の陰極電流密度で電
解メツキを行つた場合の電解メツキ層の成長状況
を示す図、第3図は、ピロリン酸銅メツキ液での
電解メツキによるメツキ層の成長曲線である。 図中、1は基板、2は金属薄板、3は電解メツ
キ層を示す。
Figure 1 shows the growth of the electrolytically plated layer when electrolytically plated at a cathode current density of 2A/ dm2 , and Figure 2 shows the growth of the electrolytically plated layer when electrolytically plated at a cathode current density of 5A/ dm2 . FIG. 3 is a growth curve of a plating layer formed by electrolytic plating using a copper pyrophosphate plating solution. In the figure, 1 is a substrate, 2 is a thin metal plate, and 3 is an electroplated layer.

Claims (1)

【特許請求の範囲】[Claims] 1 フイルム基板上に予め形成した薄膜導電体膜
にマスク法またはエツチング法を適用して形成し
た薄膜導電体パターン上に、金属パターン導体路
を電解メツキにより形成する回路パターンの製造
において、薄膜導電体膜の膜厚が0.1〜10μm(無
電解メツキ薄膜導電体膜の場合には、1〜10μm)
であり、電解メツキがピロリン酸銅メツキ液を用
いて、陰極電流密度5〜15A/dm2の条件である
ことを特徴とする線密度5本/mm以上で厚さ
20μm以上の導体を有する厚膜フアインパターン
の製法。
1. In manufacturing a circuit pattern in which a metal pattern conductor path is formed by electrolytic plating on a thin film conductor pattern formed by applying a mask method or an etching method to a thin film conductor film previously formed on a film substrate, a thin film conductor is used. The film thickness of the film is 0.1 to 10 μm (1 to 10 μm in the case of electroless plating thin film conductor film)
The line density is 5 lines/mm or more and the thickness is
A method for manufacturing thick film fine patterns with conductors of 20 μm or more.
JP16926879A 1979-12-27 1979-12-27 Thin film fine pattern and method of manufacturing same Granted JPS5694684A (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP16926879A JPS5694684A (en) 1979-12-27 1979-12-27 Thin film fine pattern and method of manufacturing same
US06/219,155 US4392013A (en) 1979-12-27 1980-12-22 Fine-patterned thick film conductor structure and manufacturing method thereof
NLAANVRAGE8006987,A NL183380C (en) 1979-12-27 1980-12-22 PATTERNED AND THICK LAYER CONTAINING CONDUCTOR CONSTRUCTION AND METHOD FOR MANUFACTURING THESE
GB8041120A GB2066583B (en) 1979-12-27 1980-12-23 Thick film conductor
DE3048740A DE3048740C2 (en) 1979-12-27 1980-12-23 Method for producing a finely screened thick film conductor track arrangement

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16926879A JPS5694684A (en) 1979-12-27 1979-12-27 Thin film fine pattern and method of manufacturing same

Publications (2)

Publication Number Publication Date
JPS5694684A JPS5694684A (en) 1981-07-31
JPH0154874B2 true JPH0154874B2 (en) 1989-11-21

Family

ID=15883350

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16926879A Granted JPS5694684A (en) 1979-12-27 1979-12-27 Thin film fine pattern and method of manufacturing same

Country Status (1)

Country Link
JP (1) JPS5694684A (en)

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* Cited by examiner, † Cited by third party
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WO2015199116A1 (en) * 2014-06-26 2015-12-30 住友電工プリントサーキット株式会社 Printed wiring board, electronic component, and method for producing printed wiring board

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0620019B2 (en) * 1986-12-16 1994-03-16 富士電機株式会社 Fine wire coil take-out and holding device
JP5231863B2 (en) * 2008-05-16 2013-07-10 東京応化工業株式会社 Three-dimensional structure having conductive layer and method of manufacturing three-dimensional metal structure

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5243976A (en) * 1975-10-03 1977-04-06 Sumitomo Bakelite Co Method of producing printed circuit board

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015199116A1 (en) * 2014-06-26 2015-12-30 住友電工プリントサーキット株式会社 Printed wiring board, electronic component, and method for producing printed wiring board
JP2016009854A (en) * 2014-06-26 2016-01-18 住友電工プリントサーキット株式会社 Printed wiring board, electronic component, and printed wiring board manufacturing method
US10111330B2 (en) 2014-06-26 2018-10-23 Sumitomo Electric Printed Circuits, Inc. Printed circuit board, electronic component, and method for producing printed circuit board

Also Published As

Publication number Publication date
JPS5694684A (en) 1981-07-31

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