JPH0154894B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to improvements in phase control circuits used in sonar and the like.

In the Seidoltzking sonar, as shown in FIG. 1, a large number of ultrasonic transducers 1-1, 1-2...
is installed on the side of the duplexer towed by the ship.

Here, in order to change the transmission direction and reception direction of ultrasonic waves without rotating each transducer itself, it is necessary to continuously change the phase of the transmission signal given to each transducer and the reception signal from each transducer. It becomes necessary.

An example of a conventional phase control circuit used for this purpose is shown in FIG. In this figure, the oscillator 2 that generates the frequency f _T is N times the desired local oscillation frequency f _C for driving the vibrator (N is a constant)
It has an oscillator 3 that generates a frequency Nf _C , and frequency dividers 4-1, 4-2, . Here, n is a numerical value equal to the number of oscillators, and each frequency divider corresponds to each oscillator. The output of oscillator 2 is given to program counter 5. The program counter 5 is composed of a number of flip-flops connected in series, and divides the input signal by changing the division ratio in accordance with the tilt angle applied to the terminal 5a, and each division value is output in parallel. is given to each frequency divider 4-1, 4-2, . Each frequency divider 4-
1, 4-2, . . . start frequency division if there is an output from the program counter 5. Therefore, each frequency divider 4-
The outputs of 1, 4-2, . . . output signals with frequencies f _C sequentially delayed by a constant phase amount.

In such a conventional phase control circuit, in order to reduce the minimum tilt angle control amount, it is necessary to increase the oscillation frequency f _T of the oscillator 2, and the oscillation frequency Nf _C of the oscillator 3 must also be made higher than f _T. It won't happen.
For example, if the local oscillation frequency f _C is 515 kHz and the minimum tilt angle control amount is 1°, the frequency f _T is 37 MHz, which requires a high frequency crystal and a complicated digital circuit. Further, according to such a circuit, it is not possible to change the tilt amount continuously, and it is difficult to easily obtain positive and negative tilt amounts.

It is an object of the present invention to eliminate such conventional drawbacks, and to provide a phase control circuit that can continuously vary the amount of phase with a simple configuration.

DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention of the present application will be described below with reference to embodiments and drawings. FIG. 3 shows an embodiment of the present invention. In this diagram, an oscillator 10 is an oscillator that oscillates at a local oscillation frequency f _C , and its output is sent to a phase comparator 11-1 (abbreviated as PC in the diagram).
is applied to the first input terminal of. This phase comparator is one that locks when the two inputs are in phase. A phase comparator 11-1, a low-pass filter 12-1 (hereinafter referred to as LPF), and a voltage-controlled oscillator 13-1 connected to the output side thereof.
(hereinafter referred to as VCO) constitutes a well-known phase locked loop (hereinafter referred to as PLL).
The output of the VCO 13-1 is applied to the second input terminal of the phase comparator 11-1 and the first input terminal of the next stage phase comparator 11-2. Phase comparator 11-
2.LPF12-2 and VCO13-2 are also PLL
The output of the VCO 13-2 is connected to the second input terminal of the phase comparator 11-2 and the next stage.
It is applied to the first input terminal of the phase comparator 11-3 of the PLL circuit. The same applies to each stage below. In the present application, an adder 14-1 is provided between the low-pass filter and the voltage controlled oscillator of each PLL circuit.
14-2, . . . , 14-n are provided. The phase shift amount setter 15 sets a desired phase change amount in correspondence with the voltage, and its output is sent to one input terminal of the adders 14-1, 14-2, . . . , 14-n. Given. Each VCO13-1, 13-2,
...The output of 13-n is the output terminal 16-1, 16-
2,..., 16-n.

Next, the operation of this embodiment will be explained. If the output voltage of the phase amount setter 15 is zero, n normal
The PLL circuits are connected in cascade. Therefore, each output terminal 16-1, 16-
2, . . . , 16-n all output signals that are equal to the oscillation frequency f _C of the oscillator 10 and have the same phase.
In this way, if the output voltage of the phase amount setter 15 is zero, outputs with uniform phases can be obtained from each output terminal.

Next, when the phase shift amount setter 15 outputs a positive predetermined voltage, the output of the oscillator 10 is changed to the phase comparator 11-
1, is added to the adder 14-1 via the LPF 12-1. The adder 14-1 adds the output of the LPF 12-1 and the output of the phase shift amount setter 15 and outputs the VCO 13.
-1. So that this added value becomes zero
VCO 13-1 is controlled. Therefore, in the locked state, the output of the VCO 13-1 is equal to the oscillation frequency f _C of the oscillator 10, and the phase is advanced by a predetermined amount θ, that is, the phase θ. This VCO13-1
The output is outputted to the output terminal 16-1 and simultaneously applied to the next stage phase comparator 11-2. This phase comparator 11-2, LPF 12-2, adder 14-2
The PLL circuit composed of the VCO 13-2 and the VCO 13-2 also operates in a similar manner. Here, since the adder 14-2 is given the same positive voltage from the phase shift amount setter 15 as that for the adder 14-1, the VCO 13-2
is advanced by the phase θ from the phase comparator 11-2. Therefore, a signal whose phase is ahead of the oscillator 10 by 2θ and whose frequency is equal to the oscillation frequency f _c is obtained from the output terminal 16-2. Since this signal becomes the reference, the next stage PLL circuit also performs the same operation and further
A signal whose phase is advanced by this amount is obtained from the output terminal 16-8. FIG. 4 shows this state, in which the phase of the output of the oscillator 10 is sequentially kθ (k=1,
2,...,n) The advanced signal is sent to each output terminal 16-1,
16-2,..., 16-n. By continuously varying the output voltage of the phase shift amount setting device 15, the magnitude of θ can also be changed continuously, and by making the output of the phase shift amount setting device 15 negative, each output terminal 1
6-1, 16-2, etc., signals whose phase is delayed by a predetermined amount are sequentially obtained.

As described in detail above, according to the invention of the present application, the amount of change in phase can be continuously changed with a relatively simple configuration without using a high frequency crystal or a complicated digital circuit as in the prior art. Furthermore, it is extremely easy to switch between phase retardation and advance, as it is only necessary to change the positive or negative of the voltage of the phase shift amount setter.

The PLL used in the present invention uses a phase comparator that locks when the two inputs are in phase, but an appropriate shifter is used on the output side of the voltage controlled oscillator to connect the phase shifter output and the PLL input. It may be arranged so that it is locked when the signals become in phase. In that case, a phase comparator that locks with a phase difference of 90°, for example, can be used.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing the oscillator of a side-looking sonar, Fig. 2 is a block diagram of a conventional phase control circuit, Fig. 3 is a block diagram of a phase control circuit showing an embodiment of the present invention, and Fig. 4 is a block diagram of a phase control circuit showing an embodiment of the present invention. The figure is a graph showing input and output waveforms of the phase control circuit of FIG. 3. 10... Oscillator, 11-1, 11-2... Phase comparator, 12-1, 12-2... Low pass filter, 13-1, 13-2... Voltage suppressed oscillator, 1
4-1, 14-2... Adder, 15... Phase shift amount setter.

Claims (1)

[Claims] 1. A phase comparator that compares the phases of a reference signal and the output of a voltage controlled oscillator and generates a voltage according to the phase difference, and outputs a signal with a frequency corresponding to the output voltage of this phase comparator. A plurality of phase-locked loop circuits each having a voltage controlled oscillator are configured to be connected in cascade to each other such that the output of the voltage controlled oscillator in the previous stage serves as a reference signal for the phase comparator in the subsequent stage, and a phase shift amount setter that provides a voltage corresponding to the amount of change in phase; and an adder that adds the output voltage of each phase comparator and the output voltage of the phase shift amount setter in each of the phase-locked loop circuits. A phase control circuit comprising: 2. Claim 1, wherein the phase-locked loop circuit is locked when two inputs of a phase comparator are in phase.
The phase control circuit described in .