JPH0155785B2 - - Google Patents

Description

[Detailed Description of the Invention] (Technical Field) The present invention relates to code error control suitable for coded teletext broadcasting in which character and graphic information coded as digital signals is multiplexed transmitted during the vertical retrace period of a TV signal. In particular, it relates to an error correction decoding circuit that attempts to recover as much as possible by correcting bit errors occurring on a transmission path.

(Technical background) As an error correction method for this type of service using a TV transmission path, one packet is composed of 272 bits, and a data signal of 272 data bits, 190 information bits, and 82 parity bits is formed and transmitted. The method for decoding was proposed in a patent application filed in 1982.
6579 (Japanese Unexamined Patent Publication No. 133751/1983), Patent Application 1987-
54002 (Japanese Unexamined Patent Publication No. 59-181841), and
58-90017 (Japanese Unexamined Patent Publication No. 59-216388).

FIG. 1 shows the configuration of the error correction decoding circuit disclosed herein. In FIG. 1, 1 is a CPU bus line connected to a CPU (not shown), and is connected to an input terminal of an output port 2 and an output terminal of an input port 3. The output signal of output port 2 is supplied to an error correction circuit, and the input signal of input port 3 is supplied from the error correction circuit. The error correction circuit 4 includes a parallel-serial conversion circuit, a serial-parallel conversion circuit,
It includes syndrome registers, data registers, etc., and performs operations to correct (272, 290) codes.

Next, the operation shown in FIG. 1 will be explained. The data before correction
It is supplied from the CPU to output port 2 via CPU bus line 1. The uncorrected data received by the output port 2 is corrected by the error correction circuit 4, supplied to the input port 3, and transmitted to the CPU via the CPU bus line 1.

In Figure 1, assuming that signals are exchanged between the CPU and the error correction unit via the CPU bus in units of 8 bits, for example, 1 packet = 272 bits of uncorrected data is supplied from the CPU to the error correction decoding circuit. It takes 34 bytes to process the data, and it takes a similar amount of time to supply one packet of data corrected by the error correction circuit 4 from the error correction decoding circuit to the CPU.

Furthermore, in Japanese teletext broadcasting, up to 12 packets can be transmitted in one vertical period, and if you try to process all of them, one vertical period =
The data transfer time between the CPU and the error correction decoding circuit during 16.67mS is 34 byte time x 2 x 12 = 816
This extends to part-time work time.

These transfers are performed by the CPU's write and read commands, and during this transfer time, the CPU cannot perform any other processing, so it must decode the codes and display formats necessary for receiving and displaying teletext. This will cause problems in processing such as generation of . In particular, since the error correction operation in the error correction circuit 4 is performed asynchronously with the operation of the CPU,
The CPU must constantly detect whether or not the error correction for one packet has been completed, and as soon as the error correction is completed, the CPU must shift to the operation of reading data from input port 3. is interrupted intermittently and frequently.

In actual teletext broadcasting, multiple packets of data are transmitted serially during the vertical retrace period, so in the circuit configuration shown in Figure 1, the serially received data is serial-parallel converted and read by the CPU.
In some cases, it may be necessary to temporarily store the data in memory.

As explained above, the conventional technology shown in Figure 1 imposes a heavy burden on the CPU, requiring much of the processing time, and in fact cannot perform all the processing necessary for receiving and displaying teletext. It had the disadvantage of being stored away.

(Objective and Summary of the Invention) In order to eliminate the drawbacks of the prior art, the present invention has a buffer memory for storing and holding uncorrected data and post-corrected data, and the present invention has a buffer memory for storing and holding uncorrected data and post-corrected data. The degree of freedom of operation of the CPU is increased by automatically transferring previous data to the buffer memory and automatically transferring corrected data to the buffer memory.

(Embodiment of the Invention) A circuit diagram of a first embodiment of the invention is shown in FIG. In Figure 2, 10 is the CPU data bus,
Further, 11 is the address bus of the CPU. The data bus 10 of the CPU is the first bus of the data bus control circuit 16.
A second input/output terminal of the data bus control circuit 16 is connected to a local data bus 17, and the local data bus 17 is connected to a data input/output terminal of the error correction circuit 12. It is connected to the data input/output terminal of the buffer memory 13.

The address bus 11 of the CPU is connected to a first input terminal of an address switching circuit 14. An output terminal of the address switching circuit is connected to an address input terminal of the buffer memory. 15
is a received data input terminal, which is connected to the signal input terminal of the error correction circuit 12. The error correction circuit has an address output terminal 18,
This address output terminal is the address switching circuit 1.
4 is connected to the second input terminal of 4.

Next, the operation shown in FIG. 2 will be explained.

Of the received broadcast signals, only the teletext signal inserted in the vertical blanking period is extracted and applied to the received data input terminal 15 in FIG. 2, and supplied to the error correction circuit 12. This teletext signal is binary serial data of 272 bits with 190 information bits and 82 parity bits per packet. One packet = 272 bits of data is sent every arbitrary horizontal scanning period from the 10th to the 21st H of the vertical retrace period. Maximum per vertical blanking period
12 packets of data are sent.

In the first operating mode, packet reception data is written to buffer memory 13 via local data bus 17.

The error correction circuit 12 includes a data transfer section, the detailed circuit configuration of which will be explained later, converts the serial teletext signal applied to the received data input terminal 15 into serial-to-parallel signals and transfers it to the local data bus 17. and supplies it to the buffer memory 13 via this. The number of bits of the local data bus 17 is arbitrarily selected depending on the type of CPU or the bit configuration of the buffer memory, but in practice it is 8 bits to 16 bits. In the following explanation, both the CPU bus and local data bus are 8.
The case of bits will be explained.

At the same time, the error correction circuit 12 has an address generation section, and outputs an address signal for specifying which address in the buffer memory 13 to write to the address output terminal 18, and outputs an address signal to the second input terminal of the address switching circuit 14. supply to.

The first input terminal of the address switching circuit 14 has a
In the first operation mode, an arbitrary address signal is supplied from the CPU via the CPU address bus.
That is, during the transfer of serial reception data, the signal at the second input terminal is selected, outputted to the output terminal of the address switching circuit, and controlled so as to be supplied to the address input terminal of the buffer memory 13. At the same time, the data bus control circuit 16 is controlled so that the CPU data bus 10 and the local data bus 17 are separated. Thus, in the first operation mode, serially received data is written to the address of the buffer memory 13 specified by the address generator in the error correction circuit.

As will be explained later, the transfer in the first operation mode, that is, the transfer of serial reception data (data before correction) is written in an area in the buffer memory 13 that is different from the area where the data after correction is stored. .

In addition, in the transfer in the first operation mode, if the bit capacity of the local data bus 17 is assumed to be 8 bits, 1 packet = 272 bits of data is transferred, which is 272 ÷ 8 = 34, and the data is divided into 34 times. . Therefore, in the buffer memory 13, 34 addresses are required as data before correction. If multiple packets, for example 12 packets of uncorrected data are stored in the buffer memory 13, 34 addresses will form 1 block and 12
A memory area for each block is required.

In the transfer in the first operation mode, practically, it is preferable to continuously transfer all packets (for example, 12 packets) in one vertical blanking period. And during this time
Since the CPU does not need any intervention, it can perform other processing.

In the second operation mode, the uncorrected data stored in the buffer memory in the first operation mode is supplied to an error correction circuit for correction.

In the second mode of operation, the error correction circuit 12
The buffer memory 1 is connected to the address output terminal 18.
The address signal of the location to be read out is sent out and supplied to the second input terminal of the address switching circuit 14. In this case, that is, in the second operation mode, the address switching circuit 14 operates to select the signal at the second input terminal and send it to the output terminal, so that the address output signal of the error correction circuit changes to the address of the buffer memory. Supplied to the input terminal.

At the same time, the data bus switching circuit 16 is controlled to separate the CPU data bus 10 and the local data bus 17, so that the error correction circuit 12 receives the output signal of the buffer memory 13 via the local data bus 17. Thus, error correction circuit 1
The contents of the buffer memory 13 at the address specified by 2 enter the error correction circuit 12. If the number of bits of the local data bus 17 is 8 bits, data transfer in these second operation modes is performed every 8 bits, and the address output of the error correction circuit 12 is output every time 8 bits are transferred. Since the signal at the terminal changes, the uncorrected data in the buffer memory 13 is sequentially transferred to the error correction circuit. 3
Data transfer of 272 bits=1 packet is completed by four transfers. The error correction circuit 12 treats one packet of data as a unit block and performs error correction.

Buffer memory 13 in second operating mode
Since the uncorrected data transfer from to the error correction circuit 12 is managed by the error correction circuit 12,
There is no need for the CPU to intervene, and the CPU can perform other processing.

When transfer and correction are performed in the second operation mode, a third operation mode is entered, that is, an operation mode in which corrected data is written to the buffer memory 34 times in 8-bit increments. One packet of data corrected in the second operation mode is sequentially loaded in 8-bit units onto the local data bus 17 and supplied to the data input/output terminal of the buffer memory 13. Also in the third operation mode, the data bus control circuit 16 operates to separate the local data bus 17 from the CPU data bus 10.

On the other hand, the error correction circuit 12 has a buffer memory 13.
An address output signal is applied to the second input terminal of the address switching circuit 14 to supply an address signal to the address switching circuit 14. Also in the third operation mode, the address switching circuit 14 operates to select the address signal applied to the second input terminal and supply it to the address input terminal of the buffer memory 13. error correction circuit 12
operates to update the address output terminal every time 8-bit corrected data is sent to the local data bus 17, so that the error-corrected data is stored in the buffer memory 13 in sequence.

At this time, if the corrected data is stored at the same address where the uncorrected data was stored, the uncorrected data will disappear. In order to retain the data before correction, it is necessary to store the data after correction in a different area. 3 and 4 illustrate mapping when storing data in the buffer memory.

In FIG. 3, 20-31 and 40-51 are memory areas for storing one packet of data, respectively. One packet consists of 34 bytes of data, so if addresses are assigned in byte units, the memory area for one packet only needs to be 34 addresses. Therefore, the uncorrected data of the first packet is assigned to addresses 0 to 33, that is, 20, and
The uncorrected data of the 12th packet is assigned to addresses 34 to 67, that is, 21, and the uncorrected data of the 3rd packet is assigned to addresses 68 to 101, that is, 22. In the same manner, the uncorrected data of the 12th packet is assigned to 21.
Assigned to addresses 374 to 407, ie 31.

On the other hand, as a storage area for corrected data, 40~
Prepare 51. In terms of addresses, the area from 408 to 815 is equivalent to 12 packets.

In devices that use a CPU or memory, it is often convenient from a software and hardware standpoint to set not only the data length but also the address size to 2 ⁿ (n is an integer). In Figure 4, the memory area for one packet is 2 ⁶ =
Only 64 bytes are reserved. Furthermore, an area for 2 ⁴ =16 packets is secured for both the pre-correction and post-correction areas. Mapping buffer memory in this manner creates unnecessary memory area, but this area can be used for other purposes. According to the method shown in FIG. 4, a memory area of 2048 bytes (commonly called 2k bytes) is all that is required, and so-called 16k-bit RAM can be easily used, which is convenient.

Next, the fourth operation mode will be explained. Fourth
In the operating mode, the CPU reads error-corrected data stored in the buffer memory 13 in order to process and display the error-corrected data. In FIG. 2, in the fourth operation mode, the address switching circuit 14 operates to select the signal applied to the first input terminal and apply it to the address input terminal of the buffer memory 13, so the address specified by the CPU is is supplied to buffer memory 13 via CPU address bus 11 and address switching circuit 14. 4th at the same time
In the operation mode, data bus control circuit 1
6 operates to connect the CPU data bus 10 to the local data bus 17. Thus, in the fourth operating mode, the contents of buffer memory 13 addressed by the CPU are transferred to local data bus 17, control circuit 16 and CPU data bus 1.
0 to the CPU or main memory. The CPU buffers memory 1 at the desired time.
The corrected data stored in 3 can be retrieved and data processing can be performed based on the corrected data in order to perform display necessary for teletext broadcasting.

Next, in order to make the operation of FIG. 2 more clear, a more detailed circuit diagram of the error correction circuit 12 is shown in FIG. 17 and 18 in FIG. 5 are equivalent to those with the same numbers in FIG. 2, and 68a is equivalent to the received data input terminal 15 in FIG.

In FIG. 5, 60 is a timing control section which receives a reference clock pulse 87 and receives a first clock pulse 87.
A switching signal 61 is generated as a timing output signal of
A third timing output signal is supplied to the data transfer section 63, a fourth timing output signal is supplied to the address generation section 64, and a status signal 64 is generated. The status signal 67 is
This is a signal indicating whether or not the CPU may access the buffer memory 13, and in the first to third modes, for example, "H" is output, and in other cases, it is "L". The CPU detects the status signal 67, confirms that it is "L", and then accesses the buffer memory.

68a is serial reception data, 68b is a framing detection signal, 68c is serial reception data 6
These clock pulses are synchronized with the data string 8a, and both are supplied to the data transfer section 63.

The data transfer unit transfers the pre-correction signal 65 to the error correction unit 6.
It also receives a corrected signal 66 from the error correction section 62, supplies an address increment pulse 69 to the address generation section 64, and is also connected to the local data bus 17. Address generation section 6
4 functions to generate an address signal for addressing the buffer memory.

Next, the operation shown in FIG. 5 will be explained. In FIG. 5, an error correction section 62 receives a pre-correction signal 65 from a data transfer section 63, corrects it in packet units, and provides a post-correction signal 66 to the data transfer section 63.

The data transfer unit 63 has a reception data input terminal 68
The serial reception data given to a is serial-parallel converted and sent to the local data bus 17 (first
operation mode), receives the uncorrected data sent from the buffer memory 13 to the local data bus 17, performs parallel-to-serial conversion to generate the uncorrected signal 65, and transmits it to the error correction unit 62 (second (in the third operation mode) and serial-to-parallel convert the corrected signal 66 sent from the error correction section 62 and send it to the local data bus 17 (in the third operation mode).

The flow of each signal in each operation mode is as follows. In the first operation mode, data is transferred from the serial reception data input terminal 68a to the data transfer unit 63 to the local data bus 17. During this time, the data transfer unit 63 generates an address increment pulse every time one byte of data is transferred. 69 is generated and given to the address generation unit 64, thereby the address signal 18 is updated and can be sequentially written into the buffer memory.

In the second operation mode, data is transferred as follows: local data bus 17 → data transfer unit 63 → pre-correction signal 65 → error correction unit 62, and the address generation unit 64 updates the address every time one byte is transferred. Since the timing control unit 60 supplies the timing signal, the data are read out from the buffer memory 13 in one byte unit sequentially.

In the third operation mode, data is transferred as follows: error correction unit 62 → corrected signal 66 → data transfer unit 63 → local data bus 17, and every byte is transferred by a timing pulse from the timing control unit 60. The address generator 64 then updates the address and can sequentially write the corrected data into the buffer memory 13.

In FIG. 5, in order to more specifically illustrate the operation of receiving serial reception data by the data transfer unit 63 and storing it in the buffer memory 13, details are shown in the sixth section.
7 and 8.

FIG. 6 is a timing chart showing the format of packet reception data, and is the same as FIG. 16 of Japanese Patent Application No. 58-6579. That is, in FIG. 6, 70 is a horizontal synchronization signal, 71 is a color burst, 72 is a clock line in for clock synchronization, 73 is a framing signal for frame synchronization, and 74 is a 34-byte packet signal, that is, serial reception data 68a. represents. A framing detection signal 68b is generated when frame synchronization is achieved by the framing signal 73, and a clock pulse 68c is generated when the frame is synchronized by the clock run-in 72.

FIG. 7 shows the serial received data 68 by the framing detection signal 68b and clock pulse 68c.
A partial circuit diagram of a data transfer section 63 for storing data a into the buffer memory 13 via the local data bus 17 is shown. 8 is a timing diagram showing the operation of FIG. 7, which is a partial circuit of the data transfer section 63. In FIG.

In FIG. 7, 80 is a gate circuit, which operates to supply a clock pulse 68c to the clock pulse input terminal of the shift register 81 when the frame detection signal 68b is "L". Shift register 81 sequentially takes in and shifts serial received data 68a in response to pulses from a clock pulse input terminal, and supplies an 8-bit shifted signal to an input terminal of register 82. register 8
2 takes in the 8-bit signal supplied from the shift register 81 by means of a latch pulse 85, and supplies the taken-in 8-bit signal to the bus line interface circuit 83. Bus line interface circuit 83 sends the 8-bit signal supplied from register 82 to local data bus 17 at a designated timing. By counting the output pulses of the gate circuit 80, the data reception control circuit 84 issues a latch pulse 85 to transfer the serial reception data to the register 82 every time 8 bits = 1 byte of serial reception data is shifted to the shift register 81. A write pulse 86 to the buffer memory 13 is generated every time one byte is transferred, and an address increment pulse 69 is generated to update the address every time one byte is transferred.

Thus, in FIG. 7, the serially sent packet reception data is converted into 8-bit units and sequentially sent to the local data bus 17 via the bus interface circuit 83. During this time, address increment pulse 69 and buffer memory write pulse 8
6, the 8-bit unit data sent to the local data bus 17 is sequentially written to different addresses in the buffer memory 13.

In FIG. 8, 93 is the local data bus 1
This shows the contents of the data sent out at 7 and shows that the data is updated by the latch pulse 85.

As explained above, if the circuit shown in FIG. 5 is used as the error correction circuit 12 in FIG.
Pre-correction data and post-correction data can be stored and held without the intervention of the CPU. During this time, the CPU may be performing other processing.

In the above description, the CPU data bus 10 and the local data bus 17 have an 8-bit=1-byte configuration, but other bit configurations, such as a 4-bit configuration or a 16-bit configuration, may be used.

In addition, in the first embodiment, the received data is stored in the buffer memory 13 and the uncorrected data is retained, but if the uncorrected data is not needed, the uncorrected data is stored in the buffer memory 13. It can be stored at the same address as the data, or it can obviate the first mode of operation and is applied to the receive data input terminal 15. It is also possible to directly transmit the serial reception data to the error correction section 62 via the data transfer section 63 and correct it.

Next, as a method for generating an address when transferring received data to the buffer memory 13, another embodiment that is more effective will be described below.

In order to explain this embodiment, the buffer memory mapping shown in FIG. 4 is rewritten and shown in FIG. 9. For example, the first packet data before correction is stored in addresses 0 to 33. The first address is address 0, and if address 0 is expressed in binary notation, it is “000, 0000, 0000” (“000” in hexadecimal notation)
It is. The second packet data before correction is stored from address 64 to address 97. The first address is address 64, and if address 64 is expressed in binary representation, it is “000,
0100, 0000"("040" in hexadecimal representation). In the same way, the start address where the packet data before and after correction is stored is divided into decimal representation, binary representation, and hexadecimal representation. They are listed in Figure 9. 11 bits are required as an address signal to give a total of 2048 bytes of address, and they correspond to A ₁₀ , A ₉ , A ₈ ...A ₀ in order from the most significant bit. What should be noted in Figure 9 is that the packet number can be expressed with only 4 bits, _A9 , _A8 , _A7 , and _{A6.A5 to A0 correspond} to the byte numbers within the packet. _A10 serves as an identification bit as to whether the data is before correction or after correction.

Therefore, the addressing when storing received data in buffer memory is based on packet numbers _A9 to _A6.
All you have to do is make it correspond to .

Further, in order to explain the operation of this embodiment, a timing diagram of the teletext data to be transmitted is shown in No. 10. In FIG. 10, 100a is a vertical synchronizing signal, 100b is a vertical blanking signal, 100
c is a vertical synchronizing signal 100a and a vertical blanking signal 1
00b or vertical blanking signal 100b, and both of these are repetitive pulse signals whose period is one vertical scanning period.

The vertical blanking period is 21 horizontal scanning periods (hereinafter referred to as 21H).
(H represents the horizontal scanning period), of which data for teletext broadcasting is carried for 12 hours after the 10th hour. That is,
Only 12H after the vertical signal 100c is inverted from "L" to "H" has meaning as teletext data. Since the data loaded in the 1H period is 1 packet, the 1st packet data is loaded in the 10th hour, the 2nd packet data is loaded in the 11th hour, and so on, and the 12th packet is loaded in the 21st hour. Contains data on.

FIG. 11 shows a partial circuit diagram of the address generation circuit for transferring and storing received data in the buffer memory 13 in this embodiment. In Figure 11, 1
00c is the vertical signal shown in FIG. 10, which is a repetitive pulse for each vertical scanning period. 110 is a horizontal clock pulse input terminal for a horizontal synchronization signal or a horizontal blanking signal, and is connected to a clock pulse input terminal CK of a 4-bit counter 111. At the same time, the vertical signal 100c is applied to the reset input terminal R of the 4-bit counter 111. Numerals 113-116 are respective bit output terminals of the 4-bit counter 111, and form address output signals _A6 - _A9, respectively.

Next, the operation shown in FIG. 11 will be explained with reference to FIGS. 9 and 10. The 4-bit counter 111 is reset until the period when the vertical signal 100c is "L", that is, the 9th H of the vertical blanking period.
Do not count horizontal clock pulses. The 4-bit counter 111 starts counting from the 10th H.
10H has not counted up yet, so
86 to 83 are “0000” and address signal A ₉
~ _A6 is "0000" and can give the address of the first packet in FIG. 11H
4-bit counter 111 counts up and the output signals 116-11 of the 4-bit counter
3 is "0001", and the address signals _A9 to _A6 are "0001", so that the address of the second packet can be given.

Similarly, 4-bit counter 1 every 1H
11 counts up and the address signals _A9 to _A6 sequentially increment to update the address.

Although not shown in Fig. 11, _A10 is
For example, it is given from the vertical blanking period signal, ie, the vertical blanking signal 100b in FIG. 10, and is set to "L" during the period in which packet reception data is inserted.

In addition, the lower bit signals A ₅ to _{A 0} of the address are
It is generated by counting the address step pulse 69 in FIG. 5 or the address step pulse supplied from the timing control section 63.

As explained above, in this embodiment, addressing of the buffer memory can be easily performed by counting the horizontal synchronizing signal or the horizontal blanking signal.

(Effects of the Invention) As explained above, according to the present invention, the error correction decoding circuit has a function of sequentially storing received data sent serially in a buffer memory, and sequentially reading and correcting uncorrected data stored in the buffer memory. function and the function to sequentially store corrected data in the buffer memory,
During these operations, the CPU does not need to intervene;
During this time, the CPU can perform other processing,
The degree of freedom of CPU operation can be increased,
This is extremely effective for code-based teletext receivers.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram of a conventional error correction decoding circuit, Fig. 2 is a circuit diagram of an error correction decoding circuit according to an embodiment of the present invention, Figs. 3 and 4 are mapping diagrams of buffer memory, and Fig. 5 is a circuit diagram of a conventional error correction decoding circuit. Circuit diagram of error correction circuit, No. 6
7 is a partial circuit diagram of the data transfer section. FIG. 8 is a timing diagram showing the operation of the partial circuit of the data transfer section. FIG. 9 is a mapping diagram of the buffer memory. FIG. 10 is a timing diagram of teletext data, and FIG. 11 is a partial circuit diagram of an address generation circuit. 1...CPU bus line, 2...Output port,
3...Input port, 4...Error correction circuit, 10...
...CPU data bus, 11...CPU address bus,
12...Error correction circuit, 13...Buffer memory, 14...Address switching circuit, 15...Receive data input terminal, 16...Data bus control circuit, 1
7...Local data bus, 18...Address output terminal of error correction circuit, 20-31, 40-51
...Packet memory area, 32-35, 52-
55... Packet memory area, 60... Timing control section, 61... Switching signal, 62... Error correction section, 63... Data transfer section, 64... Address generation section, 65... Signal before correction, 66 ...Corrected signal, 67...Signal indicating whether or not the CPU may access the buffer memory, 68a...Serial reception data, 68b...Framing detection signal,
68c...Clock pulse, 69...Address step pulse, 70...Horizontal synchronization signal, 71...Color burst, 72...Clock run in, 73...
...Framing signal, 74...34-byte packet signal, 80...Gate circuit, 81...Shift register, 82...Register, 83...Bus interface circuit, 84...Data reception control circuit, 85
...Latch pulse, 86 ...Write pulse, 10
0a...Vertical synchronization signal, 100b...Vertical blanking signal, 100c...Vertical signal, 110...Horizontal synchronization signal or horizontal blanking signal, 111...
4-bit counter, 113-116... Output signal of 4-bit counter. 87...Clock pulse.

Claims (1)

[Claims] 1. A local data bus; an error correction circuit that corrects errors in teletext code data and transfers the corrected data to the local data bus; a buffer memory for storing data; selectively transferring an address signal output from the error correction circuit and an address signal output from a CPU (central processing unit) to the buffer memory;
an address switching circuit that specifies an address of the buffer memory; and an address switching circuit coupled between the data bus of the CPU and the local data bus, and when the address switching circuit selects the address signal output from the error correction circuit, the data bus and a data bus control circuit that separates between the local data bus and the local data bus. 2. The error correction circuit includes an address generation section that generates an address signal to be applied to the buffer memory, an error correction section that corrects code data, and transfers received data to the local data bus or the error correction section, or a data transfer unit that operates to transfer data on the local data bus to the error correction unit or transfer data from the error correction unit to the local data bus, the address generation unit, the error correction unit, and the data transfer unit; 2. The error correction decoding circuit according to claim 1, further comprising a timing control section that supplies a predetermined timing signal. 3. Error correction decoding according to claim 1 or 2, wherein the buffer memory has an area for storing uncorrected data and an area for storing post-corrected data at different addresses. circuit. 4. The address generation unit determines an address for storing received data by counting horizontal pulse signals.
The error correction decoding circuit described in Section 1. 5. The data transfer unit transmits a signal for detecting frame synchronization using a framing signal included in a packet signal for character code broadcasting, and a clock clamp signal also included in a packet signal for character code broadcasting. 3. The error correction decoding circuit according to claim 2, further comprising means for sending the received packet data to the local data bus using a clock pulse synchronized with the IN signal.