JPH0156538B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing an ohmic electrode.
Relates to the manufacturing method of GaAs MESFET.

[Technical background of the invention and its problems]

As is well known, GaAs MESFETs have recently been studied in various fields as high-speed integrated circuit elements. Particular emphasis is placed on the gate electrode structure. Conventionally, gates and ohmic electrodes have been formed by mask alignment, and the precision of alignment has determined the dimensions between the gate and ohmic electrodes. Conventionally, as a GaAs MESFET, one shown in FIG. 4, for example, is known.

1 in the figure is a semi-insulating GaAs substrate. On the surface of this substrate 1, N ⁺ type low resistance regions 2 and 3 are provided spaced apart from each other. These areas 2,
3 is an N ^- type region 4, and a gate electrode 5 is provided on this region 4. Furthermore, high melting point metal layers 6, 6 are provided in the low resistance regions 2, 3, respectively. However, this FET
According to , when the gate length becomes short, a short channel effect occurs and Gm decreases.

In response, NEC's Higasisaka et al. have proposed the following (Extended
Abstracts of the Conference on Solid
StateDevices and Materils.Tokyo.1983pp69~
72). This is a Side Wall-Assisted Closely
It is called Spaced Electrode Technology, and a cross-sectional view of its process is shown in Figure 3.

First, Si ions are selectively implanted into the surface of the GaAs substrate 11 to form the active region 12.
Subsequently, a film with a thickness of 4000 to 5000 Å is placed on the substrate 11.
A gate electrode 13 made of Al is formed (as shown in FIG. 3a). Next, an oxide film 14 having a thickness of 2000 to 6000 Å is formed on the entire surface by CVD (as shown in FIG. 3B). Thereafter, this oxide film 14 is left only on the side walls of the gate electrode 13 by reactive ion etching (RIE) (as shown in FIG. 3c). Furthermore, after depositing an AuGe/Ni layer 15 that will become an ohmic electrode on the entire surface, a photoresist 16 is coated (see Fig. 3d).
(Illustrated). Note that this photoresist 16 is thin on the gate electrode 13 and thick on the field region. Continuing, the photoresist 16 is applied.
The area around the gate electrode 13 is etched by RIE.
FIG. 3e shows only the AuGe/Ni layer 15 exposed). After this, the area around the gate electrode 13 is exposed.
The AuGe/Ni layer 15 is removed by ion milling, and the photoresist 16 is further removed to form an alloy (as shown in FIG. 3f). By this method, the gate electrode 13 and the ohmic contact become a self-line, and the Gm of the MESFET becomes high, allowing high-speed operation. However, as mentioned above
According to the MESFET manufacturing method, after depositing the photoresist 16, the photoresist 16 is etched back, and the AuGe/Ni layer around the gate electrode 14 is etched back.
Since RIE, ion milling, etc. are used in the process of removing the layer 15, it is very difficult to control the process and uniformity cannot be obtained.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a method for manufacturing a semiconductor device that allows ohmic electrodes to be easily formed by self-alignment, increases Gm, and enables high-speed operation.

[Summary of the invention]

The present invention includes a step of forming a high-melting point metal layer on a semiconductor substrate having an impurity region on the surface, a step of forming a first film on the high-melting point metal layer that can be selectively etched together with the first film, and and a step of patterning the high melting point metal layer to form a coating pattern and a gate electrode, and a second step capable of selectively etching the coating pattern and gate electrode over the entire surface.
a step of forming a third film having the same composition as the film pattern on the second film; and a step of etching away the third film by reactive ion etching. a step of leaving the coating on the coating pattern and the sidewalls of the gate electrode via a second coating, and selectively etching and removing the second coating exposed from the opening to form an ohmic electrode on the impurity region. process and
This method is characterized by a step of removing ohmic electrode materials other than ohmic electrodes, and can easily form ohmic electrodes by self-alignment, and can improve Gm and enable high-speed operation. .

[Embodiments of the invention]

Hereinafter, a case in which the present invention is applied to manufacturing a GaAs MESFET will be described with reference to FIGS. 1a to 1i.

(1) First, on the surface of the semi-insulating GaAs substrate 21,
Type impurity acceleration voltage 40-100KeV, dose 1.0
After implanting into the substrate 21 under conditions of ~5.0×10 ¹² cm ^-2 , annealing is performed for 15 minutes at a temperature of 700 to 900°C to form an N-type active channel region (impurity region) 22.
was formed. Next, WSi, WN,
A high melting point metal layer 23 of WAl, Ti, TiSi, etc. was formed (as shown in FIG. 1a). At this time, the film thickness is determined taking into account the gate resistance, but it is 1000 to 5000 Å.
An appropriate range is between. Next, a silicon oxide film (first film) 24 was formed on the high melting point metal layer 23 by a plasma method (as shown in FIG. 1B).
Thereafter, using a resist (not shown) as a mask, the silicon oxide film 24 and the high melting point metal layer 23 are selectively etched away to form a coating pattern 2.
5. Gate electrodes 26 were formed (Fig. 1c)
(Illustrated). Furthermore, after peeling off the resist, a silicon nitride film (second film) 27 was formed on the entire surface by plasma method, and a silicon oxide film (third film) 28 was further formed by the same method (first film).
Figure d shown).

(2) Next, on this silicon oxide film 28, an opening 2 is formed in a portion corresponding to the active channel region 22.
A resist 30 as a mask material having 9 was formed. Subsequently, using this resist 30 as a mask, the silicon oxide film 28 is selectively etched away by RIE, and the gate electrode 28 is etched away.
An oxide film pattern (sidewall) 31 was left on the side wall of the coating pattern 25 (as shown in FIG. 1e). Next, the exposed silicon nitride film 27 was selectively etched away using the resist 30, the film pattern 25, and the sidewall 31 as a mask to expose the active channel region 22 and remove the resist 30 (as shown in FIG. 1f). . Further, an AuGe/Ni layer 32 as an ohmic electrode material was deposited on the entire surface (as shown in FIG. 1g). In addition, in the same figure g, the AuGe/Ni layer 32 on the active channel region 22 is called ohmic electrodes 32a and 32b. After that, the opening 29 is removed by removing the film pattern 25, the silicon nitride film 27, and the sidewall 31.
The remaining AuGe/Ni layer 32 was removed (lift-off). As a result, the AuGe/Ni layer (ohmic electrode) 32 except for the gate electrodes 32a and 32b on the active channel region 22 was removed. Subsequently, as shown in FIG. 1h, after forming a protective film 33 on the entire surface, the ohmic electrodes 32a, 32
The contact holes 34 are formed by selectively removing the protective film 33 corresponding to the wirings 3 and 3.
5 was formed to manufacture a GaAs MESFET (as shown in FIG. 1i).

According to the present invention, the gate electrode 26 and the coating pattern 25 are formed on the GaAs substrate 21,
Silicon nitride film 27 and silicon oxide film 28 on the entire surface
, and further has an opening 29.
A sidewall 31 is formed on the sidewalls of the gate electrode 26 and the film pattern 25 by RIE using as a mask, and then selective etching of the silicon nitride film 27 is performed using the sidewall 31 and the like as a mask.
Through each step of forming the AuGe/Ni layer 32, the ohmic electrodes 32a, 32b can be formed in a self-aligned manner only on the N-type active channel region 22. Therefore, it has the following effects.

It is possible to obtain a higher Gm than the FET shown in Fig. 4, and to maintain gate breakdown voltage. Furthermore, the short channel effect can also be reduced. That is, in the FET shown in FIG. 4, the resistance between the gate and the source is reduced by forming the N ⁺ type low resistance regions 2 and 3. In this case, when the concentration in this region increases, the withstand voltage between the gate and the low resistance region deteriorates, and conversely, when the concentration decreases, Gm decreases. Also, when forming a low resistance region, it was not possible to form a low resistance region, so the gate,
It is impossible to reduce the resistance between low resistance regions to a local extent. Furthermore, when a low resistance region is formed, short channels are likely to occur. For this reason, attempts have been made to bring the ohmic electrode as close as possible to the gate, but since this is done through mask alignment, there is a risk of it being shot with the gate.

The ohmic electrodes 32a, 32b can be easily formed using normal processes.

In fact, compared to the FET shown in Figure 4, the Gm has increased by 1.5 times, and the reverse breakdown voltage of the Schottky diode has also achieved good results of over 10V, compared to the conventional 4-6V. Furthermore, the short channel effect did not appear significantly when the gate length was 1.0 μm. Furthermore, the PEP process could be shortened by 1 to 2 steps.

In the above embodiment, silicon oxide films were used as the first and third films, and silicon nitride films were used as the second film, but the present invention is not limited thereto. That is, the first coating may be made of a material that can be selectively etched with respect to the high melting point metal layer, and the second coating may be made of a material that can be selectively etched with respect to the first coating (coating pattern) and the gate electrode. However, the third coating may be made of the same material as the first coating.

Further, in the above embodiment, the AuGe/Ni layer was deposited on the entire surface after exposing the active channel region as shown in FIG. 1f, but the present invention is not limited thereto. For example, after etching the substrate, n-type impurities may be ion-implanted into the exposed substrate 21 to facilitate ohmic formation as shown in FIG. 2, and then annealed to form N ⁺ -type layers 41 and 42. In this way, the ohmic characteristics can be further improved compared to the embodiment.

〔Effect of the invention〕

As detailed above, according to the present invention, ohmic electrodes can be easily formed by self-alignment, and Gm can be increased to enable high-speed operation.
It is possible to provide a method for manufacturing semiconductor devices such as GaAs MESFETs.

[Brief explanation of drawings]

Figures 1 a to i relate to an embodiment of the present invention.
FIG. 2 is a cross-sectional view showing the manufacturing method of GaAs MESFET in the order of steps, according to another embodiment of the present invention.
Cross-sectional view during the manufacturing process of GaAs MESFET, Part 3
Figures a to f are cross-sectional views showing the conventional GaAs MESFET manufacturing method in order of process, and Figure 4 is a cross-sectional view showing the conventional manufacturing method of GaAs MESFET.
FIG. 2 is a cross-sectional view of a GaAs MESFET. 21... Semi-insulating GaAs substrate, 22... N-type active channel region, 23... High melting point metal layer, 2
4, 28... Silicon oxide film, 25... Film pattern, 26... Gate electrode, 27... Silicon nitride film (second film), 29... Opening, 30...
Resist, 31... Silicon oxide film pattern (side wall), 32... AuGe/Ni layer, 32a,
32b...gate electrode, 33...protective film, 34...
...Contact hole, 35...Wiring, 41, 42
...N ⁺ type layer.

Claims (1)

[Claims] 1. A step of forming a high melting point metal layer on a semiconductor substrate having an impurity region on the surface, a step of forming a first film on this high melting point metal layer which can be selectively etched together with the first film, a step of patterning the melting point metal layer to form a coating pattern and a gate electrode; a step of forming a second coating on the entire surface that can be selectively etched with respect to the coating pattern and the gate electrode; forming a third coating having the same composition as the coating pattern;
forming a mask material having an opening in a portion corresponding to the impurity region on the third film;
Using this mask material, the third coating is removed by reactive ion etching, and the third coating is applied to the coating pattern and the sidewalls of the gate electrode.
a step of selectively etching away the second film exposed from the opening to expose the impurity region; and a step of depositing an ohmic electrode material on the entire surface on the impurity region. A method for manufacturing a semiconductor device, comprising the steps of forming an ohmic electrode and removing ohmic electrode material other than the ohmic electrode.