JPH0156542B2 - - Google Patents
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- Publication number
- JPH0156542B2 JPH0156542B2 JP60037432A JP3743285A JPH0156542B2 JP H0156542 B2 JPH0156542 B2 JP H0156542B2 JP 60037432 A JP60037432 A JP 60037432A JP 3743285 A JP3743285 A JP 3743285A JP H0156542 B2 JPH0156542 B2 JP H0156542B2
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- JP
- Japan
- Prior art keywords
- layer
- type
- semiconductor
- electron
- molecular beam
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/60—Impurity distributions or concentrations
- H10D62/605—Planar doped, e.g. atomic-plane doped or delta-doped
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
- H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
- H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
- H10D30/475—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs
- H10D30/4755—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs having wide bandgap charge-carrier supplying layers, e.g. modulation doped HEMTs such as n-AlGaAs/GaAs HEMTs
Landscapes
- Junction Field-Effect Transistors (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、2次元電子ガス層を生成させて電子
の高速走行を可能とした電界効果型半導体装置の
改良に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to an improvement in a field-effect semiconductor device that generates a two-dimensional electron gas layer and enables high-speed electron travel.
第3図は前記電界効果型半導体装置の従来例に
於けるエピタキシヤル成長半導体層の構成を表す
要部切断側面図である。
FIG. 3 is a cross-sectional side view of a main part showing the structure of an epitaxially grown semiconductor layer in a conventional example of the field effect semiconductor device.
図に於いて、1は半絶縁性GaAs基板、2は高
純度i型GaAs能動層、3は2次元電子ガス層、
4は高純度i型AlXGa1-XAsスペーサ層、5はn
型AlXGa1-XAs電子供給層、6はn型GaAsオー
ミツク電極コンタクト層をそれぞれ示している。 In the figure, 1 is a semi-insulating GaAs substrate, 2 is a high-purity i-type GaAs active layer, 3 is a two-dimensional electron gas layer,
4 is a high purity i-type Al x Ga 1-X As spacer layer, 5 is an n
A type Al x Ga 1-x As electron supply layer and 6 indicate an n-type GaAs ohmic electrode contact layer, respectively.
第4図は第3図に見られるエピタキシヤル成長
半導体層の組成プロフアイルを表す線図である。 FIG. 4 is a diagram representing the composition profile of the epitaxially grown semiconductor layer seen in FIG.
図から判るように、i型AlXGa1-XAsスペーサ
層4及びn型AlXGa1-XAs電子供給層5に於ける
x値が0.3であり、その他の半導体層はx=0で
ある。 As can be seen from the figure, the x value in the i-type Al X Ga 1-X As spacer layer 4 and the n-type Al It is.
このような半導体層を備えた電界効果型半導体
装置は、2次元電子ガス層3にオーミツク・コン
タクトするソース電極及びドレイン電極を設け、
その間の2次元電子ガス層3をチヤネルとして用
い、そのチヤネルをゲート電極で制御するように
している。 A field effect semiconductor device including such a semiconductor layer is provided with a source electrode and a drain electrode in ohmic contact with the two-dimensional electron gas layer 3,
The two-dimensional electron gas layer 3 between them is used as a channel, and the channel is controlled by a gate electrode.
尚、i型AlXGa1-XAsスペーサ層4は、2次元
電子ガス層3に依存する電子とn型AlXGa1-XAs
電子供給層5からのイオン化したドナー不純物と
の空間分離を撤底させる為に設けたものであり、
このようにすると、電子がイオン化したドナー不
純物に依りクローン散乱を受ける度合が著しく小
さくなり、ヘテロ界面に沿つて非常に高い電子移
動度が得られる。この効果は室温でも得られる
が、イオン化した不純物に依る散乱が支配的にな
る低温では特に顕著なものとなる。 Note that the i - type Al
This is provided to eliminate spatial separation from the ionized donor impurities from the electron supply layer 5.
In this way, the degree to which electrons undergo Crohn scattering due to ionized donor impurities is significantly reduced, and extremely high electron mobility can be obtained along the heterointerface. Although this effect can be obtained even at room temperature, it becomes particularly noticeable at low temperatures where scattering due to ionized impurities becomes dominant.
現在、この種の電界効果型半導体装置での最大
の技術課題となつているのは、2次元電子ガス層
3に於ける電子濃度の向上である。
Currently, the biggest technical challenge in this type of field effect semiconductor device is to improve the electron concentration in the two-dimensional electron gas layer 3.
この2次元電子ガス層3に於ける電子濃度はn
型AlXGa1-XAs電子供給層5からi型GaAs能動
層4に滲み出す電子に依存するのであるから、n
型AlXGa1-XAs電子供給層5に対するドーピング
を多くすれば良いことになるが、例えば、x=
0.3である場合に於いては、n型AlXGa1-XAs電子
供給層5に対するドーピンゲ限界は2×1018〔cm
-3〕程度であり、従つて、2次元電子ガス層3に
於ける電子濃度を高めることができない。 The electron concentration in this two-dimensional electron gas layer 3 is n
Since it depends on the electrons leaking from the type Al x Ga 1-x As electron supply layer 5 to the i-type GaAs active layer 4, n
It would be better to increase the doping to the type Al
0.3, the doping limit for the n-type Al x Ga 1-x As electron supply layer 5 is 2×10 18 [cm
-3 ], therefore, the electron concentration in the two-dimensional electron gas layer 3 cannot be increased.
第3図及び第4図について説明されるような半
導体層を成長させるには、通常、分子線エピタキ
シヤル成長(molecular beam epitaxy:MBE)
法を適用しているが、このMBE法は、1種また
はそれ以上の原料原子或いは分子を基板成長面に
衝突、吸収させ、加熱された基板から与える熱エ
ネルギで適当な格子点に移動させて半導体層を成
長させる超高真空成長プロセスであり、例えば、
n型GaAs層を成長させる場合、超高真空チヤン
バ内にシヤツタを有する分子線セルをGa用、As
用、Si(n型不純物)用の三つを配設し、分子線
セルを加熱して蒸気圧が所定値に上昇したところ
で各シヤツタを開きn型GaAsの成長を開始す
る。 To grow semiconductor layers such as those illustrated in FIGS. 3 and 4, molecular beam epitaxy (MBE) is typically used.
This MBE method involves colliding and absorbing one or more raw material atoms or molecules onto the growth surface of the substrate, and moving them to appropriate lattice points using thermal energy provided by the heated substrate. It is an ultra-high vacuum growth process for growing semiconductor layers, for example,
When growing an n-type GaAs layer, a molecular beam cell with a shutter in an ultra-high vacuum chamber is used for Ga and As.
The molecular beam cell is heated, and when the vapor pressure rises to a predetermined value, each shutter is opened and the growth of n-type GaAs is started.
前記したようなn型AlXGa1-XAs電子供給層5
に於ける不純物濃度を高めることができない理由
に関しては、種々の説明或いは主張が展開されつ
つあるが、いま一つ判然としないのが実情であ
る。 n-type Al x Ga 1-x As electron supply layer 5 as described above
Although various explanations or arguments are being developed as to why it is not possible to increase the impurity concentration in the material, the reality is that it is still not clear.
尚、前記欠点を解消する手段として、例えば、
i型AlXGa1-XAsスペーサ層4を薄くしたり、全
く形成しない等の対策も採られているが、それで
も、2次元電子ガス層3に於ける電子濃度として
最高で1×1012〔cm-2〕程度しか得られない。 In addition, as a means to eliminate the above-mentioned drawbacks, for example,
Countermeasures have been taken, such as making the i - type Al Only about [cm -2 ] can be obtained.
このように2次元電子ガス層3の電子濃度を高
めることができないことは、電流を取り出せない
ことに結び付き、従つて、伝達コンダクタンスg
mは小さいから、例えば、メモリのアクセスなど
に用いた場合には、負荷容量の充放電に時間が掛
かるので、システム全体のスピードは低く抑えら
れてしまう。 The inability to increase the electron concentration in the two-dimensional electron gas layer 3 leads to the inability to extract current, and therefore the transfer conductance g.
Since m is small, for example, when used for memory access, it takes time to charge and discharge the load capacitor, so the speed of the entire system is kept low.
本発明に於ける一実施例を解説する為の図であ
る第1図及び第2図を借りて説明すると、本発明
電界効果型半導体装置は、半絶縁性半導体基板の
一種である半絶縁性GaAs基板1上に形成され且
つ電子親和力が大である高抵抗半導体からなる能
動層の一種である高純度i型GaAs能動層2と、
該高純度i型GaAs能動層2上に形成され且つ前
記高純度i型GaAs能動層2に比較して電子親和
力が小である高抵抗半導体からなるスペーサ層の
一種である高純度i型AlXGa1-XAsスペーサ層4
と、該高純度i型AlXGa1-XAsスペーサ層4上に
形成され且つ前記高純度i型GaAs能動層2に比
較して電子親和力が小である高不純物濃度半導体
からなる電子供給層の一種であるn型AlXGa1-X
As電子供給層5と、高純度i型AlXGa1-XAsスペ
ーサ層4とn型AlXGa1-XAs電子供給層5との界
面付近にアトミツク・プレーン・ドーピング法に
て形成された高不純物濃度薄膜5Aとを備えてな
る構成を採つている。
To explain with reference to FIGS. 1 and 2, which are diagrams for explaining one embodiment of the present invention, the field effect semiconductor device of the present invention is a semi-insulating semiconductor substrate, which is a type of semi-insulating semiconductor substrate. A high-purity i-type GaAs active layer 2, which is a type of active layer formed on a GaAs substrate 1 and made of a high-resistance semiconductor with high electron affinity;
High-purity i-type Al Ga 1-X As spacer layer 4
and an electron supply layer formed on the high-purity i-type Al x Ga 1-x As spacer layer 4 and made of a highly impurity-concentrated semiconductor having a lower electron affinity than the high-purity i-type GaAs active layer 2. n-type Al x Ga 1-X
The As electron supply layer 5 is formed near the interface between the high-purity i-type Al x Ga 1-X As spacer layer 4 and the n-type Al The structure includes a high impurity concentration thin film 5A.
ここで、前記アトミツク・プレーン・ドーピン
グ(APD)法を適用してn型GaAs層を成長する
場合について説明しよう。 Here, a case will be described in which an n-type GaAs layer is grown by applying the above-mentioned atomic plane doping (APD) method.
超高真空チヤンバ内にシヤツタを有する分子線
セルをGa用、As用、Si用の三つを配設し、ま
た、n型GaAs層を成長させるべき半絶縁性
GaAs基板を配設して加熱する。 Three molecular beam cells with shutters for Ga, As, and Si are installed in an ultra-high vacuum chamber, and a semi-insulating cell for growing an n-type GaAs layer is installed.
A GaAs substrate is placed and heated.
各分子線セルを加熱して蒸気圧が所定値に上昇
したところで例えばAs用及びSi用の分子線セル
のシヤツタを開放する。AsはGaの存在下で初め
てGaAsとしてGaAs基板に被着することが可能
になるものであり、前記のように、As用分子線
セルのシヤツタを開放しても、Asが単独でGaAs
基板に被着することはあり得ない。 When each molecular beam cell is heated and the vapor pressure rises to a predetermined value, for example, the shutters of the molecular beam cells for As and Si are opened. As can only be deposited as GaAs on a GaAs substrate in the presence of Ga, and as mentioned above, even if the shutter of the molecular beam cell for As is opened, As alone cannot adhere to GaAs.
It is impossible for it to adhere to the substrate.
従つて、この場合、GaAs基板に被着されるの
はSiのみであり、Siは加熱されたGaAs基板に衝
突、吸収され、その面上を充分に時間を掛けて移
動し適切な格子点を探すことができる。尚、
GaAs基板にAsが被着しないのにAs用分子線セ
ルのシヤツタを開いておくのは、GaAs基板の温
度が上昇している為、Asが或る程度以上の蒸気
圧を保つた雰囲気を生成しておかないと、GaAs
基板からAsが放出されてしまうことに依る。 Therefore, in this case, only Si is deposited on the GaAs substrate, and the Si collides with the heated GaAs substrate, is absorbed, and moves over the surface for a sufficient amount of time to form appropriate lattice points. You can search. still,
The reason why the shutter of the molecular beam cell for As is kept open even though As is not deposited on the GaAs substrate is because the temperature of the GaAs substrate is rising, which creates an atmosphere in which As maintains a certain level of vapor pressure. Otherwise, GaAs
This is due to As being released from the substrate.
さて、GaAs基板全面に於いてSiが占位し得る
格子点にSiを被着してから、Si用分子線セルのシ
ヤツタを閉成し且つGa用分子線セルのシヤツタ
を開放することに依りGaAs層を数原子層分だけ
成長させ、再び、Ga用分子線セルのシヤツタを
閉成し且つSi用分子線セルのシヤツタを開放して
Siの被着を行う。以後、この工程を必要に応じて
繰り返し、高濃度のn型GaAs層を成長させる。 Now, after depositing Si on the entire surface of the GaAs substrate at lattice points where Si can occupy, we close the shutter of the molecular beam cell for Si and open the shutter of the molecular beam cell for Ga. After growing the GaAs layer by several atomic layers, the shutter of the molecular beam cell for Ga was closed and the shutter of the molecular beam cell for Si was opened again.
Deposit Si. Thereafter, this step is repeated as necessary to grow a highly concentrated n-type GaAs layer.
以上説明した技法がAPD法であり、この技術
に依ると、従来の通常のMBE法に於けるドーピ
ングと比較し、不純物濃度を2倍程度高くするこ
とができる。 The technique described above is the APD method, and according to this technique, the impurity concentration can be increased approximately twice as much as doping in the conventional MBE method.
本発明に依る電界効果型半導体装置では、スペ
ーサ層及び電子供給層の界面付近にAPD法にて
形成された高不純物濃度薄膜が存在していること
から、高抵抗半導体能動層に生成される2次元電
子ガス層に於ける電子濃度は20〔%〕〜30〔%〕程
度高くなり、その結果、伝達コンダクタンスgm
が高くなつて大きな電流を取り出すことが可能で
ある。
In the field effect semiconductor device according to the present invention, since a high impurity concentration thin film formed by the APD method exists near the interface between the spacer layer and the electron supply layer, 2 The electron concentration in the dimensional electron gas layer increases by about 20% to 30%, and as a result, the transfer conductance gm
becomes high, and it is possible to extract a large current.
第1図は本発明一実施例に於けるエピタキシヤ
ル成長半導体層の構成を表す要部切断側面図であ
り、第3図及び第4図に於いて用いた記号と同記
号は同部分を表すか或いは同じ意味を持つものと
する。
FIG. 1 is a cross-sectional side view of essential parts showing the structure of an epitaxially grown semiconductor layer in one embodiment of the present invention, and the same symbols as those used in FIGS. 3 and 4 represent the same parts. or have the same meaning.
本実施例が第3図及び第4図に見られる従来例
と相違する点は、n型AlXGa1-XAs電子供給層5
内にAPD法にて生成した高不純物濃度薄膜5A
が形成されていることであり、この高不純物濃度
薄膜5Aの実体は、例えば、Siが高濃度にドープ
されたn型AlXGa1-XAs薄膜である。 The difference between this embodiment and the conventional example shown in FIGS. 3 and 4 is that the n-type Al x Ga 1-x As electron supply layer 5
High impurity concentration thin film 5A produced by APD method inside
The substance of this high impurity concentration thin film 5A is, for example, an n-type Al x Ga 1-x As thin film doped with a high concentration of Si.
第2図は第1図に見られるエピタキシヤル成長
半導体層の組成プロフアイルを表す線図である。 FIG. 2 is a diagram representing the composition profile of the epitaxially grown semiconductor layer seen in FIG.
図から判るように、n型AlXGa1-XAs電子供給
層5中にAPD法で形成された高不純物濃度薄膜
5Aが存在していても、x値の点では第4図に示
した従来例と相違するところはない。第1図及び
第2図に見られるようなエピタキシヤル成長半導
体層を得る場合について第3図及び第4図に関し
て説明した従来技術と比較して説明する。 As can be seen from the figure, even if the high impurity concentration thin film 5A formed by the APD method exists in the n-type Al x Ga 1-X As electron supply layer 5, the x value shown in Fig. 4 is There is no difference from the conventional example. The case of obtaining an epitaxially grown semiconductor layer as shown in FIGS. 1 and 2 will be described in comparison with the prior art described with reference to FIGS. 3 and 4.
高純度i型AlXGa1-XAsスペーサ層4を成長さ
せる迄は第3図及び第4図に関して説明した従来
例と全く同じである。 The process up to the growth of the high-purity i-type Al x Ga 1-x As spacer layer 4 is exactly the same as the conventional example explained with reference to FIGS. 3 and 4.
次に、Al用分子線セルのシヤツタ及びGa用分
子線セルのシヤツタを閉成し、Si用分子線セルの
シヤツタ及びAs用分子線セルのシヤツタのみを
開放して高濃度のSiドーピングを行う。このとき
のドーピング濃度を具体的に例示すると約1.1×
1019〔cm-2〕である。 Next, close the shutter of the molecular beam cell for Al and the shutter of the molecular beam cell for Ga, and open only the shutter of the molecular beam cell for Si and the shutter of the molecular beam cell for As to perform high concentration Si doping. . A specific example of the doping concentration at this time is approximately 1.1×
10 19 [cm -2 ].
次に、Si用分子線セルのシヤツタを閉成すると
共にAl用分子線セルのシヤツタ及びGa用分子線
セルのシヤツタを再び開放してn型AlXGa1-XAs
電子供給層5を成長させる。ここで高不純物濃度
薄膜はn型AlXGa1-XAs電子供給層5の成長途中
に形成しても良い。 Next, the shutter of the molecular beam cell for Si is closed, and the shutter of the molecular beam cell for Al and the shutter of the molecular beam cell for Ga are opened again to form n-type Al X Ga 1-X As.
The electron supply layer 5 is grown. Here, the high impurity concentration thin film may be formed during the growth of the n-type Al x Ga 1-x As electron supply layer 5.
この後は第3図及び第4図に関して説明した従
来技術と同様にしてn型GaAsオーミツク・コン
タクト層6を成長させれば良く、また、電界効果
型半導体装置として完成させるには、通常の技法
通りにして、ゲート電極、ソース電極、ドレイン
電極等を形成する。尚、前記実施例では、APD
法にて生成した高不純物濃度薄膜を電子供給層内
に形成したが、これはスペーサ層内に形成しても
良い。 After this, the n-type GaAs ohmic contact layer 6 can be grown in the same manner as in the conventional technique explained with reference to FIGS. A gate electrode, a source electrode, a drain electrode, etc. are formed by the following steps. In addition, in the above embodiment, APD
Although the high impurity concentration thin film produced by the method is formed within the electron supply layer, it may also be formed within the spacer layer.
また、高濃度のSiドーピングは複数回実施すれ
ば、より高い電子濃度の2次元電子ガス層を生成
することができる。 Moreover, if high-concentration Si doping is performed multiple times, a two-dimensional electron gas layer with a higher electron concentration can be generated.
本発明に依る電界効果型半導体装置は、能動層
上のスペーサ層及び電子供給層の界面付近に
APD法にて形成された高不純物濃度薄膜を形成
した構成になつている。
In the field effect semiconductor device according to the present invention, near the interface between the spacer layer and the electron supply layer on the active layer,
It has a structure in which a thin film with high impurity concentration is formed using the APD method.
この構成に依れば、前記能動層に生成される2
次元電子ガス層に於ける電子濃度は、従来技術に
依つて製造した此の種の電界効果型半導体装置に
比較して20〜30〔%〕程度も高くなり、その結果、
伝達コンダクタンスgmが高くなつて大きな電流
を取り出すことが可能であり、従つて、メモリの
アクセスなどに用いた場合にも、負荷容量の充放
電を高速で行うことができる。 According to this configuration, 2 generated in the active layer
The electron concentration in the dimensional electron gas layer is about 20 to 30% higher than that of this type of field effect semiconductor device manufactured using conventional technology, and as a result,
As the transfer conductance gm increases, it is possible to extract a large current, and therefore, even when used for accessing a memory, the load capacitance can be charged and discharged at high speed.
また、各半導体層をエピタキシヤル成長させる
場合は勿論のこと、高不純物濃度薄膜をエピタキ
シヤル成長させる際であつても温度を高く維持し
ておくことが可能であるから、スルー・プツトの
低下などの問題は生じない。 In addition, since it is possible to maintain a high temperature not only when epitaxially growing each semiconductor layer but also when epitaxially growing a thin film with high impurity concentration, it is possible to reduce throughput. No problem arises.
第1図は本発明一実施例に於けるエピタキシヤ
ル成長半導体層の構成を示す要部切断側面図、第
2図は第1図に見られるエピタキシヤル成長半導
体層の組成プロフアイルを示す線図、第3図は従
来例に於けるエピタキシヤル成長半導体層の構成
を示す要部切断側面図、第4図は第3図に見られ
るエピタキシヤル成長半導体層の組成プロフアイ
ルを示す線図をそれぞれ表している。
図に於いて、1は半絶縁性GaAs基板、2は高
純度i型GaAs能動層、3は2次元電子ガス層、
4は高純度i型AlXGa1-XAsスペーサ層、5Aは
APD法で形成した高不純物濃度薄膜、5はn型
AlXGa1-XAs電子供給層、6はn型GaAsオーミ
ツク電極コンタクト層をそれぞれ示している。
FIG. 1 is a cross-sectional side view of essential parts showing the structure of an epitaxially grown semiconductor layer in an embodiment of the present invention, and FIG. 2 is a diagram showing the composition profile of the epitaxially grown semiconductor layer shown in FIG. 1. , FIG. 3 is a cross-sectional side view of essential parts showing the structure of the epitaxially grown semiconductor layer in the conventional example, and FIG. 4 is a diagram showing the composition profile of the epitaxially grown semiconductor layer shown in FIG. 3. represents. In the figure, 1 is a semi-insulating GaAs substrate, 2 is a high-purity i-type GaAs active layer, 3 is a two-dimensional electron gas layer,
4 is a high purity i-type Al x Ga 1-X As spacer layer, 5A is a
High impurity concentration thin film formed by APD method, 5 is n-type
6 represents an Al x Ga 1-x As electron supply layer and an n-type GaAs ohmic electrode contact layer.
Claims (1)
和力が大である高抵抗半導体からなる能動層と、
該高抵抗半導体能動層上に形成され且つ前記高抵
抗半導体能動層に比較して電子親和力が小である
高抵抗半導体からなるスペーサ層と、該高抵抗半
導体スペーサ層上に形成され且つ前記高抵抗半導
体能動層に比較して電子親和力が小である高不純
物濃度半導体からなる電子供給層と、前記高抵抗
スペーサ層及び前記電子供給層の界面付近にアト
ミツク・プレーン・ドーピング法にて形成された
高不純物濃度薄膜とを備えてなることを特徴とす
る電界効果型半導体装置。1. An active layer formed on a semi-insulating semiconductor substrate and made of a high-resistance semiconductor with high electron affinity;
a spacer layer formed on the high-resistance semiconductor active layer and made of a high-resistance semiconductor whose electron affinity is smaller than that of the high-resistance semiconductor active layer; An electron supply layer made of a high impurity concentration semiconductor whose electron affinity is lower than that of the semiconductor active layer, and a high resistance spacer layer formed by an atomic plane doping method near the interface between the high resistance spacer layer and the electron supply layer. 1. A field effect semiconductor device comprising: a thin impurity concentration film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60037432A JPS61198783A (en) | 1985-02-28 | 1985-02-28 | Field effect type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60037432A JPS61198783A (en) | 1985-02-28 | 1985-02-28 | Field effect type semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61198783A JPS61198783A (en) | 1986-09-03 |
| JPH0156542B2 true JPH0156542B2 (en) | 1989-11-30 |
Family
ID=12497350
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60037432A Granted JPS61198783A (en) | 1985-02-28 | 1985-02-28 | Field effect type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61198783A (en) |
-
1985
- 1985-02-28 JP JP60037432A patent/JPS61198783A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61198783A (en) | 1986-09-03 |
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