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JPH0158658B2 - - Google Patents
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JPH0158658B2 - - Google Patents

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Publication number
JPH0158658B2
JPH0158658B2 JP18204384A JP18204384A JPH0158658B2 JP H0158658 B2 JPH0158658 B2 JP H0158658B2 JP 18204384 A JP18204384 A JP 18204384A JP 18204384 A JP18204384 A JP 18204384A JP H0158658 B2 JPH0158658 B2 JP H0158658B2
Authority
JP
Japan
Prior art keywords
semiconductor wafer
plate
rotor
wafer
vacuum chuck
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP18204384A
Other languages
Japanese (ja)
Other versions
JPS6159745A (en
Inventor
Yoshio Watanabe
Hitoshi Myazawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP18204384A priority Critical patent/JPS6159745A/en
Publication of JPS6159745A publication Critical patent/JPS6159745A/en
Publication of JPH0158658B2 publication Critical patent/JPH0158658B2/ja
Granted legal-status Critical Current

Links

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はウエハの位置合わせ方法であり、特に
一側部に位置合わせ用の切欠き部を有する板状体
の位置合わせに関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for aligning a wafer, and particularly to aligning a plate-shaped body having a notch for alignment on one side.

半導体装置の製造工程では、電極形成を行う半
導体ウエハ面の位置合わせのために、半導体ウエ
ハの一部に切欠部であるオリエンテーシヨン.フ
ラツト(以下O.F.と略称する)を形成し、このO.
F.を基準ピンに当接させて半導体ウエハの位置決
めを行つている。
In the manufacturing process of semiconductor devices, an orientation hole, which is a cutout in a part of the semiconductor wafer, is used to align the surface of the semiconductor wafer on which electrodes are formed. A flat (hereinafter abbreviated as OF) is formed, and this O.
The semiconductor wafer is positioned by bringing F into contact with the reference pin.

然しながら、従来の基準ピンに半導体ウエハの
O.F.を当接させて位置決めをする方法が複雑な構
造であるために、より容易な方法で位置決めする
方法が要望されている。
However, the conventional reference pin is
Since the method of positioning by bringing the OF into contact has a complicated structure, there is a need for an easier method of positioning.

〔従来の技術〕[Conventional technology]

第6図は従来の半導体ウエハのO.F.を基準ピン
で位置決めをする方法の一例を示す斜視図であ
り、例えばホトリソグラフイ等を行う際に利用さ
れている。
FIG. 6 is a perspective view showing an example of a conventional method for positioning the OF of a semiconductor wafer using reference pins, which is used, for example, when performing photolithography.

アライメント台1の表面上に置かれたO.F.部2
を有する半導体ウエハ3(図では点線で示してい
る)は、アライメント台上で外力Fにより複数の
位置決めピン4,5の方向に押し出され、ここで
半導体ウエハはロータ6により回転されて、O.F.
検出器7により半導体ウエハのO.F.部が検出され
ると、制御装置により自動的に回転モータ6の回
転が停止し、外力fが作動して半導体ウエハを三
個の位置決めピン4,5及び8に押しつけて位置
決めをしている。
OF part 2 placed on the surface of alignment table 1
A semiconductor wafer 3 (indicated by a dotted line in the figure) having an OF
When the OF part of the semiconductor wafer is detected by the detector 7, the rotation of the rotary motor 6 is automatically stopped by the control device, and the external force f is activated to move the semiconductor wafer to the three positioning pins 4, 5, and 8. Positioning is done by pressing.

又、他の方法として半導体ウエハの中心出しを
行つた後、真空チヤツクで構成された軸上で半導
体ウエハを回転させ、上記のような検知方式によ
りO.F.を検出して、回転を制御するものもある。
Another method is to center the semiconductor wafer, then rotate the semiconductor wafer on an axis made of a vacuum chuck, detect the OF using the detection method described above, and control the rotation. be.

これらの装置の共通の欠点として、機構的に複
雑であり、又半導体ウエハを置くアライメント台
が移動性のものであると一段と位置決めが困難に
なる。
A common drawback of these devices is that they are mechanically complex, and if the alignment table on which the semiconductor wafer is placed is movable, positioning becomes even more difficult.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上記の構成の半導体ウエハの位置決め方法にお
いては、構造が複雑であり、又位置決めの精度が
低いことが問題点であり、そのために半導体ウエ
ハの製造工程における能率低下や不良品が発生す
る等の不具合を生ずる。
The problem with the semiconductor wafer positioning method with the above configuration is that the structure is complex and the positioning accuracy is low, resulting in problems such as reduced efficiency and defective products in the semiconductor wafer manufacturing process. will occur.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は上記問題点を解消したウエハの位置合
わせ方法を提供するもので、その手段は、空気ノ
ズルと真空チヤツクとロータと基準板と基準ピン
とを具備した傾斜したアライメント台上で、一側
部に切欠き部を有するウエハを空気ノズルにより
浮揚してロータ部に搬送し、該板状体を該ローラ
で回転させて該切欠き部を基準板に合致させた
後、該ロータと該基準板を一旦除去して、上記真
空チヤツクによつて浮揚状態の該板状体をアライ
メント台上に真空吸着と真空から開放とを間欠的
に行つて緩慢に移動させ、該ウエハを上記基準ピ
ンの位置に配置したことを特徴とする板状体の位
置合わせ方法によつて達成できる。
The present invention provides a method for aligning wafers that solves the above-mentioned problems. A wafer having a notch is floated by an air nozzle and conveyed to the rotor, the plate is rotated by the roller to align the notch with the reference plate, and then the rotor and the reference plate are is temporarily removed, and the plate-shaped body suspended by the vacuum chuck is moved slowly by vacuum suction and release from the vacuum intermittently on the alignment table, and the wafer is moved to the position of the reference pin. This can be achieved by a method of positioning plate-like bodies, which is characterized in that the plate-shaped bodies are arranged in the same direction.

〔作用〕[Effect]

本発明は、傾斜したアライメント台上に設けら
れた空気ノズルにより、浮揚した状態の半導体ウ
エハを一旦ロータと基準板の位置に搬送して密着
させ、ロータで半導体ウエハを回転させて切欠き
部を基準板に合致させ、切欠き部の方向を保持し
たままで、その位置から基準ピンの位置に搬送す
るために、半導体ウエハを真空チヤツクによる真
空吸着と、真空開放とを間欠的に行つて、傾斜し
たアライメント面上を半導体ウエハを緩慢に移動
させ、半導体ウエハを上記基準ピンの位置に位置
合わせするように考慮したものである。
In the present invention, an air nozzle installed on an inclined alignment table transports a floating semiconductor wafer to a rotor and a reference plate to bring them into close contact with each other, and then the rotor rotates the semiconductor wafer to remove a notch. In order to align the semiconductor wafer with the reference plate and transfer it from that position to the reference pin position while maintaining the direction of the notch, vacuum suction with a vacuum chuck and vacuum release are performed intermittently. This method is designed to slowly move the semiconductor wafer on an inclined alignment surface to align the semiconductor wafer with the reference pins.

〔実施例〕〔Example〕

第1図は本発明の実施例を説明するための斜視
図である。
FIG. 1 is a perspective view for explaining an embodiment of the present invention.

傾斜したアライメント板11があり、その表面
を半導体ウエハ3が搬送されるためのガイド12
があり、厚みが約0.6mmの半導体ウエハ3がアラ
イメント板11で最終的に位置決めされる三個の
基準ピン13,14,15が植設されている。
There is an inclined alignment plate 11, and a guide 12 on the surface of which the semiconductor wafer 3 is transported.
There are three reference pins 13, 14, and 15 implanted with which the semiconductor wafer 3 having a thickness of about 0.6 mm is finally positioned by the alignment plate 11.

アライメント台11上には、孔径0.5mm程度で
圧力が3Kg/cm2の空気を噴射する複数の空気ノズ
ル孔16が所定の間隔で複数列に配列され、その
空気ノズルの傾斜欠くはアライメント台の面に対
し約30度〜45度の傾斜を有している。
On the alignment table 11, a plurality of air nozzle holes 16 that eject air with a hole diameter of about 0.5 mm and a pressure of 3 kg/cm 2 are arranged in multiple rows at predetermined intervals. It has an inclination of approximately 30 to 45 degrees with respect to the surface.

又、直径が2〜3mmで真空の吸引圧力400Torr
程度の真空チヤツク17が基準ピンのほぼ中央部
に設けられている。
Also, the diameter is 2 to 3 mm and the vacuum suction pressure is 400 Torr.
A vacuum chuck 17 of approximately the same size is provided approximately at the center of the reference pin.

ロータ18は回転軸径が6mm程度であり、基準
ピン13,14に平行であり、且つ平行度の許容
範囲が1/1000mmである基準板19とは、同一のフ
レーム20に取りつけられ、このフレームは昇降
自在の機構21で作動する。
The rotor 18 has a rotating shaft diameter of about 6 mm, is parallel to the reference pins 13 and 14, and has a parallelism tolerance of 1/1000 mm.The rotor 18 is attached to the same frame 20, and is attached to the same frame 20. is operated by a mechanism 21 that can be raised and lowered.

O.F.検出装置22は最終的にO.F.部が正確に位
置合わせ状態をチエツクするための光学検出装置
である。
The OF detection device 22 is an optical detection device for finally checking the accurate alignment state of the OF section.

第2図は、半導体ウエハ3をロータ18の回転
により回転させて、半導体ウエハ3のO.F.部2を
基準板19に合致させることを説明するための模
式平面図であり、第3図は空気ノズルの断面図
で、d=0.5mm程度、α=30度〜45度である。
FIG. 2 is a schematic plan view for explaining how the semiconductor wafer 3 is rotated by the rotation of the rotor 18 to align the OF part 2 of the semiconductor wafer 3 with the reference plate 19, and FIG. 3 is a schematic plan view of the air nozzle. In this cross-sectional view, d=about 0.5 mm and α=30 degrees to 45 degrees.

第4図は真空チヤツクの断面図であつて、D=
2〜3mmである。
FIG. 4 is a cross-sectional view of the vacuum chuck, where D=
It is 2 to 3 mm.

第5図a〜第5図fは本発明の機能を説明する
ための模式断面図である。
FIGS. 5a to 5f are schematic sectional views for explaining the functions of the present invention.

第5図aで、アライメント台11があつて、そ
の表面に半導体ウエハ3が置かれ、この半導体ウ
エハ3は空気ノズル16から噴射する矢印の空気
圧pによつて浮揚し、通常アライメント台11か
ら0.3〜0.5mm程度の高さに浮揚して矢印の方向に
移動する。
In FIG. 5a, an alignment table 11 is placed on the surface of which a semiconductor wafer 3 is placed, and this semiconductor wafer 3 is levitated by the air pressure p as indicated by the arrow ejected from an air nozzle 16, and is normally 0.3 m above the alignment table 11. It levitates to a height of ~0.5mm and moves in the direction of the arrow.

第5図(b)は、移動した半導体ウエハが、ロータ
18と基準板19とを備えたフレーム20によつ
て回転され、O.F.部が検出されて半導体ウエハの
O.F.部の方向が決定された状態である。
FIG. 5(b) shows that the moved semiconductor wafer is rotated by the frame 20 equipped with the rotor 18 and the reference plate 19, and the OF part is detected and the semiconductor wafer is rotated.
This is a state in which the direction of the OF section has been determined.

第5図cは、半導体ウエハが真空チヤツク17
の真空圧Pによつて吸着されて固定されると同時
にフレーム20が矢印のように上部に移動して除
去された状態である。
FIG. 5c shows that the semiconductor wafer is placed in the vacuum chuck 17.
At the same time, the frame 20 is moved upward as shown by the arrow and removed.

第5図dは、O.F.部の方向が決められた半導体
ウエハを徐々に基準ピン13,14,15に近接
させるために、一旦真空チヤツク17を真空から
開放した状態であり、半導体ウエハはアライメン
ト台の傾斜と空気ノズルの浮揚力により、基準ピ
ンの位置に僅かに近接する。
FIG. 5d shows a state in which the vacuum chuck 17 is temporarily released from the vacuum in order to gradually bring the semiconductor wafer, whose direction of the OF part has been determined, closer to the reference pins 13, 14, 15, and the semiconductor wafer is placed on the alignment table. Due to the inclination of the plane and the buoyancy force of the air nozzle, the position of the reference pin is slightly approached.

第5図eは、再度半導体ウエハを真空チヤツク
17の真空圧Pによつて吸着されて固定しり状態
である。
In FIG. 5e, the semiconductor wafer is once again attracted and fixed by the vacuum pressure P of the vacuum chuck 17.

第5図fは、このようにO.F.の位置出しがなさ
れた半導体ウエハを真空チヤツク17の間欠的な
作動により、徐々に基準ピン13,14,15に
近接させて最後に半導体ウエハをアライメント台
の基準ピンの位置に当接させた状態である。
FIG. 5f shows that the semiconductor wafer whose OF position has been positioned in this way is gradually moved closer to the reference pins 13, 14, 15 by intermittent operation of the vacuum chuck 17, and finally the semiconductor wafer is placed on the alignment table. It is in a state where it is brought into contact with the position of the reference pin.

このような操作により、半導体ウエハの位置合
わせが容易に且つ正確に行うことができる。
Through such operations, the semiconductor wafer can be easily and accurately aligned.

〔発明の効果〕〔Effect of the invention〕

以上詳細に説明したように本発明は簡単な装置
で、切欠部を有するウエハの位置合わせが容易に
できることができ効果大なるものがある。
As described in detail above, the present invention is a simple device that can easily align a wafer having a notch, which is highly effective.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の板状体の位置合わせを説明す
るための斜視図、第2図は半導体ウエハのO.F.部
を基準板に合致させる模式平面図、第3図は空気
ノズルの断面図、第4図は真空チヤツクの断面
図、第5図a〜第5図fは本発明の機能を説明す
るための模式断面図、第6図は従来の半導体ウエ
ハのO.F.と基準ピンの位置決めをするための機構
を示す斜視図である。 図において、3は半導体ウエハ、11はアライ
メント板、12はガイド、13,14,15は基
準ピン、16は空気ノズル孔、17は真空チヤツ
ク、18はロータ、19は基準板、20はフレー
ム、21は昇降自在機構、22はO.F.検出装置で
ある。
FIG. 1 is a perspective view for explaining the alignment of the plate-shaped body of the present invention, FIG. 2 is a schematic plan view of aligning the OF part of the semiconductor wafer with the reference plate, and FIG. 3 is a cross-sectional view of the air nozzle. Figure 4 is a cross-sectional view of the vacuum chuck, Figures 5a to 5f are schematic cross-sectional views for explaining the functions of the present invention, and Figure 6 is the conventional positioning of the OF of a semiconductor wafer and the reference pin. It is a perspective view showing a mechanism for this. In the figure, 3 is a semiconductor wafer, 11 is an alignment plate, 12 is a guide, 13, 14, 15 are reference pins, 16 is an air nozzle hole, 17 is a vacuum chuck, 18 is a rotor, 19 is a reference plate, 20 is a frame, 21 is a mechanism that can be raised and lowered, and 22 is an OF detection device.

Claims (1)

【特許請求の範囲】[Claims] 1 空気ノズルと真空チヤツクとロータと基準板
と基準ピンとを具備した傾斜したアライメント台
上で、一側部に切欠き部を有するウエハを空気ノ
ズルにより浮揚してロータ部に搬送し、該板状体
を該ロータで回転させて該切欠き部を基準板に合
致させた後、該ロータと該基準板を一旦除去し
て、上記真空チヤツクによつて浮揚状態の該板状
体をアライメント台上で真空吸着と真空から開放
動作を間欠的に行つて緩慢に移動させ、該ウエハ
を上記基準ピンの位置に配置したことを特徴とす
るウエハの位置合わせ方法。
1. On an inclined alignment table equipped with an air nozzle, a vacuum chuck, a rotor, a reference plate, and a reference pin, a wafer having a notch on one side is levitated by the air nozzle and transferred to the rotor, and the plate-like After the body is rotated by the rotor so that the notch matches the reference plate, the rotor and the reference plate are once removed, and the plate-like body, which is suspended by the vacuum chuck, is placed on the alignment table. A method for aligning a wafer, characterized in that the wafer is moved slowly by intermittently performing vacuum suction and vacuum releasing operations, and the wafer is placed at the position of the reference pin.
JP18204384A 1984-08-30 1984-08-30 Alignment of wafer Granted JPS6159745A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18204384A JPS6159745A (en) 1984-08-30 1984-08-30 Alignment of wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18204384A JPS6159745A (en) 1984-08-30 1984-08-30 Alignment of wafer

Publications (2)

Publication Number Publication Date
JPS6159745A JPS6159745A (en) 1986-03-27
JPH0158658B2 true JPH0158658B2 (en) 1989-12-13

Family

ID=16111341

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18204384A Granted JPS6159745A (en) 1984-08-30 1984-08-30 Alignment of wafer

Country Status (1)

Country Link
JP (1) JPS6159745A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023052839A1 (en) 2021-09-30 2023-04-06 Raiz - Instituto De Investigação Da Floresta E Papel Chromogenic copolymer, method of producing the same, products incorporating the same and method for detecting counterfeiting and for products authentication

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100915835B1 (en) * 2006-09-05 2009-09-07 라인시스템(주) Automatic Printing Arrangement and Method of Screen Printing Equipment

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023052839A1 (en) 2021-09-30 2023-04-06 Raiz - Instituto De Investigação Da Floresta E Papel Chromogenic copolymer, method of producing the same, products incorporating the same and method for detecting counterfeiting and for products authentication

Also Published As

Publication number Publication date
JPS6159745A (en) 1986-03-27

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