JPH0158659B2 - - Google Patents
Info
- Publication number
- JPH0158659B2 JPH0158659B2 JP59188403A JP18840384A JPH0158659B2 JP H0158659 B2 JPH0158659 B2 JP H0158659B2 JP 59188403 A JP59188403 A JP 59188403A JP 18840384 A JP18840384 A JP 18840384A JP H0158659 B2 JPH0158659 B2 JP H0158659B2
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- semiconductor layer
- forming
- alignment pattern
- epitaxial
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/01—Manufacture or treatment
Landscapes
- Element Separation (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は半導体装置の製造方法、特に素子分
離技術に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and in particular to an element isolation technique.
従来半導体装置の有効な素子分離技術として、
シリコン基板上の所定の領域にシリコン酸化膜等
の絶縁膜を形成した後、選択的エピタキシヤル成
長法を用いて露出した基板上に半導体層を形成し
活性領域とするものがあるが、絶縁膜との界面近
傍に格子欠陥が生じることから、この領域を活性
領域として使用するのを避けるために、さらに選
択酸化法を用いる方法が考えられる。
As an effective element isolation technology for conventional semiconductor devices,
After forming an insulating film such as a silicon oxide film in a predetermined area on a silicon substrate, a semiconductor layer is formed on the exposed substrate using a selective epitaxial growth method to form an active region. Since lattice defects occur near the interface with the oxide, a method using selective oxidation may be considered in order to avoid using this region as an active region.
第2図にこのような素子分離法の一例を示す。
同図において、はじめにシリコン基板1の主表面
上に酸化シリコン(SiO2)や窒化シリコン
(Si3N4)などからなる絶縁膜2を形成した後、
これを写真蝕刻法などにより選択的に除去して開
口部3を形成し、その部分のシリコン基板1を露
出させる(第2図a)。次に残つた絶縁膜2をマ
スクにして上記開口部3内に半導体層4をエピタ
キシヤル成長させる。このとき、半導体層4は絶
縁膜2の厚さより厚くして絶縁膜2を覆うように
形成する(第2図b)。次いで半導体層4上に窒
化シリコン膜5を形成し、写真蝕刻法などにより
半導体装置の素子の活性領域に対応する部分上に
窒化シリコン膜5が残るようにする(第2図c)。
次に、これをマスクとして半導体層4に選択酸化
を施し、絶縁膜2と接するようにフイールド酸化
膜6を形成した後、窒化シリコン膜5を除去する
(第2図d)。 FIG. 2 shows an example of such an element isolation method.
In the figure, after first forming an insulating film 2 made of silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), etc. on the main surface of a silicon substrate 1,
This is selectively removed by photolithography or the like to form an opening 3 and expose that portion of the silicon substrate 1 (FIG. 2a). Next, a semiconductor layer 4 is epitaxially grown in the opening 3 using the remaining insulating film 2 as a mask. At this time, the semiconductor layer 4 is formed to be thicker than the insulating film 2 so as to cover the insulating film 2 (FIG. 2b). Next, a silicon nitride film 5 is formed on the semiconductor layer 4, and the silicon nitride film 5 is left on the portion corresponding to the active region of the semiconductor device by photolithography or the like (FIG. 2c).
Next, using this as a mask, selective oxidation is performed on the semiconductor layer 4 to form a field oxide film 6 in contact with the insulating film 2, and then the silicon nitride film 5 is removed (FIG. 2d).
この結果、絶縁膜2とフイールド酸化膜6とに
よつて物理的に分離されたエピタキシヤル半導体
層4からなる活性領域が形成され、しかも絶縁膜
2との界面近傍の欠陥が生ずる領域はフイールド
酸化膜6の存在によつて活性領域から排除される
ため、良好な半導体装置の素子分離が可能にな
る。 As a result, an active region consisting of the epitaxial semiconductor layer 4 that is physically separated by the insulating film 2 and the field oxide film 6 is formed, and the region where defects occur near the interface with the insulating film 2 is formed by the field oxide film 6. Due to the presence of the film 6, it is excluded from the active region, so that good element isolation of the semiconductor device is possible.
ところが、この方法において、上述したように
エピタキシヤル半導体層4を、絶縁膜2を覆うよ
うに成長させると、次の窒化シリコン膜5を写真
蝕刻する工程で下地の絶縁膜2の形状が見えにく
くなるために、マスク合せが困難となる問題があ
つた。
However, in this method, when the epitaxial semiconductor layer 4 is grown to cover the insulating film 2 as described above, the shape of the underlying insulating film 2 becomes difficult to see in the next step of photo-etching the silicon nitride film 5. Therefore, there was a problem that it was difficult to match the masks.
この発明はこのような問題点を解決するために
なされたもので、その目的は、所定の領域に第1
の絶縁膜を形成した後にエピタキシヤル成長法お
よび選択酸化法を用いて素子分離を行なう際に、
エピタキシヤル層を第1の絶縁膜より厚く形成す
る場合でも選択酸化用のマスク合せが容易に行な
える、半導体装置の製造方法を提供することにあ
る。 This invention was made to solve these problems, and its purpose is to
When performing element isolation using epitaxial growth and selective oxidation after forming an insulating film,
It is an object of the present invention to provide a method for manufacturing a semiconductor device in which mask alignment for selective oxidation can be easily performed even when an epitaxial layer is formed thicker than a first insulating film.
このような目的を達成するために、この発明
は、第1の絶縁膜を形成する際に、素子分離用に
対し位置合せ用パターン部の絶縁膜の幅を広く形
成するものである。
In order to achieve such an object, in the present invention, when forming the first insulating film, the width of the insulating film in the alignment pattern portion is made wider than that for element isolation.
位置合せパターン部の第1の絶縁膜を幅広く形
成しておくことにより、素子分離用の第1の絶縁
膜がエピタキシヤル半導体層によつて完全に覆わ
れた時点でも位置合せパターン部のそれは残るた
め、それを基準としてマスク合せが行なえる。
By forming the first insulating film in the alignment pattern part to be wide, even when the first insulating film for element isolation is completely covered with the epitaxial semiconductor layer, it remains in the alignment pattern part. Therefore, mask matching can be performed using this as a reference.
第1図はこの発明の一実施例を示す工程断面図
である。図中破断線より左側は半導体素子が形成
される領域で、右側は位置合せ用のパターンが形
成される領域を示す。また、同図a,b,cはそ
れぞれ第2図a,b,dと同じ段階に相当する。
FIG. 1 is a process sectional view showing an embodiment of the present invention. In the figure, the left side of the broken line is a region where a semiconductor element is formed, and the right side is a region where an alignment pattern is formed. Further, a, b, and c in the figure correspond to the same stages as a, b, and d in FIG. 2, respectively.
第1図において、はじめにシリコン基板1の主
表面上に酸化シリコンや窒化シリコン等からなる
絶縁膜を形成し、写真蝕刻法などにより開口部3
を形成する際に、図中左側の素子分離用の絶縁膜
2の幅D1に比較して、位置合せ用パターン部の
絶縁膜2Aの幅D2が広くなるようにする(第1
図a)。 In FIG. 1, an insulating film made of silicon oxide, silicon nitride, etc. is first formed on the main surface of a silicon substrate 1, and an opening 3 is formed by photolithography or the like.
, the width D2 of the insulating film 2A in the alignment pattern section is made wider than the width D1 of the insulating film 2 for element isolation on the left side in the figure (first
Diagram a).
これにより、次にエピタキシヤル成長法により
半導体層4を形成した際に、素子分離用の絶縁膜
2が半導体層4によつて完全に覆われても、位置
合せ用パターン部の絶縁膜2Aは覆われずにその
表面が露出するようにすることができる(第1図
b)。これは、絶縁膜2ないし2A上の半導体層
4は、開口部3で当該絶縁膜より厚く成長する半
導体層4の横方向の成長により形成されるもので
あるため、幅の狭い素子分離間の絶縁膜2が半導
体層4に完全に覆われた時点でも幅の広い位置合
せ用パターン部の絶縁膜2Aは完全には覆われる
ことがないからである。 As a result, when the semiconductor layer 4 is next formed by the epitaxial growth method, even if the insulating film 2 for element isolation is completely covered with the semiconductor layer 4, the insulating film 2A in the alignment pattern part will be It can be uncovered so that its surface is exposed (FIG. 1b). This is because the semiconductor layer 4 on the insulating film 2 or 2A is formed by the lateral growth of the semiconductor layer 4, which grows thicker than the insulating film in the opening 3. This is because even when the insulating film 2 is completely covered with the semiconductor layer 4, the insulating film 2A in the wide alignment pattern portion is not completely covered.
したがつて、素子分離用の絶縁膜2の幅を十分
挾く、例えば2μm以下程度に形成し、位置合せ
用パターン部の絶縁膜2Aの幅を十分広く、例え
ば10μm以上程度に形成し、絶縁膜2がエピタキ
シヤル半導体層4に覆われた時点でエピタキシヤ
ル成長を止めれば、絶縁膜2Aはまだ露出してい
るために、次工程の写真蝕刻法等のマスク合せが
容易になる。 Therefore, the width of the insulating film 2 for element isolation is formed sufficiently wide, for example, about 2 μm or less, and the width of the insulating film 2A of the alignment pattern part is formed sufficiently wide, for example, about 10 μm or more. If the epitaxial growth is stopped when the film 2 is covered with the epitaxial semiconductor layer 4, the insulating film 2A is still exposed, which facilitates mask alignment in the next step, such as photolithography.
そこで、図上省略したが露出した絶縁膜4Aを
基準に、前述したと同様に位置合せしたマスクを
用い、写真蝕刻法等により第2図に示した窒化シ
リコン膜5を形成した後、これをマスクとして選
択酸化を行なつてフイールド酸化膜6を形成し、
次いで窒化シリコン膜5を除去すれば、前述した
と同様に絶縁膜2とフイールド酸化膜6とによつ
て分離されたエピタキシヤル半導体層4からなる
活性領域が形成できる(第1図c)。 Therefore, although not shown in the figure, the silicon nitride film 5 shown in FIG. 2 was formed by photolithography using a mask aligned in the same manner as described above, using the exposed insulating film 4A as a reference. A field oxide film 6 is formed by performing selective oxidation as a mask,
Then, by removing the silicon nitride film 5, an active region consisting of the epitaxial semiconductor layer 4 separated by the insulating film 2 and the field oxide film 6 can be formed as described above (FIG. 1c).
絶縁膜2Aの幅は、位置合せ用パターンとして
用いるという上記の目的からは十分広いことが望
ましいが、発明者らの実験によれば、この絶縁膜
2Aの幅を500μm以上にすると、当該絶縁膜上
でシリコンが異常成長することがあり、それを防
ぐためには500μm以下であることが望ましい。 It is desirable that the width of the insulating film 2A is sufficiently wide for the above-mentioned purpose of using it as an alignment pattern, but according to experiments by the inventors, when the width of the insulating film 2A is set to 500 μm or more, the width of the insulating film 2A is Silicon may grow abnormally on the surface, and to prevent this, the thickness is preferably 500 μm or less.
このような本発明による方法は、シリコン基板
を用いた各種の半導体装置を形成する際に、前提
となる素子分離技術として共通に使用することが
できる。なお、基板およびエピタキシヤル半導体
層の導電形については特に触れなかつたが、これ
は、本発明がこれらの導電形には一切無関係に適
用できるためであり、両者の導電形はP形でもN
形でも、相互に同一でも異なつていてもよい。 Such a method according to the present invention can be commonly used as a prerequisite element isolation technique when forming various semiconductor devices using a silicon substrate. Note that the conductivity types of the substrate and the epitaxial semiconductor layer have not been specifically mentioned because the present invention can be applied regardless of these conductivity types, and the conductivity types of both may be P type or N type.
They may be the same or different in shape.
以上説明したように、この発明によれば、第1
の絶縁膜を形成する際に、素子分離用に対し位置
合せパターン部の幅を広く形成することにより、
開口部にエピタキシヤル成長法を用いて半導体層
を形成する際に位置合せパターン部の第1の絶縁
膜は当該エピタキシヤル半導体層によつて埋め込
まれないようにし、その露出した第1の絶縁膜を
基準として容易にマスク合せを行なうことがで
き、選択酸化法により第1の絶縁膜上にフイール
ド絶縁膜を精度良く形成することが可能となる。
As explained above, according to the present invention, the first
When forming the insulating film of
When forming a semiconductor layer in the opening using an epitaxial growth method, the first insulating film in the alignment pattern portion is not buried by the epitaxial semiconductor layer, and the exposed first insulating film is Mask alignment can be easily carried out based on the reference, and a field insulating film can be formed with high precision on the first insulating film by selective oxidation.
第1図は本発明の一実施例を示す工程断面図、
第2図は選択エピタキシヤル法および選択酸化法
を用いた従来の素子分離法を示す工程断面図であ
る。
1……シリコン基板、2,2A……絶縁膜(第
1の絶縁膜)、3……開口部、4……エピタキシ
ヤル半導体層、5……選択酸化用のマスクとして
の窒化シリコン膜、6……フイールド酸化膜(第
2の絶縁膜)。
FIG. 1 is a process sectional view showing an embodiment of the present invention;
FIG. 2 is a process sectional view showing a conventional element isolation method using selective epitaxial method and selective oxidation method. DESCRIPTION OF SYMBOLS 1... Silicon substrate, 2, 2A... Insulating film (first insulating film), 3... Opening, 4... Epitaxial semiconductor layer, 5... Silicon nitride film as a mask for selective oxidation, 6 ...Field oxide film (second insulating film).
Claims (1)
する工程と、この第1の絶縁膜を選択的にエツチ
ングして半導体基板が露出した開口部を形成する
工程と、開口部にエピタキシヤル成長法により半
導体層を形成する工程と、形成したエピタキシヤ
ル半導体層に選択酸化法を適用することにより第
1の絶縁膜上に第2の絶縁膜を形成する工程とを
含み、上記開口部を形成する際に当該開口部間に
残す第1の絶縁膜のうち半導体素子分離用の第1
の絶縁膜に対して位置合せパターン部の第1の絶
縁膜の幅を広くし、かつエピタキシヤル成長法に
より半導体層を形成する際に位置合せパターン部
の第1の絶縁膜は当該エピタキシヤル半導体層に
よつて埋め込まれないようにすることを特徴とす
る半導体装置の製造方法。1. A step of forming a first insulating film on the main surface of a semiconductor substrate, a step of selectively etching this first insulating film to form an opening through which the semiconductor substrate is exposed, and etching an epitaxial layer in the opening. The method includes a step of forming a semiconductor layer by a growth method, and a step of forming a second insulating film on the first insulating film by applying a selective oxidation method to the formed epitaxial semiconductor layer, and forming the second insulating film on the first insulating film. Of the first insulating film left between the openings during formation, the first insulating film for semiconductor element isolation is
The width of the first insulating film in the alignment pattern part is made wider than the insulating film in the alignment pattern part, and when forming a semiconductor layer by an epitaxial growth method, the first insulating film in the alignment pattern part is made wider than the width of the first insulating film in the alignment pattern part. A method for manufacturing a semiconductor device, characterized in that it is prevented from being buried by layers.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59188403A JPS6165448A (en) | 1984-09-07 | 1984-09-07 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59188403A JPS6165448A (en) | 1984-09-07 | 1984-09-07 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6165448A JPS6165448A (en) | 1986-04-04 |
| JPH0158659B2 true JPH0158659B2 (en) | 1989-12-13 |
Family
ID=16223033
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59188403A Granted JPS6165448A (en) | 1984-09-07 | 1984-09-07 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6165448A (en) |
-
1984
- 1984-09-07 JP JP59188403A patent/JPS6165448A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6165448A (en) | 1986-04-04 |
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