JPH0158699B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a multiplex conversion device for time-division multiplexing digital transmission using a staff synchronization method. Concerning a faster staff synchronization method.

A staff synchronization method is generally used when multiplexing a plurality of asynchronous digital signals to transmit a single signal with a high frequency.

FIG. 1 shows a block diagram of a conventional staff-type digital multiplex converter, where A is a transmitter and B is a transmitter.
indicates the receiving section.

In the figure, 1 and 2 are transmission channel sections, and 3 and 14 are bipolar/unipolar conversion sections (hereinafter referred to as B/U
CONV), 4 and 22 are buffer memories,
5 and 15 are timing extractors, 6 is a phase comparator,
7 is a multiplexing section, 8 is a staff control circuit (judgement control circuit), 9 is a multiplexing section, 1
0 is the main oscillator, 11 is the transmitting side clock generation circuit,
12 and 24 are unipolar/bipolar converters (hereinafter referred to as U/B CONV), 16 is a receiving side clock generation circuit, 17 is a frame synchronization circuit, 18 is a separation unit, 19 is a destaft control circuit, and 20 and 21 are reception channels. 23 is a phase synchronized oscillation circuit.

In operation, the input low-order group signal of the bipolar code input from the SIN of each transmission channel section is sent to the B/U.
CONV3 converts the signal into a unipolar code, and the timing extractor 5 extracts a timing pulse from this signal and writes it into the buffer memory 4. On the other hand, a synchronization signal frequency that is slightly higher than the input low-order group frequency is inputted from the transmitting side clock generator 11 to the staff control circuit 8, and the pulses generated by the synchronization signal frequency are used to control the signal written in the buffer memory 4 as described above. Read it. At this time, by inserting a stuff pulse, the frequency deviation of multiplexing in the multiplexer 9 is absorbed. At this time, information as to whether a stuff pulse is inserted or not is separately superimposed on the multiplexed signal as a staff designation pulse. Further, frame pulses and various service pulses for synchronization on the receiving side are also superimposed on the multiplexed signal. The multiplexed signals sent from each of the transmission channel sections 1, 2, etc. are multiplexed by the multiplexing section 9, and the U/B
CONV12 converts it into a bipolar code and sends it to the receiving side. On the receiving side, B/U CONV14
The receiving side clock generation circuit 16 is operated with the timing pulse converted into a unipolar code and extracted by the timing extraction circuit 15.The frame synchronization circuit 17 synchronizes the transmitted signal, and the separation unit 18 outputs signals for each channel. separated into On the other hand, the staff designation pulse is detected and the staff pulse is separated from the signal. After being separated into each channel by the separation unit 18, it is written to the buffer memory 22, but where stuff pulses, stuff designation pulses, frame pulses, etc. are inserted, they are removed by prohibiting the write clock by the de-staff control circuit 19. is going on. The signal written in the buffer memory 22 is read out as a low-order group original signal by the read clock generated by the voltage controlled oscillator in the phase synchronized oscillation circuit 23, and is converted into a bipolar code by the U/B CONV 24. The signal is sent from the ROUT of each receiving channel section. At this time, the phase comparison circuit in the phase synchronization circuit 23 compares the phase of the clock with the clock corresponding to the stuff pulse inhibited and the readout clock, and a smoothed control voltage proportional to the comparison value is sent to the voltage controlled oscillator. The readout clock is made to follow the frequency of the input low-order group signal on the transmitting side. But the sender's SIN
If the frequency of the input low-order group signal is significantly shifted for some reason, the staff designated pulse will continuously indicate the insertion state or non-insertion state, and all staff pulse insertion possible locations will be in the all staff state. Or it becomes all non-staff state,
On the receiving side, the voltage controlled oscillator of the phase synchronized oscillation circuit 23 remains out of the pull-in range. In this state, even if the input low-order group signal from the SIN on the transmitting side returns to its normal frequency, it takes time for the voltage controlled oscillator to pull in.
The disadvantage is that it takes time for the output signal from ROUT to return to normal.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a staff synchronization system that speeds up the pull-in time of a voltage controlled oscillator when the input low-order group signal frequency shifts significantly and returns again.

In order to achieve the above object, the present invention is directed to a digital multiplex converter using a staff synchronization method, when a continuous state of insertion or non-insertion of staff designation pulses that become all staff or all non-staff is detected on the receiving side. By prohibiting the sending of the write clock to the phase comparison circuit of the phase synchronized oscillation circuit, the read clock is output as is from the phase comparison circuit, the voltage controlled oscillator is locked to the center frequency, and the low-order input to the transmitting side is It is characterized in that the voltage controlled oscillator can be pulled in quickly when the group signal frequency is restored.

An embodiment of the present invention will be described below with reference to the drawings. FIG. 2 is a block diagram of a staff-type digital multiplex converter according to an embodiment of the present invention, in which A is a transmitting section and B is a receiving section. FIG. 3 is a block diagram of a known phase-locked oscillator circuit.

Components in the figure that have the same functions as those in FIG. 1 are indicated by the same symbols. 25 is an all-staff and all-nonstaff detection circuit, 26 is a phase comparator circuit, 27 is a low frequency amplifier, 28 is an amplifier, and 29 is a voltage controlled oscillator.

The only difference in FIG. 2 from FIG. 1 is that an all-staff/all-nonstaff detection circuit 25 is provided in the separation section 13 of the receiving section shown in (B). The normal operation is therefore the same as described above. Now in the transmitting section
If the frequency of the input low-order group signal from the SIN deviates significantly for some reason, all locations where stuff pulses can be inserted become all stuff or all non-stuff states, as explained above. The signal in this state is detected by the all-staff/all-non-staff detection circuit 25 on the receiving side via the de-staff control circuit 19, and an inhibit signal is sent to the de-staff control circuit which is input to the phase comparator circuit 26 in FIG. The write clock from No. 19 (WCLK in FIG. 3) is prohibited. As a result, the control voltage from the phase comparator circuit 26 in FIG.
The voltage controlled oscillator 29 is then locked to the center frequency. When the frequency of the input low-order group signal from the SIN of the transmitting section returns to its original state, it will be in a normal state, so the all-staff/all-non-staff detection circuit 25 will not operate, and the write clock from the de-staff control circuit 19 will not operate. The inhibition is removed and the write clock is input to the phase comparator circuit 26. However, since the voltage controlled oscillator 29 operates at a center frequency that is almost the same as that of the write clock, it immediately pulls in the write clock, follows the input low-order group frequency on the transmitting side, and immediately returns to the normal state.

As described in detail above, according to the present invention, even if the input low-order group signal frequency on the transmitting side deviates significantly for some reason and returns to normal, it immediately returns to normal and has the effect of greatly shortening the time during which communication is interrupted.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional staff type digital multiplex converter, FIG. 2 is a block diagram of a staff type digital multiplex converter according to an embodiment of the present invention, and FIG. 3 is a block diagram of a phase locked circuit. be. In the figure, 1 and 2 are transmission channel sections, 3 and 14 are B/U CONV, 4 and 22 are buffer memories,
5 and 15 are timing extractors, 6 is a phase comparator,
7 is a multiplexing section, 8 is a staff control circuit, 9 is a multiplexing section, 10 is a main oscillator, 11 is a transmitting side clock generating circuit, 12 and 24 are B/U CONVs, 16 is a receiving side clock generating circuit, and 17 is a receiving side clock generating circuit. Frame synchronization circuit, 3 and 18 are separation sections, 19 is a destaff control circuit, 20 and 21 are reception channel sections, 23 is a phase synchronization oscillation circuit, 25 is an all staff/all non staff detection circuit, 26 is a phase comparison circuit, 27
28 is an amplifier, and 29 is a voltage controlled oscillator.

Claims (1)

[Scope of Claims] 1. A receiving side multiplex conversion device for time division multiplexing digital transmission using a staff synchronization method, which detects frame synchronization of a received signal, separates the signal into each channel, and performs staff synchronization for each channel. When detecting the presence or absence of pulse insertion and writing the separated signal to the buffer of each channel using a write clock synchronized with the separated signal, if a stuff pulse is inserted, the write clock corresponding to the stuff pulse is disabled. By doing so, the signal written in the buffer is read out by the clock generated by the phase synchronized oscillator, which receives as input the clock in which the write clock corresponding to the stuff pulse is invalidated. In the multiplex conversion device for receiving output of the channel, when detecting the presence or absence of stuff pulse insertion for each channel, means is provided for detecting a continuous state of the stuff pulse insertion state or the non-stuff pulse insertion state; A staff synchronization method characterized in that when a state is detected, sending out a write clock to the phase synchronization oscillation circuit is prohibited.