JPH0158700B2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a multiplex conversion device for time division multiplexing digital transmission using a staff synchronization method, and when synchronization is lost on the receiving side and synchronization is restored again, the phase locked oscillation circuit (PLL, Phase Lock Loop) is activated. This invention relates to a staff synchronization method that speeds up the pull-in time.

A staff synchronization method is generally used when multiplexing a plurality of asynchronous digital signals to transmit a single signal with a high frequency.

FIG. 1 shows a block diagram of a conventional digital multiplex converter using a staff synchronization method, where A indicates a transmitting section and B indicates a receiving section.

In the figure, 1 and 2 are transmission channel sections, and 3 and 14 are bipolar/unipolar conversion sections (hereinafter referred to as B/V
CONV), 4 and 22 are buffer memories,
5 and 15 are timing extractors, 6 is a phase comparator,
7 is a multiplexing section, 8 is a staff control circuit (judgement control circuit), 9 is a multiplexing section, 1
0 is a main oscillator, 11 is a transmitting side clock generating circuit, 12 and 24 are unipolar/bipolar converters (hereinafter referred to as U/B CONV), 16 is a receiving side clock generating circuit, 17 is a frame synchronizing circuit, 1
3 and 18 are separation sections, 19 is a destaph control circuit,
20 and 21 are reception channel sections, 23 is a phase synchronized oscillation circuit, and 25 is an AIS signal generator.

In operation, the input low-order group signal of the bipolar code input from the SIN of each transmission channel section is
Convert to unipolar code with U CONV3,
The timing pulse extracted from this signal by the timing extractor 5 is written into the buffer memory 4. On the other hand, a synchronization signal frequency that is slightly higher than the input low-order group frequency is inputted from the transmitting side clock generator 11 to the staff control circuit 8, and the pulses generated by the synchronization signal frequency are used to control the signal written in the buffer memory 4 as described above. Read it. At this time, by inserting a stuff pulse, the frequency deviation of multiplexing in the multiplexer 9 is absorbed. At this time, information as to whether or not a stuff pulse is inserted is separately superimposed on the multiplexed signal as a staff designation pulse. Further, frame pulses and various service pulses for synchronization on the receiving side are also superimposed on the multiplexed signal. The multiplexed signals sent from each of the transmission channel sections 1, 2, etc. are multiplexed by the multiplexing section 9, and the U/B
CONV12 converts it into a bipolar code and sends it to the receiving side. On the receiving side, B/U CONV1
4, the timing pulse is converted into a unipolar code, and the timing pulse extracted by the timing extraction circuit 15 operates the receiving side clock generation circuit 16. The frame synchronization circuit 17 synchronizes with the transmitted frame pulse and sends it to the separation unit 18. is separated into each channel. On the other hand, the staff designation pulse is detected and the staff pulse is separated from the signal. Separation part 1
After being separated into each channel at step 8, the signals are written to the buffer memory 22, but where stuff pulses, stuff designation pulses, frame pulses, etc. have been inserted, they are removed by prohibiting the write clock from the de-staff control circuit 19. It's on. The signal written in the buffer memory 22 is read out as a low-order group original signal by the read clock generated by the voltage controlled oscillator in the phase synchronized oscillation circuit 23, and is converted into a bipolar code by the U/B CONV 24. of each receiving channel.
Sent from ROUT. At this time, the phase comparison circuit in the phase synchronization circuit 23 compares the phase of the clock with the clock corresponding to the stuff pulse inhibited and the readout clock, and a smoothed control voltage proportional to the comparison value is applied to the voltage controlled oscillator. The readout clock is made to follow the frequency of the input low-order group signal on the transmitting side. However, if synchronization occurs in the receiving-side separation unit 13 for some reason, the signals will not be separated accurately and the frequency of the write clock from the de-staff control circuit 19 will change to the voltage-controlled oscillator in the phase-locked oscillator circuit 23. The vehicle will remain out of the pull-in range. In this state, even after synchronization is restored, it takes time for the voltage controlled oscillator to pull in.
The disadvantage is that it takes time for the output signal from ROUT to return to normal. Furthermore, when the separation unit 13 is out of synchronization, the AIS signal (alarm indication signal usually all "1") generator 25 detects it and sends the AIS signal to the lower order group to notify the out-of-synchronization. Generally speaking, when the voltage controlled oscillator in the phase-locked oscillator circuit 23 is out of the pull-in range, the frequency of the output signal to the lower order group of ROUT is also shifted, so the lower order group device The disadvantage is that the signal may not be received.

The purpose of the present invention is to eliminate the above drawbacks by locking the voltage controlled oscillator in the phase synchronized oscillator circuit to the center frequency when synchronization occurs on the receiving side.
To provide a staff synchronization system in which low-order group devices can receive an AIS signal, and when synchronization is restored again, a voltage controlled oscillator is immediately pulled in, and the communication state is immediately returned to normal.

In order to achieve the above object, the present invention prohibits the sending of write clocks to the phase comparator circuit of the phase synchronized oscillator circuit on the receiving side when synchronization occurs on the receiving side in a digital multiplex converter using a staff synchronization method. By doing so, the readout clock is output as is from the phase comparator circuit, the voltage controlled oscillator is locked to the center frequency, the low-order group device can receive the AIS signal via each channel, and when synchronization is restored again, it is quickly It is characterized by the ability to pull in the voltage controlled oscillator.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a block diagram of a staff-synchronized digital converter according to an embodiment of the present invention, in which (A) shows a transmitting section;
(B) is the receiving section, and FIG. 3 shows a block diagram of the phase-locked oscillator circuit.

Components in the figure that have the same functions as those in FIG. 1 are indicated by the same symbols. 17' is a frame synchronization circuit, 19' is a destapping control circuit, 26 is a phase comparison circuit, 27 is a wave reducer, 28 is an amplifier, and 29 is a voltage controlled oscillator.

The only difference in FIG. 2 from FIG. 1 is that an inhibiting function is provided between the frame synchronization circuit 17' and the destapping control circuit 19' of the receiving section shown in (B). The normal operation is therefore the same as described above. However, if a synchronization loss occurs in the separation section 13 of the receiving section, it is detected by the frame synchronization circuit 17', and the writing lock from the de-staff control circuit 19' is activated by the inhibit signal (see FIG. 2B).
WCLK} transmission is prohibited. As a result, the control voltage from the phase comparison circuit 26 in FIG. 3 becomes 0, and the voltage controlled oscillator 29 is locked to the center frequency. The AIS signal from the AIS signal generator 25 is read out using the clock at the center frequency and is transmitted to the low-order group device from the ROUT of each channel, so the low-order group device can reliably receive the AIS signal. It can be seen that a failure has occurred in the receiving section of the higher order group shown in B. Next, when the out-of-synchronization is restored, the frame synchronization circuit 17' detects this and releases the inhibition to the de-staff control circuit 19'. As a result, the write clock is sent to the phase comparison circuit 26 of the phase synchronized oscillation circuit 23. At this time, since the voltage controlled oscillator 29 is operating near the center frequency, it immediately pulls in the write lock and returns to the normal state, resulting in a normal communication state.

As explained in detail above, according to the present invention, even if an out-of-synchronization occurs on the receiving side, the low-order group device can reliably receive the AIS signal, and when the out-of-synchronization returns, it immediately returns to normal and communication is interrupted. This has the effect of significantly reducing time.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional staff-type digital multiplex converter, FIG. 2 is a block diagram of a staff-type digital multiplex converter according to an embodiment of the present invention, and FIG. 3 is a block diagram of a phase-locked oscillator circuit. It is. In the figure, 1 and 2 are transmission channel sections, 3 and 14 are B/U CONV, 4 and 22 are buffer memories,
5 and 15 are timing extractors, 6 is a phase comparator,
7 is a multiplexing section, 8 is a staff control circuit, 9 is a multiplexing section, 10 is a main oscillator, 11 is a transmitting side clock generating circuit, 12 and 24 are U/B CONVs, 16 is a receiving side clock generating circuit, 17, 17' is a frame synchronization circuit, 13 and 18 are separation units, and 19 and 19'
is a destatus control circuit, 20 and 21 are reception channel sections, 23 is a phase synchronized oscillator circuit, 25 is an AIS signal generator, 26 is a phase comparator circuit, 27 is a low frequency generator, 28 is an amplifier, and 29 is a voltage controlled oscillator. be.

Claims (1)

[Scope of Claims] 1. A receiving side multiplex conversion device for time division multiplexing digital transmission using a staff synchronization method, which detects frame synchronization of a received signal, separates the signal into each channel, and performs staff synchronization for each channel. When detecting the presence or absence of pulse insertion and writing the separated signal into the buffer of each channel using a write clock synchronized with the separated signal, if a stuff pulse is inserted, the write clock corresponding to the stuff pulse is invalidated. By doing this, the signal written in the buffer is read out by the generated clock of the phase synchronized oscillator circuit, which inputs the clock with the write clock corresponding to the stuff pulse invalidated. A staff synchronization method, characterized in that, in a multiplex conversion device for receiving output of the channel, when the frame synchronization detection becomes out of synchronization, sending out a write clock to the phase synchronization oscillation circuit is prohibited.