JPH0210455B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to instruction processing control in an information processing device, and particularly to a method for detecting register update wait information necessary for read start control of operands necessary for arithmetic operations. It is.

[Conventional technology]

Conventionally, this type of information processing device has attempted to improve the throughput of instruction processing by dividing instruction processing into multiple stages and configuring the instruction processing system in a so-called pipeline configuration, thereby overlapping the processing in each stage. . However, when the arithmetic processing phase of an instruction becomes complex, the number of stages in the arithmetic processing phase increases, and the time required to obtain the execution result of the instruction becomes extremely long. In conventional instruction processing, as a general rule, the arithmetic processing phase of the following instruction was started after waiting for the arithmetic result of the preceding instruction to be determined, so the instruction with a very long arithmetic processing phase as described above was executed. In this case, the start of arithmetic processing of subsequent instructions is forced to wait until the result is determined, resulting in a decrease in processing efficiency.

Therefore, when decoding an instruction, it is determined whether the operands required for the operation of the instruction are waiting to be updated by the operation of the preceding instruction, and if they are not waiting to be updated, the following instruction is executed without waiting for the completion of the preceding instruction. There is a system in which the above-mentioned decrease in efficiency is minimized by starting the arithmetic processing of . In this case, in the conventional information processing device, as shown in FIG. 2, there is a stack 53' for registering update waiting register numbers, and a register number holding means 55 for holding register numbers required by the instruction as the instruction is processed. ′
and a coincidence detecting means 54 for detecting a coincidence between the contents of the stack 53' and the contents of the register number holding means 55', and a register for starting the arithmetic processing of the instruction and storing the arithmetic result of the instruction. The register number is registered in the stack 53', and at the time when the result of the calculation is actually stored in the register, the register number registered in the stack 53' is invalidated, and prior to the start of the calculation process, the register number holding means 55' is The coincidence detecting means 54 compares the contents of the stack 53' and determines whether there is a match.
By checking with , it is determined whether an operand necessary for an operation is waiting to be updated by a preceding instruction.

[Problem that the invention seeks to solve]

However, in this type of information processing device, the number of registers for storing operation operands and operation results tends to increase, and in conventional information processing devices, the information held along with instruction processing is used for reading operands. Since it is a register number, there are disadvantages in that as the number of registers increases, the amount of hardware required to hold the register number increases, and the delay time of the update wait detection circuit increases.

[Means for solving problems]

An information processing device according to the present invention includes a register bank that can be read and written by instructions, a plurality of arithmetic units that can operate independently of each other, a data path that supplies operands from the register bank to the arithmetic units, and a register bank that can be read and written by instructions. The control unit includes a data path for transferring the operation results of the unit to the register bank, and a control unit that controls each of the above components, and the control unit controls the operation of the register bank by the preceding instruction to control the start of reading operands of the instruction. In an information processing device that monitors updates, the control unit determines that a register number of the register bank storing the operation result of the discontinued instruction and a register of the register bank specified by the register number are waiting for update by a preceding instruction. A stack that has multiple entries that register update wait instruction bit information indicating that there is an update, and a match check between the operand read register number specified by the instruction prior to reading the operand and the register number registered in each entry of the stack. matching entry detecting means for outputting a matching entry number; entry number holding means for holding the entry number detected by the matching entry detecting means as instruction processing progresses; By checking only the update wait instruction bit information registered in the entry of the stack specified by the entry number held in the holding means, it is possible to determine whether the register of the register bank in which the operand is stored is waiting for update. an update wait detecting means for detecting whether or not the operand is waiting; and a control means for causing the operand reading to wait until the update wait is released when the detection result from the update wait detecting means is that the update wait is canceled. Ru.

[Effect]

As described above, the information processing device of the present invention includes a stack having a plurality of entries in which the operation result storage register number and register update wait instruction bit information can be registered together, and the operation operand read register is registered at an early stage of instruction processing. By checking the match between the number and the register number registered in each entry in the stack above, the entry number in which the register number to be managed as an update waiting management target is registered is detected, and from then on, the corresponding register number is used instead of the register number. To manage the register update wait by rotating the entry number and checking only the update wait instruction bit information of the stack entry specified by the entry number at the time of starting the operation, and to perform faster instruction processing with a smaller amount of hardware. Can be done.

〔Example〕

Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing the configuration of an embodiment of an information processing apparatus according to the present invention.
In FIG. 1, the information processing apparatus of this embodiment includes a register bank 10 for storing arithmetic operands or results, a plurality of arithmetic units 20a, . , the arithmetic unit group 20a, 2
0b, a data path 30 that supplies the operands necessary for the operation to 0b, a data path 40 that transfers the operation results of the arithmetic unit groups 20a, . It consists of 50.

The control unit 50 includes an instruction register 51 that holds read instructions, an instruction decoding processing circuit 52 having a pipeline configuration that performs instruction decoding processing, and the register bank 1 that stores the calculation result of the instruction that is being processed.
The update waiting register management stack 53 is composed of a plurality of entries, including a field 53a for registering a register number of 0 and a field 53b for registering instruction bit information indicating that the register is waiting for an update, and an instruction register 51. A field 53a for registering the register number in which the operands necessary for the arithmetic processing are stored in the instruction being processed, and a field 53a for registering the register number in which the arithmetic result of the instruction being processed by the update waiting register management stack 53 is to be stored. a match detection circuit 54 that checks for a match with the above and outputs a matching entry number, and a shift register that rotates the entry number output from the match detection circuit 54 in correspondence to each stage of instruction processing. 5
5. Before starting the arithmetic processing, read the register update wait instruction bit information registered in the field 53b of the update wait register management stack 53 based on the contents of the corresponding stage of the shift register 55, and use this information to start the arithmetic processing. It is comprised of an arithmetic activation control circuit 56 that generates control signals that control the entire instruction processing including whether to activate or not.

Next, the operation of the present invention will be explained using a specific example.

When an instruction I O is set in the instruction register 51 that performs an operation using the contents of the registers specified by register numbers y _O and Z _O as operands, and stores _the result of the operation in the register specified by register number x _O. , Register management stack 5 waiting for update of register number x _O of the register that should store the operation result of this instruction
3 in the register number registration field 53a, it also checks whether the register numbers y _{O and} Z _O in which the operands used by the instruction I _O are stored are registered in the stack 53 by the preceding instruction. The match detection circuit 54 checks.

If no match is detected as a result, the instruction I _/O executes instruction decoding processing and operand reading to start arithmetic processing, and at the same time updates the register of the same entry as the entry that registered the register number of the register that should store the arithmetic result. Information "1" indicating that update is pending is set in the wait instruction bit information registration field 53b. This field is the instruction I _O
It is reset at the same time as storing the operation result in the register indicated by register number _xO .

On the other hand, if a match is detected by the match check, the entry number output from the match detection circuit 54 is set in the shift register 55, and is rotated as the instruction is processed. Reads the update wait instruction bit information specified by the entry number. As a result, if the read information is "0", this means that the register in which the operand used in the operation of the instruction is stored is not waiting for update. If the information is "1", it means that the register storing the operand used in the operation of the instruction is waiting for update, so the operation processing of the instruction is not started until the update wait is released. Control to wait.

In the present invention, the entry number of the update register management stack 53 is the information that is passed around during instruction processing for register update wait management, so the amount of hardware can be reduced compared to the conventional system in which register numbers themselves are passed around. Furthermore, in the present invention, when checking whether the register storing the operands necessary for the operation is waiting for update before starting the operation, it is sufficient to read 1 bit of information as described above.
The check result can be obtained with a shorter delay time than the conventional method of comparing register numbers.

〔Effect of the invention〕

As explained above, the present invention provides a stack for registering the operation result storage register number and update wait instruction bit information, and uses the entry number of the stack instead of the register number as the information that is passed around during instruction processing. This has the effect of enabling faster register update management with a smaller amount of hardware.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of an information processing apparatus according to the present invention, and FIG. 2 is a block diagram for explaining the prior art. DESCRIPTION OF SYMBOLS 10...Register bank, 20a, 20b...Arithmetic unit, 30...Operand supply data path, 40...Arithmetic result transfer data path, 50...Control unit, 51...Instruction register, 52...Instruction explanation processing circuit, 53...Update waiting register management Stack, 53a...Arithmetic result write register number registration field, 53b...
Register update wait instruction bit information registration field, 54... Match detection circuit, 55... Entry number holding shift register, 56... Arithmetic start control circuit.

Claims (1)

[Claims] 1. A register bank that can be read and written by instructions, multiple calculation units that can operate independently of each other,
Consisting of a data path that supplies operands from the register bank to the arithmetic unit, a data path that transfers the arithmetic results of the arithmetic unit to the register bank, and a control unit that controls each of the above components,
In the information processing device, the control unit monitors update of the register bank by a preceding instruction to control operand read start of the instruction, the control unit comprising:
An entry for registering a register number of the register bank that stores the operation result of the decoded instruction and update wait instruction bit information indicating that the register of the register bank specified by the register number is waiting to be updated by a preceding instruction. A stack having multiple entries, and matching entry detection means for checking the match between an operand read register number specified by an instruction prior to reading an operand and a register number registered in each entry of the stack, and outputting a matching entry number. and entry number holding means for holding the entry number detected by the matching entry detection means as the instruction processing progresses, and the stack specified by the entry number held in the entry number holding means when reading the operand. By checking only the update wait instruction bit information registered in the entry,
update waiting detection means for detecting whether a register of the register bank in which an operand is stored is waiting for update; and if the detection result from the update waiting detection means is that it is waiting for update, 1. An information processing apparatus comprising: control means for causing readout of the operand to wait until the operand is released.