JPH0211034B2 - - Google Patents
Info
- Publication number
- JPH0211034B2 JPH0211034B2 JP27847984A JP27847984A JPH0211034B2 JP H0211034 B2 JPH0211034 B2 JP H0211034B2 JP 27847984 A JP27847984 A JP 27847984A JP 27847984 A JP27847984 A JP 27847984A JP H0211034 B2 JPH0211034 B2 JP H0211034B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- plating
- wiring board
- adhesive
- printed wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000010410 layer Substances 0.000 claims description 37
- 238000007747 plating Methods 0.000 claims description 26
- 239000000463 material Substances 0.000 claims description 9
- 239000000853 adhesive Substances 0.000 claims description 8
- 230000001070 adhesive effect Effects 0.000 claims description 8
- 239000012790 adhesive layer Substances 0.000 claims description 8
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 238000000034 method Methods 0.000 claims description 6
- 238000007772 electroless plating Methods 0.000 claims description 5
- 239000003054 catalyst Substances 0.000 claims description 4
- 238000001723 curing Methods 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 4
- 239000012298 atmosphere Substances 0.000 claims description 3
- 238000007788 roughening Methods 0.000 claims description 3
- 238000007598 dipping method Methods 0.000 claims description 2
- 238000013007 heat curing Methods 0.000 claims description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 7
- 229910052802 copper Inorganic materials 0.000 description 7
- 239000010949 copper Substances 0.000 description 7
- 238000003475 lamination Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 238000007650 screen-printing Methods 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 230000008961 swelling Effects 0.000 description 2
- KXGFMDJXCMQABM-UHFFFAOYSA-N 2-methoxy-6-methylphenol Chemical compound [CH]OC1=CC=CC([CH])=C1O KXGFMDJXCMQABM-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- CMMUKUYEPRGBFB-UHFFFAOYSA-L dichromic acid Chemical compound O[Cr](=O)(=O)O[Cr](O)(=O)=O CMMUKUYEPRGBFB-UHFFFAOYSA-L 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 229920001568 phenolic resin Polymers 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
【発明の詳細な説明】
産業上の利用分野
本発明は無電解銅めつき層で平面回路を形成し
て内層基板とし、プレス作業を用いないで製造す
る多層印刷板の製法に関する。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method for manufacturing a multilayer printing plate in which a planar circuit is formed using an electroless copper plating layer as an inner layer substrate and is manufactured without using a press operation.
従来の技術
多層印刷配線板は両面に回路が形成された印刷
配線板とプリプレグを交互に重ね合わせ、積層プ
レスを行い、積層した後孔を明け、全面に化学銅
めつき及び電気銅めつきを施し、その後エツチン
グレジストを塗布し、エツチング処理して製造し
ている。Conventional technology Multilayer printed wiring boards are made by alternately stacking printed wiring boards with circuits formed on both sides and prepreg, performing lamination pressing, making holes after lamination, and applying chemical copper plating and electrolytic copper plating to the entire surface. After that, an etching resist is applied and an etching process is performed.
発明が解決しようとする問題点
従来の多層印刷配線板の製造方法は、内層回路
パターンに凸凹があり、プリプレグで基板を多層
化接着する際に、パターン間の気泡が外部に完全
に追放することができずボイドが発生する欠点が
あつた。このボイド対策としては厚手のプリプレ
グを用い、高温高圧下で長時間かけて積層プレス
を行わねばならず作業性が悪かつた。Problems to be Solved by the Invention In the conventional manufacturing method of multilayer printed wiring boards, the inner layer circuit patterns have unevenness, and when bonding multiple layers of boards with prepreg, air bubbles between the patterns are completely expelled to the outside. There was a drawback that voids were generated due to the inability to do so. To counter this void, a thick prepreg was used and lamination pressing had to be carried out for a long time under high temperature and pressure, resulting in poor workability.
問題点を解決するための手段
本発明は、めつき触媒入りの絶縁基板の両面に
めつき触媒入りの接着剤が塗布された絶縁基板を
基材とし、この基材の所定個所にめつきレジスト
層を形成し、このめつきレジスト層が形成されて
いない接着剤層の表面を粗面化し、無電解めつき
液に浸漬してめつき層を設けて内層の印刷配線板
を作り、この配線板上に絶縁層を塗布し、さらに
接着剤を形成した後、めつきレジスト層を形成
し、接着剤の表面を粗面化し無電解めつき層を形
成する多層印刷配線板の製造方法において、前記
絶縁層を硬化する際に３Kg/cm2以上の高圧下で加
熱硬化を行うものである。Means for Solving the Problems The present invention uses an insulating substrate containing a plating catalyst on both sides of which an adhesive containing a plating catalyst is applied as a base material, and a plating resist is applied to predetermined locations on this base material. The surface of the adhesive layer on which the plating resist layer is not formed is roughened and immersed in an electroless plating solution to form a plating layer to create an inner printed wiring board. In a method for manufacturing a multilayer printed wiring board, the method includes applying an insulating layer on a board, further forming an adhesive, forming a plating resist layer, and roughening the surface of the adhesive to form an electroless plating layer. When curing the insulating layer, heat curing is performed under high pressure of 3 kg/cm 2 or more.
実施例
めつき触媒入りの接着剤２（日立化成工業株式
会社製HA−24）を塗布した0.8mm厚さの紙フエノ
ール樹脂積層板（日立化成工業株式会社製ACL
−141S）１を基材３（第２図）とし、この基材
３上にめつきレジスト層インク（日立化成工業株
式会社製HGM−02BK−１）をスクリーン印刷
方法で回路パターンを設けない個所を印刷して
20μ厚のメツキレジスト層４を形成し、160℃30
分の条件で硬化する（第３図）。その後硼弗化水
素酸と重クロム酸とからなる粗化液で接着剤２の
表面を粗面化５し（第４図）、洗浄した後無電解
めつき液（日立コンデンサ株式会社製CC−41）
に浸漬し20μ厚の銅めつき層６を形成し内層の印
刷配線板１０を製作する（第５図）。Example 0.8 mm thick paper phenolic resin laminate (ACL manufactured by Hitachi Chemical Co., Ltd.) coated with adhesive 2 containing plating catalyst (HA-24 manufactured by Hitachi Chemical Co., Ltd.)
-141S) 1 is used as the base material 3 (Figure 2), and on this base material 3, a plating resist layer ink (HGM-02BK-1 manufactured by Hitachi Chemical Co., Ltd.) is applied by screen printing to areas where no circuit pattern is provided. print out
Form a plating resist layer 4 with a thickness of 20μ and heat at 160℃30
It hardens under conditions of minutes (Figure 3). Thereafter, the surface of the adhesive 2 was roughened with a roughening solution consisting of borofluoric acid and dichromic acid (Fig. 4), and after washing, an electroless plating solution (CC- 41)
A copper plating layer 6 having a thickness of 20 μm is formed by dipping the copper plated layer 6 into an inner layer printed wiring board 10 (FIG. 5).
この配線板１０の銅めつき層６の表面を黒化処
理し、この上に絶縁インク（日立化成工業株式会
社製レジストインクHGM−02BK−１）をスク
リーン印刷法で50μ塗布し、100℃に加熱して溶
剤を除去後、５Kg/cm2のオートクレーブの中で160
℃30分間加熱し絶縁層１１を形成し、次にカーテ
ンコーターで接着剤層１２を塗布硬化し（第６
図）、めつきレジスト層１３を形成後、接着剤１
２の表面を化学的に粗面化１４し、めつきレジス
ト層１３を形成する（第７図）。この後パンチで
孔をあけ１５を行い（第８図）、パンチかすを洗
浄後無電解銅めつきで外層回路１６とスルーホー
ル１８を形成（第１図）し、多層印刷配線板２０
を作成した。 The surface of the copper plating layer 6 of the wiring board 10 is blackened, and 50μ of insulating ink (resist ink HGM-02BK-1 manufactured by Hitachi Chemical Co., Ltd.) is applied thereon by screen printing, and heated to 100°C. After heating to remove the solvent, it was heated to 160 ml in an autoclave at 5 kg/cm 2.
℃ for 30 minutes to form the insulating layer 11, then apply and harden the adhesive layer 12 using a curtain coater (6th
Figure), after forming the plating resist layer 13, the adhesive 1
The surface of 2 is chemically roughened 14 to form a plating resist layer 13 (FIG. 7). After that, a hole 15 is made with a punch (Fig. 8), and after cleaning the punch residue, an outer layer circuit 16 and a through hole 18 are formed by electroless copper plating (Fig. 1), and a multilayer printed wiring board 20 is formed.
It was created.
他の実施例として、前記の絶縁物１１の硬化時
に加えて、接着剤層１２の硬化時にもオートクレ
ーブ内の圧力を５Kg/cm2の雰囲気下で加熱処理を
行つた。 As another example, in addition to the curing of the insulator 11 described above, heat treatment was performed at the time of curing the adhesive layer 12 under an atmosphere in which the pressure inside the autoclave was 5 Kg/cm 2 .
この圧力は３Kg/cm2以上が好ましく、３Kg/cm2以
上の圧力下温度は150〜160℃で30分間で加熱処理
すると、層間のボイドが消失するためで、２Kg/
cm2の圧力下では完全に消えず半田付け時に脹れが
生じることがある。この加圧雰囲気は空気中でも
窒素の雰囲気でもかまわない。また、めつきレジ
スト層を形成する際に感光性フイルムを用いた場
合でも同様の効果がえられる。 This pressure is preferably 3Kg/cm 2 or more, and if the temperature is 150 to 160℃ for 30 minutes under a pressure of 3Kg/cm 2 or more, voids between the layers will disappear.
It does not disappear completely under pressure of cm2 , and swelling may occur during soldering. This pressurized atmosphere may be air or nitrogen atmosphere. Further, similar effects can be obtained even when a photosensitive film is used when forming the plating resist layer.
発明の効果
本発明の製造方法により製作された多層印刷配
線板は、半田（260℃10sec）処理を行つた後観察
すると層間に脹れが生じることがなく、また
MIL−1070（−65℃125℃）の熱サイクルが100
回以上の信頼性を確認できた。Effects of the Invention When the multilayer printed wiring board manufactured by the manufacturing method of the present invention was observed after soldering (260°C for 10 seconds), no swelling occurred between the layers.
MIL−1070 (−65℃125℃) thermal cycle is 100
We were able to confirm reliability more than once.
第１図は本発明の断面図、第２図は基材の断面
図、第３図は内層のめつきレジスト層を形成した
断面図、第４図は粗面化した断面図、第５図は内
層印刷配線板の断面図、第６図は絶縁層及び接着
剤層を形成した断面図、第７図は外層のめつきレ
ジスト層を形成した断面図、第８図はスルーホー
ル用の孔明けを行つた断面図である。
図面において、１は絶縁基板、２は接着剤層、
３は基材、１０は内層配線板、１１は絶縁層、１
２は接着剤層、１３はめつきレジスト層、２０は
多層印刷配線板。
FIG. 1 is a sectional view of the present invention, FIG. 2 is a sectional view of the base material, FIG. 3 is a sectional view of the inner plating resist layer formed, FIG. 4 is a sectional view of the roughened surface, and FIG. 5 is a sectional view of the base material. 6 is a sectional view of the inner layer printed wiring board, FIG. 6 is a sectional view of the insulating layer and adhesive layer formed, FIG. 7 is a sectional view of the outer plating resist layer formed, and FIG. 8 is the hole for the through hole. It is a cross-sectional view after opening. In the drawings, 1 is an insulating substrate, 2 is an adhesive layer,
3 is a base material, 10 is an inner layer wiring board, 11 is an insulating layer, 1
2 is an adhesive layer, 13 is a plating resist layer, and 20 is a multilayer printed wiring board.
Claims (1)
絶縁基板を基材とし、この基材の所定個所にめつ
きレジスト層を形成し、このめつきレジスト層が
形成されていない接着剤層の表面を粗面化し、無
電解めつき液に浸漬してめつき層を設けて内層の
印刷配線板を作り、この配線板上に絶縁層を塗布
し、さらに接着剤層を塗布した後、めつきレジス
ト層を形成し、接着剤の表面を粗面化し、無電解
めつき層を順次形成する多層印刷配線板の製造方
法において、前記、絶縁層を硬化する際に圧力が
３Kg/cm2以上の高圧の雰囲気化で温度が150〜160
℃で30分間加熱硬化を行うことを特徴とする印刷
配線板の製造方法。1 An insulating substrate coated with an adhesive containing a plating catalyst on both sides is used as a base material, a plating resist layer is formed at predetermined locations on this base material, and the adhesive layer on which this plating resist layer is not formed is After roughening the surface and applying a plating layer by dipping it in an electroless plating solution to create an inner layer printed wiring board, an insulating layer is applied on this wiring board, and an adhesive layer is further applied. In the method for manufacturing a multilayer printed wiring board in which a plating resist layer is formed, the surface of the adhesive is roughened, and an electroless plating layer is sequentially formed, the pressure is 3 Kg/cm 2 or more when curing the insulating layer. Temperature is 150-160℃ due to high pressure atmosphere.
A method for manufacturing a printed wiring board, characterized by heat curing at ℃ for 30 minutes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27847984A JPS61154198A (en) | 1984-12-27 | 1984-12-27 | Manufacture of multilayer printed wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27847984A JPS61154198A (en) | 1984-12-27 | 1984-12-27 | Manufacture of multilayer printed wiring board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61154198A JPS61154198A (en) | 1986-07-12 |
| JPH0211034B2 true JPH0211034B2 (en) | 1990-03-12 |
Family
ID=17597901
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27847984A Granted JPS61154198A (en) | 1984-12-27 | 1984-12-27 | Manufacture of multilayer printed wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61154198A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63126297A (en) * | 1986-11-14 | 1988-05-30 | イビデン株式会社 | Multilayer printed interconnection board and manufacture of the same |
-
1984
- 1984-12-27 JP JP27847984A patent/JPS61154198A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61154198A (en) | 1986-07-12 |
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