JPH0211872B2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention is a tester that enables the function of a circuit such as an LSI, which has a terminal whose state changes depending on the internal state of the circuit, to be input or output, to be tested without wasting time. This invention relates to a pattern generator with input/output switching control.

Conventionally, pattern generators are generally used in testers that test circuits such as LSIs that have terminals that change to input or output depending on the internal state of the circuit. Data necessary for input/output switching control of the tester stored in the pattern memory is stored in the input/output control register necessary for setting the input/output state switching of each terminal of the tester, and the judgment strobe control register (to compare the actual output with the expected value). That is, input/output control data and determination strobe control data are input and processed in synchronization with the generation cycles of test input patterns and output expected value patterns. Conventionally, when generating a test input pattern or output expected value pattern, if the state of the terminal of the circuit under test changes during the generation, generation of the pattern is stopped and the input/output control data and judgment strobe control data are It was input to each setting register. Therefore, the test input pattern and output expected value pattern treat the cycle in which input/output control data and determination strobe control data are input to each setting register as a dummy, and the pattern cannot be generated in the original test cycle.

SUMMARY OF THE INVENTION An object of the present invention is to provide a pattern generator for a tester that is suitable for testing a circuit having terminals that change between input and output depending on the internal state and is capable of controlling input/output switching without dummy cycles.

In order to achieve the above object, in the present invention,
A pattern memory in which data necessary for input/output switching control is stored in the same memory in the required order in addition to the test input pattern and the expected output value pattern;
A means for accessing this memory multiple times during one test cycle is provided, and no dummy portion is provided in the test cycle, so after switching and setting the input/output state on the test side, the test input pattern and output expected A value pattern is now generated.

FIG. 1 is a schematic block diagram of an embodiment of the present invention.
is a pattern memory, 2 is a memory content analysis circuit, and 3 is a pattern memory.
4 is an input/output control register, 4 is a judgment strobe control register, and 5 is a pattern register. FIG. 2 shows a timing chart of memory access in this embodiment. Memory 1 is accessed at timing 7 of _T1 , data is taken into the memory content analysis circuit 2, and data is written to each register according to the content of the memory. Set. At this time, if it is input/output control data or judgment strobe control data, the pattern memory is further accessed at timing 8 of T ₂ or timing 9 of T ₃ in the same test cycle, and the input/output control data is stored in the input/output control register 3. , sets the judgment strobe control data in the judgment strobe control register 4 and the pattern data in the pattern register 5. In this way, within the same test cycle,
A pattern generator can be created that processes data necessary for input/output switching, test input patterns, and output expected value patterns in parallel without dummy cycles or dummy time. Timing 7 of T ₁ begins with the test cycle. If the pattern data is retrieved at this timing 7, the data retrieval from the pattern memory in that test cycle is completed. If the determination strobe control data is taken out at this first timing 7, pattern data is taken out at the next timing 8 of _T2 . When input/output control data is first retrieved at timing 7 of T ₁ , switching settings for the input/output state of the tester side terminals are performed, and in general, corresponding determination strobe control data is retrieved at timing 8 of T ₂ . The pattern data is taken out at timing 9 of _T3 .

Conventionally, in order to prevent the loss of time caused by placing a dummy part in the test cycle, in addition to the pattern (special question) memory, special memory for input/output control data and judgment strobe control data was provided (physically speaking). In any case, there were examples in which a timing control circuit was added to control the timing between them (logically), but it became complicated and expensive. In this respect, the present invention is simple and inexpensive.

As explained above, according to the present invention, it is possible to obtain a pattern generator that is time efficient, relatively simple and inexpensive, and suitable for a tester used for testing LSIs and the like.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a timing chart of memory access of the same embodiment. 1... Pattern memory, 2... Memory content analysis circuit, 3... Input/output control register, 4... Judgment strobe control register, 5... Pattern register,
6...test cycle, 7, 8, 9...each
Timings of T ₁ , T ₂ and T ₃ , 10... pattern memory access timing.

Claims (1)

[Claims] 1. A memory that stores test input patterns, output expected value patterns, and data necessary for input/output switching control for testers intended for circuits that have terminals whose states change depending on the internal state of the circuit. In addition to the test input pattern and the output expected value pattern, the pattern generator is equipped with a memory content analysis circuit that inputs the output into a specific setting register according to the memory output content, and each setting register. It is equipped with a pattern memory in which the data necessary for output switching control is also stored in the same memory in the required order, and a means for accessing this memory multiple times during one test cycle. A pattern generator with input/output switching control for a tester, characterized in that output switching control can also be performed.