JPH0213964B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to integrated circuits using complementary insulated gate field effect transistors.

Has functions such as a microcomputer and a calculator
A function is provided to automatically set the inside of the LSI to a certain initial state when power is turned on.

However, on the other hand, it is also required to be able to use a wider range of voltages and to be able to cope with power failures during use.
The default settings currently in use are becoming insufficient.

FIG. 1 shows an example of a conventional integrated circuit configuration.

FIG. 2 shows the output waveforms of each terminal. Note that the following explanation of the operation is for the case where a positive power source is used as the power source for the terminal V _DD , but it is clear that the operation can also be applied to a negative power source.

When power is not applied to the power supply terminal V _DD , the potentials of the power supply terminals V _DD , V _SS and contacts 1, 2, and 3 are V ₁ ,
It is assumed that V ₂ and V ₃ are always at the level of V _SS (eg, ground). From this state, any potential can be applied to the power supply terminal V _DD .
When a power supply voltage of V _C is applied, the power supply terminal inside the LSI
The potential of V _DD rises toward an arbitrary potential V _C with the time constant of the internal resistance of the power supply and the parasitic capacitance of the terminal V _DD . In a transient state where the power supply terminal V _DD rises to an arbitrary potential V _C as _shown by T _A in FIG. N type transistor M
2, M3, M5, M7 threshold voltage V _A is determined by the division ratio of the load capacitance attached to the power supply terminal V _DD and power supply terminal V _SS side. Therefore, contact 1 is connected to the power supply terminal V _DD with a large capacitance C ₁ that can sufficiently ignore parasitic capacitance, and contact 2 is connected to the power supply terminal V _SS
If a large capacitor C ₂ is connected to the side so that the parasitic capacitance can be sufficiently ignored, the contact 1 will be in the vicinity of the threshold voltage V _A and the contact 2 will be in the vicinity of the voltage V _SS .

Next, contacts 1 and 2 are power supply terminals because they constitute a flip-flop with an inverter made up of a P-type transistor M1 and an N-type transistor M3, and an inverter made up of a P-type transistor M4 and an N-type transistor M5. When V _DD becomes higher than the potential V _A , the two inverters become fully operational. At this time, the potential level V ₁ of contact 1 is
Since the potential level V2 of contact ₂ is near V _A and near the potential V _SS , the potential V 1 of contact ₁ is stabilized at the potential of power supply terminal V _DD and contact 2 is stabilized at the potential of power supply terminal V _SS , and as a result, the integrated circuit Contact 3, which generates the initial set output of the internal state memory circuit, changes to the potential on the power supply terminal _VDD side and becomes stable. This means that whether the voltage applied to the power supply terminal V _SS rises quickly or slowly, the potential V 1 of contact ₁ is always on the terminal V _DD side, and the potential V ₂ of contact 2 is always on the V _SS side. At this time, the potential V ₃ of the contact 3 becomes stable on the V _DD side. This ensures that the internal circuit is in a certain initial state when the LSI power is turned on, and this state cannot be released unless the potential V ₃ of the contact 3 reaches the V _SS level. Next, contact 3
As the potential V ₃ of the terminal V 3 becomes stable to the potential V _C of the terminal V _DD , a clock signal is generated in the input signal I ₁ during the period T _B of FIG. In other words, the voltage changes from the V _SS level to the V _C level. This signal _I1 may be a clock of an oscillation circuit inside the circuit or an input signal from outside the circuit. This signal turns on the N-type transistor M2, and the potential V ₁ of contact 1 is forced to the terminal V _SS
level. (However, at this time, it is necessary to design the on-resistance of the N-type transistor M2 to be sufficiently smaller than the on-resistance of the P-type transistor M1.) As a result, the potential V ₂ of the contact point 2 is lower than that of the P-type transistor M4. is off, and the N-type transistor M5 was on, whereas the P-type transistor M5 was on.
4 is turned on, N-type transistor M5 is turned off, and the level changes from the V ₁ level to the V _C level.

Furthermore, since the potential V ₂ of contact 2 has reached the V _C level, the P-type transistor M1 was turned on and the N-type transistor _M3 was turned off, but now the P-type transistor _M1 is turned off and the N-type transistor M3 is turned off. is turned on.

Due to the above operation, even if the input signal I ₁ changes from the V _C level to the V _SS level again after a certain period of time, the potential at contact 1 remains stable at the V _SS level, and the potential V ₂ at contact 2 remains at the V _C level. The potential V ₃ of contact 3 also changes from V _C level to V _SS
The level changes and stabilizes. In this way, the initial state in which the potential V ₃ of the contact in the logic circuit inside the LSI is at the potential _VC is released, and the LSI becomes able to receive and execute instructions from the outside from the initial state.

Currently, in addition to the above operations, the power supply terminal is
When the potential of V _DD drops to a certain potential V _B and returns to V _C again, an initial state is required to prevent the LSI from malfunctioning, and there is a particularly strong requirement that V _B > V _A. In the case of V _B > V _A , in the conventional circuit, the potential of V _SS V _SS changes from V _C to V _B as shown in period T _C in Fig. 2, and when it changes from V _B to V _C , the potential of contact 2 is simply changed. There is a drawback that the inside of the LSI does not return to its initial state simply by changing the potential V ₂ from V _C to V _B and from V _B to V _C.
This is because the current circuit is operating normally because the potential V _B >the potential V _A , and the power supply terminal V _SS has simply changed within the voltage that allows normal operation.

SUMMARY OF THE INVENTION An object of the present invention is to provide an integrated circuit which eliminates the above-mentioned drawbacks.

An integrated circuit according to the present invention includes first and second terminals to which a power supply voltage is applied, and a flip-flop that enters a first stable state when the power supply voltage between these terminals rises and exceeds a first voltage level. ,
The state control terminal of this flip-flop and the first
a first transistor connected between a terminal of the flip-flop and a terminal of the flip-flop, and bringing the flip-flop into the first stable state by making the first transistor conductive after the flip-flop reaches the first stable state. further, a second transistor is provided between the state control terminal of the flip-flop and the second terminal, and the power supply voltage is set to a predetermined voltage level and the first voltage. When the voltage drops to a second voltage level set between the flip-flop and the
The stable state is changed from the stable state to the first stable state.

An embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 3 shows the circuit configuration of the embodiment, and FIG. 4 shows the output waveforms of each terminal.

In Fig. 3, the input of the power supply voltage shift circuit A is the power supply terminals V _DD and V _SS , and the output signal I2 is the power supply terminal.
When V _DD is below the potential of V _{D ,} V _D
The circuit forms a circuit that reaches the level of terminal V _DD at a potential higher than . (At this time, V _D ≧ V _B. ) Furthermore, a P-type transistor M whose gate is connected to the output signal I2 in parallel with the P-type transistor M1 at the contact 1'.
8 and input terminal I in parallel with N-type transistor M3.
An N-type transistor M2 whose gate is connected to 1' is connected. That is, this embodiment is constructed by adding a transistor M8 and a voltage shift circuit A to the circuit shown in FIG. The set output is obtained from contact 3'.

With this configuration, when a power supply having a potential V _C is applied to the power supply terminal V _DD as in the period T _A ' in FIG.
When a clock signal is input to the input terminal I ₁ ' during period T _B ' in the figure, the operation is exactly the same as that of the conventional circuit shown in FIG. 1.

Next, in period T _C ′ in Fig. 4, the power supply terminal
V _DD is at potential V _C. Further, the potential V 2 ' of the output signal I2 and the node ₂ ' is also the potential V _C , and the potential of the contacts 1' and 3' is the terminal V _SS potential. And the power terminal
When V _DD drops from the potential V _C to the potential V _D , the output signal I2 and the potential V ₂ ' at the node 2 similarly become the potential V _D.
Furthermore, when the power supply terminal V _DD becomes lower than the potential V _D , the signal I
2 changes to the potential of terminal V _SS and becomes stable. In other words, when the power supply terminal V _DD changes from the potential V _D to the potential V _B , the output signal I2 of the circuit A changes to the potential of the terminal V _SS , so that the P-type transistor M, which was in the off state until then, changes to the potential V B.
8 is turned on. At this time, the potential V ₂ ' of the contact 2' was previously at the same potential as the power supply terminal V _DD , so the N-type transistor M3 is in the on state, but the on-resistance of the P-type transistor M8 is set to be the on-resistance of the N-type transistor M3. By designing the contact point 1' to be sufficiently small, the potential V ₁ ' of the contact 1' is forcibly changed from the potential V _SS to the vicinity of the potential V _B. Further, as the potential of the contact 1' changes from the potential of the terminal V _SS to the vicinity of the potential V _B , the P-type transistor M4 whose gate is connected to the contact 1' changes from the on state to the off state, and the N-type transistor M5 changes from the off state to the on state. In this state, the potential V ₂ ' of the contact 2' becomes the potential of the terminal V _SS rather than the potential V _B. This results in N
type transistor M3 changes from the on state to the off state,
The P-type transistor M1 changes from the off state to the on state, and the potential V ₁ ' at contact 1' becomes lower than the potential near the potential V _B.
Becomes V _B. Furthermore, since the potential of the contact 2' has changed from the potential V _B to the potential of the terminal V _SS , the potential of the contact 3' changes from the potential of the terminal V _SS to the potential V _B.

Next, when the power supply terminal V _DD returns from the potential V _B to the potential V _C , when the power supply terminal V _DD becomes higher than the potential V _D , the signal I
2 changes from the potential of the terminal _VSS to the same potential as the power supply terminal _VDD , and the P-type transistor M8 changes from the on state to the off state. The potential V2' of the contact 2' is supplied with the potential of the terminal _VSS by the N-type transistor M5, and the potential of the power supply terminal _VDD is supplied to the contact 1 with the potential of the power supply terminal VDD from the P-type transistor M1, so the potential of the contacts 1' and 3' is _V1 '. , V ₃ ' become the potential V _C , and the potential V2' of the contact 2' becomes the potential of the terminal V _SS . This is the same state as when the power is turned on during period T _A ' in FIG. 4, and the LSI internal logic circuit can be brought to a certain initial state.

In other words, the circuit shown in FIG. 3 of the present invention can return the LSI internal logic circuit to its initial state when the potential of the power supply terminal V _DD drops below the potential V _D (when the LSI is used).

A specific example of the configuration of the voltage shift circuit A shown in FIG. 3 will be explained with reference to FIG. 5.

i N-type transistors _{MN1 , MN2 ,} . The total threshold value of the i transistors connected in series is set to the above-mentioned potential V _D. Further, j P-type transistors MP ₁ , MP ₂ , . . . MPj, each having a gate and a drain connected to each other, are connected in series between the node NV ₀ and the terminal V _SS . The total threshold value of these j transistors is set to be the above-mentioned potential V _D.
In this series circuit, when the terminal V _DD becomes higher than the potential V _D , the potential of the node NV ₀ changes in the direction of the terminal V _DD , and the output I at the terminal V _DD level is output via the two-stage inverters INV ₁ and INV ₂ as a buffer. It is retrieved as ₂ . At this time, P-type transistors MP ₁ to MPj are off. When the potential of the other terminal V _DD is lower than V _D , the P-type transistors MP ₁ to MPj are turned on, and the node N _V0
changes to the potential of terminal V _SS . Therefore, the output I ₂ is
V _SS level.

Another example of the voltage shift circuit A is shown in FIG. In this example, the P-type transistors MP ₁ to MPj shown in FIG.
is replaced with a resistor R, and the basic operation is the same as the example shown in FIG.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an example of a conventional circuit, FIG. 2 is a diagram showing its operating waveforms, FIG. 3 is a diagram showing an embodiment of the present invention, and FIG. 4 is a diagram showing its operating waveforms.
FIGS. 5 and 6 are circuit diagrams showing specific examples of voltage shift circuits. M1, M4, M6...P-type transistor, M
2, M3, M5, M7...N-type transistor, C
1, C2...Capacity.

[Claims]

1 first and second complementary inverters; a first field effect transistor of one conductivity type connected between the output of the first complementary inverter and the input of the second complementary inverter; a second field effect transistor of opposite isoelectric type connected between the input of the second complementary inverter and the power supply terminal, the output terminal, and the output terminal of the second complementary inverter and the output terminal; the fourth field effect transistor of the opposite conductivity type, the fourth field effect transistor being connected between the output terminal and the reference terminal and having a gate connected to the input of the second complementary inverter; a field effect transistor; a reset terminal connected to the input of the first complementary inverter and the gate of the second field effect transistor;
and a set terminal connected to the gates of the first and third field effect transistors.