JPH0213985B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a demodulation device that demodulates a composite PSK-PSK modulated wave in which a PSK-modulated signal using a main data signal is further two-phase PSK-modulated using a sub-data signal. In recent years, the development of carrier wave digital transmission systems has been remarkable, and various lines have already been put into practical use. However, recently, the required transmission systems have tended to be diversified, and it is important to find a transmission system that is versatile and has high operational efficiency. Consideration has begun. One of these is the ``carrier wave digital transmission system'' described in Japanese Patent Application No. 1983-37004 filed by the inventors of the present application on March 29, 1973. This method involves adding two-phase PSK modulation to the main data line using PSK modulation to perform composite transmission of sub data signals. According to this method, the code transmission speed of the sub data signal is compared to that of the main data signal. If the ratio is below a certain level, the sub data signal can be efficiently transmitted without affecting the error rate of the main data signal. Here, the amount of phase shift α due to the sub data signal is the number of phases of the main data signal 2 <sup>n</sup> (n=2, 3,...)
Then, the efficiency is highest when α=π/2π. At this time, the modulated output vector becomes the same as the 2 <sup>n+1</sup> phase PSK signal. In order to phase-detect such a modulated wave, conventionally used delay detection or synchronous detection may be used, but when synchronous detection is used, the following problems exist. That is, although the main data signal component must be phase-detected for 2 <sup>n</sup> phases, a phase synchronization circuit for 2 <sup>n+1</sup> phases must be used to reproduce the reference carrier wave. As is well known, in the 2 <sup>n+1</sup> phase phase locked circuit, there is a stable point of attraction every 2π/2 <sup>n +1</sup> radians, and for this reason, the 2π/2 <sup>n+1</sup> ( 2i+1) [i=0, 1,...≦ (2 <sup>n+1</sup> /2-1)] 2 <sup>n</sup> stable points of attraction in radians are included. In 1978, the inventors of the present application proposed a conventional method known as a method for avoiding the above-mentioned inconvenient retraction phase.
There is a ``phase synchronized circuit'' described in Japanese Patent Application No. 53-41672 filed on May 7th. this is,
In the modulation system, the phase shift amount α due to the sub data signal is selected to be α<π/2 ⁿ , and the vector arrangement of the modulated output is made different from that of the 2 ^{n + 1} phase PSK wave, and
The phase synchronization circuit of the composite PSK modulation system includes a phase detector for phase detecting an input signal, a first means for reproducing a sub data signal having a code transmission rate f ₂ from the output of the detector, and a second means for obtaining at least two orthogonal signals from which the sub data signal component is removed from the detector output using the sub data signal regenerated by the second means as a control signal; a third means for obtaining a phase error signal by multiplying the signal by ²ⁿ ;
and a voltage controlled oscillator whose frequency is controlled by the output signal of the means. However, according to such a phase synchronization circuit, although an inconvenient pull-in phase can be avoided, on the other hand, the phase deviation amount α of the sub data signal must be selected to satisfy α<π/2 ⁿ . For this reason, there was a drawback that the resistance to noise of the sub data signal had to be sacrificed by 20 log (α/π/2 ⁿ ) dB compared to the best condition. It is an object of the present invention to eliminate the above-mentioned drawbacks, to be able to select π/2 ⁿ radians as the phase deviation amount of the sub data signal, and to be able to maintain the correct phase shift in any phase locking state of the phase-locked demodulator. The object of the present invention is to provide a demodulator capable of obtaining main and sub data signals. According to the present invention, a signal subjected to 2 ⁿ (n=2, 3, 4, _... ) phase PSK modulation by a sending data signal having a code transmission rate f 1 is further converted to a signal having a code transmission rate f ₂ (f ₁ > f ₂ ). In a demodulation device equipped with a phase-locked demodulator that obtains at least two demodulated signals in an orthogonal relationship from an input signal in order to demodulate into a modulated wave subjected to two-phase PSK modulation using a sent sub-data signal, the demodulated signal means for reproducing a received sub-data signal corresponding to the sent sub-data signal from the received sub-data signal; and a pull-in phase determining means for determining a phase pull-in state of the phase synchronization demodulator based on a frame signal included in the received sub-data signal; A demodulation device is obtained, comprising means for reproducing a receiving main data signal corresponding to the sender data signal from the demodulated signal using the receiving sub data signal and the output signal of the pull-in phase determining means. Next, embodiments of a demodulator according to the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the structure of a first embodiment of a demodulator according to the present invention. Note that this example shows a case where 4PSK waves are applied as the main data signal, as seen in the coordinate system of FIG. 2. In FIG. 1, 1 is a quadrature demodulator, 2 to 5 are resistors, 6, 7, and 19 are adders, and 8
~9 and 20 are subtractors, 10 to 12 are multipliers, 13
1 is a low-pass filter, 14 is a discriminator, 15 to 18 are analog switches, 21 and 23 are negative circuits, and 22 is a pull-in phase discrimination circuit. In such a configuration, an input signal enters the orthogonal demodulator 1, undergoes orthogonal detection, and is converted into two demodulated signals P and Q that are orthogonal to each other. These signals are supplied to the sub data reproducing section and the main data reproducing section. First, to explain the sub data reproducing section, the P and Q signals enter a phase shifter composed of resistors 2 to 5, adders 6 and 7, and subtracters 8 and 9, and here, as shown in Table 1, Output signals 101~ with phase relationships as shown
104.

[Table] Of these, signals 101 and 102 enter the multiplier 10 and are multiplied to become 105, and 103 and 1
04 is multiplied by the multiplier 11 and becomes a signal 106. Further, 105 and 106 are multiplied by multiplier 12 to obtain signal 107. This 107 signal is the input signal multiplied by 4, so that the main data signal is removed, leaving only the sub data signal. If this signal is identified by the discriminator 14 through the low-pass filter 13 that removes noise components, the sub data signal CH
3 is obtained. Next, the main data reproducing section will be explained. The demodulated signals P and Q pass through analog switches 15 and 16, an adder 19, a subtracter 20 and an inverter 23 to become output signals 108 to 111, respectively. Of these, signals 110 and 111 become P and Q signals, respectively, when the output of a pull-in phase discriminating circuit 22, which will be described later, is in the "0" state. Further, the 108 and 109 signals are signals delayed by π/4 radians from the P and Q signals, respectively. Of these, 11
0,108 signal enters analog switch 17,
Here, when the output of the sub data signal CH3 is "0", the signal 110 is selected, and when the output is "1", the signal 110 is selected.
08 is selected to derive the signal 112 at its output. Similarly, the 111 and 109 signals enter the analog switch 18, where the sub data signal CH
When the output of 3 is "0", signal 111 is selected,
When it is "1", the signal 109 is selected and the signal 113 is derived at its output side. FIG. 3 shows signal waveforms at various parts in the embodiment of FIG. 1. In this figure, the horizontal axis θ represents the phase relationship between the input signal and the reference carrier wave, and when the modulated wave shown in FIG. 2 is input, the demodulated signals P and Q are a ₁ to a ₈ and
The signal has values from a ₁ ′ to _{a 8} ′. Now, when the modulated signal M1 in FIG. 2 is demodulated, a ₁ in FIG. 3 due to the phase uncertainty of the reference carrier wave.
~a ₈ , a ₁ ′ ~ _{a 8} ′. One of these days,
The sub data signals of a ₂ (a ₂ ′), a ₄ (a ₄ ′), a ₆ (a ₆ ′), and a ₈ (a ₈ ′) are “1” and are different from the sending signal. In the demodulation state, when the sub data signal (CH3) changes from 0 to 1 on the sending side (that is, it changes from 1 to 0 on the demodulation side), CH1 at (i)'
If we focus on the data signal of CH2 in (g)′,
It can be seen that what should be independent of the CH3 data in (d)' changes under its influence and is therefore not demodulated correctly. Therefore, in the circuit shown in FIG.
6 is provided. The retraction phase discrimination circuit 22 is
This determines whether the sub data signal matches the sending signal, and outputs "0" if the sub data signal is being reproduced correctly, and "1" if it is inverted.
When this output becomes "1", the analog switch 15 outputs the Q signal, and the analog switch 16
outputs a signal. As a result, CH2, CH1
The signals will be 112' in (h) and 113' in (j) of FIG. 3, and the identified signals will be CH2' in (h)' and CH1' in (j)'. Here, when the sub data signal changes from 0 to 1 on the sending side, CH1' and CH2' are the sub data signal even if it is demodulated as a change from 1 to 0 on the receiving side.
It can be seen that there is no influence from CH3, and the demodulation is correct as a result. In this way, in the embodiment shown in FIG. 1, the correct main signal can always be reproduced without being affected by the phase uncertainty of the reference carrier. FIG. 4 is a block diagram showing a specific configuration example of the pull-in phase discriminating circuit 22 in the embodiment of FIG. It consists of a type flip-flop. Also, Figure 5 shows the fourth
It is a time chart for explaining the operation of the pull-in phase discrimination circuit shown in the figure. The operation of the pull-in phase discriminating circuit will be described below with reference to FIGS. 4 and 5. Normally, accessory bits such as scramble bits, static bits, and parity bits are inserted or extracted into digital data signals.
A frame pulse is inserted to determine the insertion and extraction positions. Now, as shown in FIG. 5a, two frame pulses are added to the sub data signal.
Assume that a continuous bit "0" pulse is inserted. In this way, this signal can be input to the frame synchronization circuit 22-1 and frame synchronization can be established on the condition that 2 bits are consecutive.
A frame pulse as shown in Figure b can be obtained.
Therefore, if the input/output signals of the frame synchronization circuit 22-1 are applied to the D type flip-flop 22-2 at the timing shown in the time chart,
A continuous 0 level signal can be obtained at the output side of the type flip-flop 22-2. Here, the second
Point M1 in the figure is a ₁ (a ₁ ') in Figure 3a,
When demodulating with a ₃ (a ₃ ′), a ₅ (a ₅ ′), and a ₇ (a ₇ ′), the D type flip-flop 22 is used as described above.
The output of -2 is a continuous 0 level signal, but a ₂
(a ₂ ′), a ₄ (a ₄ ′), a ₆ (a ₆ ′), and a ₈ (a ₈ ′), refer to the signals in Figure 3 b and d′. As is obvious, the D type flip-flop 22
-2 output, that is, the output of the pull-in phase discrimination circuit 22, becomes a continuous 1-level signal. Therefore, the output signal of the pull-in phase discrimination circuit 22 can serve as a control signal for the analog switches 15 and 16. FIG. 6 is a block diagram showing the configuration of a second embodiment of the demodulator according to the present invention.
This example shows a case where the main data signal is an 8PSK wave, and 30 in the figure is a quadrature demodulator, 31 to 38,
59-62 are resistors, 39-42, 63-65 are adders, 43-46, 66-68 are subtracters, 47
- 53 are multipliers, 54 is a low-pass filter, 55 is a discriminator, 56 and 58 are inverter circuits, 57 is a pull-in phase discrimination circuit, and 69-79 are analog switches. First, to explain the sub data reproducing section, P, Q
The signal enters a phase shifter composed of resistors 31-38, adders 39-42, and subtracters 43-46,
Output signal 2 having a phase relationship as shown in Table 2
01 to 208 are obtained.

[Table] Of these, signals 201 and 202, 203 and 20
4, 205, 206, 207 and 208 are multiplier 4
7 to 50 respectively to obtain signals 223 to 226 at the respective outputs. Of these, signals 223, 224, 225 and 226 are sent to the next multiplier 5.
1 and 52 respectively, the signal 22
Outputs 7,228. These are further multiplier 5
Multiplied by 3, resulting in output signal 229. The signal 229 is, after all, the input signal multiplied by 8, and the main data of the 8PSK wave is removed, leaving only the sub data signal. Thus, if this signal is discriminated by the discriminator 55 via the low-pass filter 54 for noise removal, the sub data signal 230 (CH5) can be obtained via the inverter 56 on the output side. Next, to explain the main data reproducing section, the demodulated signals P and Q are connected to resistors 59 to 62 and adders 63 to 62.
65, the output signal 20 enters the phase shifter constituted by subtractors 66 to 68 and has the phase relationship shown in Table 3.
9 to 214, respectively.

[Table] Among these output signals, 210, 213, P
and Q, enter analog switches 69-72,
The selection is made according to the output of the attraction phase discriminator 57 according to Table 4 (1). The output of the pull-in phase discrimination circuit 57 is
When the sub data signal is reproduced in accordance with the sending signal, it is "0", and when it is inverted, it is "1".

【table】

[Table] In addition, the output signals 215 to 218 of the micro switches 69 to 72 and the output signals 209, 211, 212,
214 are analog switches 73 to 7 as shown in the figure.
6 and is selected as shown in Table 4 (2) depending on the output state of the recovered data signal 230. According to the above operation, the obtained signals 219 to 222 are not affected by the phase uncertainty of the reference carrier wave and always become correct main signals. Although the above first and second embodiments have been described in the case where the modulation by the main data signal is 4-phase and 8-phase, respectively, the present invention can be similarly applied to the case where the main data signal is 8 or more phases. The applicability is clear. Further, in both the first and second embodiments, the sub data reproducing section includes a first phase shifter group,
Although the second group of transporters is used in the main data reproducing section, the phase relationship between them is not limited to the values shown, and the first embodiment in FIG. 1 is taken as an example. The phase relationship between the first phase shifter group and the second phase shifter group can be freely selected as long as the waveforms g, h, i, and j in FIG. 3 are obtained.
Furthermore, although the case has been described in which the frame pulse included in the sub data signal is a fixed pulse of 2 consecutive bits, the frame pulse is not limited to 2 consecutive bits.
For example, a PN pulse can also be applied. As is clear from the above explanation, according to the present invention, it is possible to select the most efficient value α=π/ ²ⁿ as the amount of phase shift of the sub data signal, and in that case, the phase synchronization demodulator The main and sub data signals can be correctly reproduced even in an unfavorable pull-in phase state that may occur in the conventional system, which has a significant effect on improving performance and reliability.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a first embodiment of a demodulator according to the present invention, and FIG. 2 is a diagram showing a coordinate system when a 4PSK wave is applied as the main data signal to the embodiment shown in FIG. , FIG. 3 is a diagram showing the signal waveforms of each part in the embodiment of FIG. 1, FIG. This figure is a time chart for explaining the operation of the pull-in phase discrimination circuit in FIG. 4, and FIG. 6 is a block diagram showing the configuration of a second embodiment of the demodulator according to the present invention. In the figure, 1, 30 are orthogonal demodulators, 6, 7,
19, 39-42, 63-65 are adders; 8,
9, 20, 43-46, 66-68 are subtractors, 1
0-12, 47-53 are multipliers, 13, 54 are low-pass filters, 14, 55 are discriminators, 21, 23, 5
6 and 58 are inverting circuits, 22 and 57 are drawing phase discrimination circuits, 15 to 18 and 69 to 76 are analog switches, 22-1 is a frame synchronization circuit, and 22-2 is D
It is a type flip-flop.

[Claims]

1.Equipped with an answering machine and a remote control, by sending a remote control signal from the remote control to the answering machine through a telephone line, the answering machine automatically answers and records or reproduces various messages using the recording and reproducing means. In a remote control type answering machine, the remote control has input means consisting of a number key, a recording key, and a playback key, a fixed number memory that stores a fixed number unique to the remote control, and operations for the number key. When the recording key is operated along with the input of the variable number, the variable number and recording command signal are output as the first remote control signal, and when the variable number is input by operating the numeric key, the playback key is operated. If there is, the signal sending means reads the fixed number from the fixed number memory and outputs a number obtained by adding the fixed number to the variable number and a reproduction command signal as a second remote control signal, The answering machine has the above variable number and the above link.