JPH082045B2 - Digital transmission system - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a digital transmission system capable of subjecting a large-capacity data line to complex modulation of a small-capacity data signal for transmission.

[Conventional technology]

In recent years, the carrier wave digital transmission system has been remarkably developed, and various practical lines already exist. Recently, there is a tendency for the required transmission methods to diversify, and studies have begun on transmission methods with high operational efficiency. One of them is the "carrier wave digital transmission system" (Japanese Patent Laid-Open No. 54-142008) filed by the present inventors on March 29, 1978.

In this system, a sub data signal is compositely transmitted by two-phase PSK modulation to a main data line using PSK modulation. According to this method, if the code transmission rate of the sub data signal is set to a certain ratio or less compared to that of the main data signal, the sub data signal can be efficiently transmitted without affecting the error rate of the main data signal. You can

[Problems to be solved by the invention]

However, in this method, the modulation method of the main data signal is
It has the drawback that it is limited to PSH modulation and cannot be applied to 16-value or 64-value quadrature amplitude modulation, which is becoming the mainstream at present.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a digital transmission system capable of eliminating the above-mentioned drawbacks by efficiently transmitting a composite sub-data signal to a main data line using quadrature amplitude modulation.

[Means for solving problems]

In the digital transmission system of the present invention, the quadrature amplitude modulation wave modulated by the main data signal having the code transmission rate f ₁ is supplied to the modulation side by 2α as the sub data signal having the code transmission rate f ₂ (f ₁ > f ₂ ).
A means for obtaining a composite modulated wave by radian phase modulation is provided, and the demodulated signal P is obtained by quadrature phase detection of the composite modulated wave on the demodulation side.
And Q, and at least the demodulated signals P and Q
Means for discriminating the position of the main data signal and analog operation means for removing the main data signal component to reproduce the sub data signal, and the demodulated signal P.
And Q are multivalued through a + α radian phase shifter and a −α radian phase shifter, and the output data obtained is controlled by the sub data signal to reproduce the main data signal. Is characterized by.

Example of Invention

Next, an embodiment according to the present invention will be described with reference to the drawings.

1 and 2 are block diagrams showing a modulation side and a demodulation side of an embodiment according to the present invention, respectively, and FIG. 3 is a signal arrangement diagram of a composite modulated wave according to the embodiment of the present invention. An example using 16-valued quadrature amplitude modulation is shown. In FIG. 1, 1 and 2 are DA converters, 3 and 4 are low-pass filters, 5 and 6 are 0-π modulators, 7 is a π / 2 phase shifter, and 8 is 0-2α modulation. Unit 9 is a local oscillator. In Fig. 2, 10 is a quadrature detector, 11 to 14 are attenuators, and 15 and 16
Is a subtractor, 17 and 18 are adders, 19 is a sub-data signal reproduction signal, 20 is a low-pass filter, 21 to 25 are AD converters, 26 and 27 are logic circuits, and 28 is a voltage controlled oscillator. is there.

Explaining the modulation side, a conventional D / A converter 1, 2, low-pass filter 3, 4, 0-π modulator 5, 6, π / 2 phase shifter 7, local oscillator 9 is used. A 0-2α modulator 8 is added to a 16-value quadrature amplitude modulator. The code transmission rate of the sub-data signal D, which is the input of the 0-2α modulator 8, is selected to be 1 / m of the code transmission rate of the main data signal. As a result, the composite modulated wave obtained as the output of this quadrature amplitude modulator is as shown in FIG. In FIG. 3, the signal points represented by A1 to A16 represent the 0-2α modulator 8 in the 0 phase state, and the signal points represented by B1 to B16 represent the 0-2α modulator 8 in the 2α phase state. Represents the time. Signal points A1 to A16 and B
The phase difference between 1 and B16 is 2α. The signal points represented by C1 to C16 are signal points A1 to A16 and signal point B1, respectively.
~ Indicates the midpoint of B16.

Next, the demodulation side will be described. The composite modulated wave is quadrature detected by the quadrature phase detector 10 and becomes demodulated signals P and Q. The demodulated signals P and Q are reproduced into a sub data signal by the sub data signal reproducing circuit 19. Sub data signal reproduction circuit 19
Is a carrier recovery circuit for 16QAM, which is composed of analog circuits. If the input signal of the quadrature detector 10 is a 16QAM signal represented by the signal points C1 to C16 in FIG. 3, the sub data signal reproduction circuit, 19 output controls the voltage controlled oscillator 28 to reproduce the sub data signal. The circuit 19 operates as a carrier recovery circuit for 16QAM. Here, the input signal of the quadrature phase detector 10 is the signal points A1 to A16 and B1 to B16 which are shifted by ± α radian from the QAM signal at the signal points C1 to C16 in FIG.
Since it is a composite signal represented by, a binary signal corresponding to a phase of ± α radians, that is, a sub data signal is obtained at the output of the sub data signal reproducing circuit 19.

The low-pass filter 20 suppresses the thermal noise and residual jitter component of the main data signal contained in the output of the sub data signal reproduction circuit 19, and its band is selected near 1 / m of the main data signal speed. It The sub data signal reproduced by the sub data signal reproducing circuit 19 has a different signal level depending on the level of the main data signal, that is, ▲ ▼, ▲ in FIG.
There are three types represented by ▼ and ▲ ▼. Therefore, the above three types of signals are randomly included in one sub-data signal time slot corresponding to the main data signal m time slot, and the low-pass filter 20 has a function of averaging them. Is also necessary, and the band of the low-pass filter 20 is set in consideration of this. The output of the low-pass filter 20 enters the AD converter 25, where the sub-data signal D'of the binary digital signal.
Becomes

FIG. 4 shows an example of the sub data signal reproducing circuit 19,
5 is a full-wave rectifier circuit, 36-39 are phase shifters, 40-42 are subtractors, 43-
Reference numeral 45 is an analog switch, 46 is an adder, 47 is an exclusive OR circuit, 48 is a Q-selection circuit, and 49 is an amplitude modulator. Reference numeral 50 is a main signal position discriminating circuit. A circuit like this is
No. 698.

To briefly explain FIG. 4, reference numeral 50 is a circuit for determining the position of the main data signal included in the composite signal. As shown in Table 1, the main data signal is discriminated into four groups and the discrimination signal G1, Output G2, G4, G5. Next, with only the signal J obtained by multiplying the demodulated signals P and Q by two, the phase fluctuation and amplitude fluctuation components are included in the error signal finally obtained due to the difference of the preceding four groups included in the main data signal. , The signals K and M and the amplitude modulator 49 prepared so as to cancel the above-mentioned variation are selected and controlled by the position determination signal. Therefore, the signal H becomes a phase error signal for detecting the phase rotation component of the transmission carrier signal from which the 16QAM main data signal is completely removed.

The input signal in Fig. 4 is a composite modulated wave in which the transmission carrier signal is not only 16QAM modulated by the main data signal but also 2PSK modulated by the sub data signal.
The signal H becomes a sub data signal from which the main data signal is removed.

Incidentally, as the sub-data signal reproducing circuit 19, Japanese Patent Publication No. 58-69
The circuits of FIGS. 6 and 11 shown in No. 8 can be similarly used. In that case, a signal for controlling the voltage controlled oscillator may be used as the signal H.

The sub data signal is reproduced in this manner, and the discrimination margin of the signal level given to the sub data signal is represented by ▲ ▼ in FIG. 3 on average. On the other hand, the discrimination margin of the main data signal is represented by 2L. Therefore, in the example of FIG. 3, the main data signal is better by about 6 dB, but if about 8 is selected as the value of m described above, the low pass filter is selected.
A thermal noise improvement rate of 20 can be expected to be about 9 dB, and the code error rate characteristic of the sub data signal is about 3 dB from the main data signal.
You can get better.

Next, the means for reproducing the main data will be described with reference to FIG. Attenuators 11-14, Subtractors 15,16, Adders 17,18
Constitutes a + α radian phase shifter and a −α radian phase shifter. Taking the output of the subtractor 15 as an example, the attenuation amount of the attenuator 11 is selected as tan α, and the output of the subtractor 15 is represented by P · cos θ−Q · sin θ · tan α = K · cos (θ + α). , The signal P advanced by α radians compared to the demodulated signal P
It becomes _{+ α} . Similarly, at the output of the adder 17, the demodulated signal P
The signal P- _α delayed by α radians, the output of the adder 18 is a signal Q _{+ α} advanced by radians from the demodulated signal Q, and the output of the subtractor 16 is a signal Q- _α delayed by radians from Q.

Here, the signals P _−α and Q _−α are the signal points in FIG.
In the case of A1 to A16, it is a four-valued signal with values of ± 3L and ± 1L.
Therefore, if the A-D converters 21 and 24 perform multi-level discrimination at the discrimination levels of 0, ± 1L, ± 2L, and ± 3L, the main signal for the signal points A1 to A16 can be reproduced. Similarly, the signals of P _{+ α} and Q _{+ α} are four-valued signals having values of ± 3L and ± 1L for the signal points B1 to B16 in FIG. Therefore, the A-D converters 22 and 23
By performing multi-level discrimination at the discrimination levels of 0, ± 1L, ± 2L, and ± 3L, the main signal at the signal points B1 to B16 can be reproduced.
Therefore, when the input signal is A1 to A16, the AD converter 21 uses the auxiliary data signal output from the AD converter 25 which serves as a signal for discriminating the signal points A1 to A16 and B1 to B16 in the logic circuit 26. , 24 outputs are selected. On the other hand, when the input signals are B1 to B16 and the outputs of the AD converters 22 and 23 are selected, the main data signals X1 ', X2', Y1 'and Y2' are reproduced at the output of the logic circuit 26.

Here, as described above, the bit error rate characteristic of the sub data signal is better than that of the main data signal, so that the effect of the error of the sub data signal added to the main data signal can be ignored. Of the outputs of the logic circuit 26, X1 ', X3', Y1 ', Y3' enter the logic circuit 27, where a carrier error signal is created. By controlling the voltage controlled oscillator 28 with the output of the logic circuit 27, a carrier phase locked loop is formed. The operation of the phase-locked loop including the logic circuit 27 is described in detail in "Carrier Regeneration Circuit" (Japanese Patent Laid-Open No. 57-131151) by the applicant of the present invention, and a detailed description thereof is omitted.

FIG. 5 shows the configuration of another embodiment of the modulation side according to the present invention, and the same parts as in FIG. 1 are given the same numbers. Five
1, 52 is a ROM, and 53, 54 are DA converters. Main data signal X
1, X2, Y1, Y2 and the sub data signal D enter the ROMs 51,52, in which the DA converters 53,54 necessary to obtain the signal points A1 to A16 and B1 to B16 in FIG. Converted to an input data string. The more bits required for the ROMs 51, 52 and the DA converters 53, 54, the more accurate the complex modulated wave can be obtained, but in the case of 16 levels, about 8 bits seems to be sufficient. According to this embodiment, the circuit scale is of course smaller than that of FIG. 1, but there is no need for timing between the sub-data signal and the main signal, and the band limitation is commonly performed. It has the advantage that it can.

In the embodiments, the modulation method of the main signal has been described as 16-value quadrature modulation, but the present invention has 16 values or more, that is, 32 values.
It goes without saying that the same can be applied to values, 64 values, 256 values ... In that case, the number of bits of the D-A converter and the A-D converter is increased, and the values of α and m are further set to the sub-data signal reproducing circuit and the analog carrier wave corresponding to the multi-valued number of the main data signal. Change to a playback circuit. Further, it is not necessary that the sub data signal and the main data signal are synchronized in timing, and they operate even in an asynchronous state.

〔The invention's effect〕

As apparent from the above description, according to the present invention,
Modulation phase shift amount of the sub-data signal alpha, by selecting the values of the ratio m of the code transmission rate f ₂ of the code rate f ₁ and the sub-data signal of the main data signal properly, the bit error rate of the main data signal The sub data signal can be transmitted without deteriorating the characteristics. In the case of 16 values, it is possible to reduce the value of m to about 8, and the effect obtained by this is great.

[Brief description of drawings]

1 and 2 are block diagrams showing the configurations of the modulation side and the demodulation side, respectively, of an embodiment according to the present invention, and FIG.
4 is a block diagram of the sub data signal reproducing circuit in FIG. 2, FIG.
FIG. 5 is a block diagram showing the configuration of another embodiment on the modulation side according to the present invention. In the figure, 1,2,53,54 are DA converters, 3 and 4 are low-pass filters, 5 and 6 are 0-π modulators, 7 is a π / 2 phase shifter, and 8 is 0- 2α modulator, 9 is a local oscillator, 10 is a quadrature detector, 11 to 14 are attenuators, 15 and 16 are subtractors, 17 and 18 are adders, 19 is a sub data signal reproduction circuit, and 20 is a low frequency band filter. Waveforms, 21 to 25 are A / D converters, 26 and 27 are logic circuits, and 28 is a voltage controlled oscillator.

Claims (1)

[Claims] 1. A quadrature amplitude modulation wave modulated by a main data signal having a code transmission rate f _{1 is} transmitted to a modulation side at a code transmission rate f ₂ (f ₁ >
f ₂ ) is provided with means for obtaining a complex modulated wave by 2α radian phase modulation with a sub data signal, and means for obtaining demodulated signals P and Q by quadrature phase detection of the complex modulated wave on the demodulation side, and at least the demodulated Means for discriminating the position of the main data signal using the signals P and Q and means for removing the main data signal component by an analog calculating means to reproduce the sub data signal, and the demodulated signals P and Q being + α radian. A multi-valued discriminator via a phase shifter and a -α radian phase shifter, and means for controlling the output data obtained by the sub data signal to reproduce the main data signal. Transmission system.