JPH0214781B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit, and more particularly, to a semiconductor integrated circuit in which circuit elements that require a high withstand voltage and circuit elements that require a low resistance are simultaneously integrated on a dielectric isolation substrate. It is related to.

An example of the use of circuit elements that require a high breakdown voltage and circuit elements that require a low resistance will be explained using a thyristor dv/dt protection circuit shown in FIG.

In Figure 1, 1 is a thyristor consisting of four layers P _E , n _B , P _B , n _E , and between the gate and cathode terminals G and K is a thyristor consisting of three layers n _C , P _B , n _E . A transistor 2 is connected to the collector and emitter terminals C, E, and a resistor 3. A capacitor 4 is connected between the anode terminal A of the thyristor and the base terminal B of the transistor 2, and the cathode terminal K of the thyristor 1 or Emitter terminal E of transistor 2
A diode 5 is connected between the base terminal B of the transistor 2 and the base terminal B of the transistor 2. When a voltage with a steep rising rate is applied between the anode and cathode terminals A and K of thyristor 1, a displacement current flows into the P _B layer through the reverse bias Pn junction between n _B and P _B of thyristor 1, The potential of the P _B layer increases. If this potential is higher than the built-in voltage between the P _B layer and the n _E layer, carriers are injected from the n _E layer to the P _B layer, causing thyristor 1 to turn off even though no gate signal is applied to the gate terminal G. arc This phenomenon is called the rate effect, and the quality of the thyristor 1 is determined by the rate of change in voltage dv/dt that does not cause ignition, and this value is called the dv/dt withstand capacity. However, in the protection circuit shown in FIG. 1, the charging current is also supplied to the base terminal B of the transistor 2 via the capacitor 4, so the transistor 2 becomes conductive and the gate and cathode terminals G and K of the thyristor 1 are connected. short-circuit between Therefore, the displacement current in the P _B layer of the thyristor 1 is diverted to the cathode terminal K via the transistor 2, and the thyristor 1 is prevented from erroneous firing due to the rate effect. The higher the saturation degree of the transistor 2, the higher the short circuit effect and the higher the dv/dt tolerance. On the other hand, when a voltage with a steep rise is not applied, transistor 2 is non-conducting, so the gate signal does not bypass transistor 2. If resistor 3 is set to a high resistance, the gate signal is almost at the point of thyristor 1. Since it is used as an arc signal, the gate sensitivity is good. Note that the diode 5 is provided to form a discharge circuit for the electric charge in the capacitor 4.

Recently, the voltage resistance of the thyristor 1 has been steadily increasing, and the dv/dt resistance has also tended to increase.
Increasing the breakdown voltage of thyristor 1 is achieved by increasing the specific resistance of the _nB layer, etc., and increasing the dv/dt withstand capability is achieved by reducing the saturation resistance of transistor 2, that is, the specific resistance of the _nc layer. be done.

In semiconductor integrated circuits, n _B of thyristor 1
In some cases, the n _c layer of transistor 2 and the n c layer of transistor 2 have the same specific resistance, and it has been difficult to achieve high breakdown voltage and high dv/dt capacity at the same time with the protection circuit shown in FIG.

Therefore, a detailed explanation will be given based on an example shown in FIG. 2 in which a thyristor 1 and a transistor 2 are integrated using a conventional semiconductor integrated circuit.

In FIG. 2, reference numeral 10 denotes a dielectric insulating isolation substrate, which has single crystal silicon island regions 11 and 12.
It is insulated and supported by a polycrystalline silicon support region 15 via dielectric films 13 and 14 such as SiO ₂ . The upper main surfaces of both island regions 11 and 12 are embedded in a manner that coincides with the upper main surface of the support region 15, so to speak, and have a structure similar to an inlay in maki-e.

Both island regions 11 and 12 have n-type conductivity, and impurities such as acceptors and donors are selectively diffused from the upper main surface to form the island region 11.
A thyristor 1 shown in FIG. 1 is formed in the island region 12, and a transistor 2 is formed in the island region 12. A high impurity concentration layer n ⁺ in which donors are diffused at a high concentration is provided in both the island regions 11 and 12 at the portions where the island regions 11 and 12 and the dielectric films 13 and 14 are in contact with each other.

A surface stabilizing film 16 such as SiO ₂ is provided on the upper main surface of the substrate 10 .
Wirings 17 to 23 made of Al or the like provided on the surface stabilizing film 16 are in ohmic contact with each layer as terminals through the openings provided in 6. Wiring 2
0,23 and n ⁺ layer to connect n ⁺ layer 24,
25 are provided. In both island regions 11 and 12, portions corresponding to the respective layers of thyristor 1 and transistor 2 in FIG. 1 are given the same reference numerals.

Next, the breakdown voltage of the thyristor 1 will be explained.

When a negative voltage is applied to the P _E layer relative to the n _E layer via the wiring 17 and the wiring 19, a depletion layer that blocks most of the voltage is formed across the P _E layer and the n _B layer. Ru. The better the spread of the depletion layer in the _nB layer is, the more a high breakdown voltage can be prevented, so the higher the specific resistance of the _nB layer, the better. On the other hand, the depletion layer in the _nB layer is stretched toward the right in the figure as shown by the dotted line due to the electric field effect of the wiring 17, and when it reaches the dielectric film 13, the stretching stops and breakdown occurs. Furthermore, when a channel 26 is formed at the same time and reaches the dielectric film 13, leakage current increases.

The problem with this problem is that the n ⁺ layer acts as a channel stopper, and although the channel is stopped, the electric field is concentrated in this part, so it is necessary to make the surface stabilizing film 16 thicker in order to prevent this. For example, in order to prevent a withstand voltage of about 500V, the surface stabilizing film 16 needs to have a thickness of 3.5 to 4 μm, and providing such a film thickness has various disadvantages when manufacturing semiconductor integrated circuits. be.

Next, saturation resistance in transistor 2 will be explained.

Although there are various methods for manufacturing the dielectric insulating isolation substrate 10 itself, such as a single poly method and a double poly method, n-type single crystal silicon wafers are often used as the starting material.

As an example, the single poly method will be explained.

First, an n-type single crystal silicon wafer is prepared,
A grid-like V-shaped separation groove is formed on one main surface side. After an n ⁺ layer is formed on the entire surface of this main surface by diffusion or the like, a dielectric film is deposited. Second
In the figure, the dielectric films 13 and 14 are shown divided, but at this stage they are continuous. Next, a polycrystalline silicon support region 15 is grown in vapor phase on this dielectric film. Further, the silicon wafer is removed from the other main surface of the silicon wafer by polishing or the like. If the removal operation is stopped when the bottom of the V-shaped isolation groove is exposed, a dielectric insulation isolation substrate 10 as shown in FIG. 2 is obtained.

In other words, the n _B layer of thyristor 1 and transistor 2
The n _c layers have the same resistivity. Furthermore, the thicknesses of the island regions 11 and 12 measured from the upper main surface are also the same.

Most of the saturation resistance in transistor 2 is n _c
It is the resistance in the layer, and if the impurity concentration of the _nc layer is high and the thickness is thin, the saturation resistance becomes small. The n ⁺ layer in the island region 12 constitutes a part of the _nc layer and contributes to reducing this saturation resistance, but if the _nc layer is designed around the _nb layer of thyristor 1, the overall As a result, the saturation resistance had to be high, and when applied to a protection circuit as shown in Figure 1, sufficient dv/dt tolerance could not be obtained.

P _B layer in thyristor 1 and transistor 2
The saturation resistance in transistor 2 can be reduced by creating the P _B layer in a separate diffusion process and increasing the thickness of the P _B layer in transistor 2, but such a method complicates the manufacturing process, so it is not a good solution. I can't say it.

Therefore, it is an object of the present invention to provide a semiconductor integrated circuit in which high-voltage circuit elements and low-resistance circuit elements are simultaneously integrated.

A feature of the present invention that achieves the above object is that both the high impurity concentration layer n ⁺ adjacent to the dielectric film and the semiconductor layer adjacent to this layer (e.g. _nB layer or _nc layer) The point is that a semiconductor layer with an intermediate impurity concentration is provided.

This intermediate impurity concentration layer serves as an electric field relaxation layer in circuit elements that require high breakdown voltage, and serves as a resistance reduction layer in circuit elements that require low resistance. Another advantage is that this intermediate impurity concentration layer can be formed at the same time as the dielectric insulation isolation substrate.

FIG. 3 shows an embodiment of the present invention.
The same reference numerals as in FIG. 1 and FIG. 2 indicate the same elements, and the semiconductor layer indicated by n in the figure is the intermediate impurity concentration layer according to the present invention.

In the island region 11, the wiring 20 is in ohmic contact with the n layer, but the wiring 17 to 1 such as the anode
9 has no ohmic contact. Therefore, the n layer serves as an electric field relaxation layer, and the n ⁺ layer serves as a channel stopper. In other words, since the n layer has a lower impurity concentration than the n ⁺ layer, when a reverse bias voltage is applied between the P _E layer and the n _B layer, the depletion layer formed in both layers is
It does not stop within the n layer but terminates within the n ⁺ layer. n layer is n _B
Since the impurity concentration is higher than that of the depletion layer, the amount of extension of the depletion layer is reduced. Therefore, the termination does not occur abruptly in the n ⁺ layer, and the electric field is relaxed.

In the island region 12, the n layer is in ohmic contact with the wiring 23 which becomes the collector terminal, so current flows from the n ⁺ layer and the n layer to the n _c layer. Since the thickness of the _nc layer is reduced by the amount of the n layer, and the specific resistance of the n layer is reduced, the saturation resistance of the transistor 2 formed in the island region 12 is reduced.

Therefore, if the dv/dt protection circuit of the thyristor shown in Fig. 1 is integrated using a dielectric isolation isolation substrate as shown in Fig. 3, the dv/dt of the thyristor with high withstand voltage and high dv/dt withstand capacity can be reduced. It becomes possible to obtain a protection circuit.

FIG. 4 shows an example of measuring the withstand voltage of the thyristor 1, and it can be seen that in this example, the withstand voltage is improved by about 60 V compared to the conventional example shown in FIG.

FIG. 5 shows the relationship between collector saturation voltage and current in transistor 2. In the figure, curve A is based on the conventional example shown in FIG. 2, and curve B is based on the present invention shown in FIG. Saturation resistance is approximately 1/
It can be seen that the number has been reduced to 2.

When comparing the dv/dt tolerance, the conventional example
500V/μs, but according to the present invention, it is 2000V/μs.
It was confirmed that the speed was improved to μs.

Next, a method of manufacturing the dielectric insulating isolation substrate shown in FIG. 3 will be explained according to the single poly method.

As shown in FIG. 6a, an n-type conductive single crystal silicon wafer 31 is prepared and thermally oxidized to form an oxide film 32. As shown in FIG. Openings are provided by a known selective etching method, and phosphorus is diffused through the openings to form the n-layer 33.

Next, as shown in FIG. 6b, an oxide film 34 is formed by thermal oxidation again, an opening is formed by a known selective etching method, and the silicon wafer 31 is selectively etched from this opening using an alkaline etching solution. Then, a V-shaped separation groove 35 is formed.

Next, as shown in FIG. 6c, phosphorus is diffused using the oxide film remaining on the silicon wafer 31 as a mask to form an n-layer 36. Both n-layers 33,
36 corresponds to the n layer in FIG. 3, and it goes without saying that the impurity concentration is higher than that of the silicon wafer 31.

Next, as shown in FIG. 6d, the oxide film 34 on the silicon wafer 31 is removed and antimony is diffused over the entire surface to form an n ⁺ layer 37. The n ⁺ layer 37 corresponds to the n ⁺ layer in FIG.
The impurity concentration is higher than that of

Next, as shown in FIG. 6e, the silicon wafer 3 is
An oxide film 38 serving as a dielectric film is formed on the oxide film 1, and a polycrystalline silicon support region 39 is further grown in a vapor phase on the oxide film 38. After that, the position shown in the dashed line A-A,
That is, the silicon wafer 31 is polished until the bottom of the separation groove 35 is exposed.

FIG. 6f shows the dielectric insulating isolation substrate 40 in which the vertical relationship has been reversed after polishing.

As explained above, the n-layer, which serves as an electric field relaxation layer and a resistance reduction layer, is provided during the process of manufacturing the dielectric insulation isolation substrate 40, so even if such a layer is included, the semiconductor integrated circuit The manufacturing process is not complicated.

Note that although an n-type conductive silicon wafer 31 is prepared as a starting base material, it may be of p-type conductivity. At this time, each of the semiconductor layers 33, 36, and 37 has P-type conductivity.

As described above, according to the present invention, circuit elements that require high breakdown voltage and circuit elements that require low resistance can be easily integrated using the same dielectric isolation substrate.

[Brief explanation of drawings]

Figure 1 is a connection diagram of the thyristor dv/dt protection circuit, and Figure 2 is the thyristor dv/dt shown in Figure 1.
FIG. 3 is a partial longitudinal cross-sectional view of a dielectric insulation isolation substrate in which a protection circuit is integrated according to a conventional example; FIG. Figure 5 shows the dv/dt of the thyristor shown in Figure 1 using the dielectric isolation isolation substrate shown in Figure 3.
Figures 6a to 6 are diagrams showing the relationship between the withstand voltage in a thyristor and the collector saturation voltage and collector current in a transistor when a protection circuit is integrated.
FIG. f is a diagram showing the manufacturing process of the dielectric insulation isolation substrate shown in FIG. 3. 10... Dielectric insulation isolation substrate, 11, 12...
Single crystal silicon island region, 13, 14... dielectric film, 15... polycrystalline silicon support region, 16...
Surface stabilizing film, 17-23...wiring.

Claims (1)

[Claims] 1 A plurality of single-crystal silicon island regions of one conductivity type are buried in a support region through a dielectric film so that the main surface of each island region is exposed, and impurities are diffused into the island region from the main surface side. A circuit element is formed, a surface stabilizing film is provided on the main surface of the island region, and wiring is provided on the surface stabilizing film to make ohmic contact with a predetermined area of the circuit element through an opening provided in the film. In the semiconductor integrated circuit, the plurality of island regions have at least a first silicon layer of one conductivity type and a higher impurity concentration than the island region, sequentially from the dielectric film side over the entire portion adjacent to the dielectric film. and a second silicon layer of one conductivity type having a lower impurity concentration than the first silicon layer and a higher impurity concentration than the island region, and the entire portion adjacent to the dielectric film. a third silicon layer of one conductivity type and having a higher impurity concentration than the island region; 1. A semiconductor integrated circuit comprising a second island region provided with a fourth silicon layer having an impurity concentration lower than that of the third silicon layer and higher impurity concentration than the island region.