JPH0214817B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to an encoding/decoding processing device in an information storage device or the like.

BACKGROUND ART Conventionally, in this type of device, as shown in FIG. 3, an input terminal 1 into which an information code is input;
A division circuit 2 that generates a test code from the information code input to this input terminal 1;
The encoding circuit A is controlled by the encoder control circuit 4 and the selector 5 which switches between the inspection code outputted from the output line 3 and the information code inputted from the input terminal 1 and outputs the encoded code from the output line 6. While the encoding process is performed by configuring the information code and adding a check code to the information code, there is an input terminal 7 into which the encoded code is input, and a syndrome is detected from the encoded code input to this input terminal 7. a correction circuit 11 that performs a correction process on the syndrome outputted from an output line 9 of this calculation circuit 8 and the encoded code and outputs an information code from its output line 12; The control circuit 10 constitutes a decoding circuit B, and decoding processing is performed.

Problems to be Solved by the Invention However, according to the configuration of the conventional device described above, the encoding process and the decoding process are performed in separate circuit configurations, so separate control is required for both circuits. In addition, since a division circuit is used to generate the check code, there is a problem in that the circuit scale of the division circuit and syndrome calculation circuit becomes enormous for code words that handle symbols with a large number of constituent bits.

The present invention has been made in view of the above-mentioned problems, and it is an object of the present invention to provide an encoding/decoding processing device that does not require an enormous circuit scale.

Means for Solving the Problems In order to solve the above problems, the present invention uses a generation matrix (G-Matrix) and a check matrix (H-Matrix).
Matrix) table in a read-only memory (ROM), and the encoding and syndrome calculations are performed in the same circuit.

Effect: In other words, according to the present invention, the above-described configuration allows encoding and decoding processing to be combined into one circuit, thereby making it possible to significantly reduce the circuit scale.

Embodiment Hereinafter, the present invention will be explained based on an embodiment shown in FIGS. 1 and 2.

FIG. 1 shows a schematic configuration of an encoding/decoding processing device according to the present invention, in which 21 is an input terminal for an information code or an encoded code, 22 is a circuit for encoding and syndrome calculation, and 23 is a generation matrix and check ROM in which the matrix table is stored, 24
25 is a selector that switches and outputs the information code and the test code during encoding; 26 is an output terminal for the encoded code from the selector 25; 27 is a control circuit; 28
2 is a circuit that performs a correction operation during decoding, and 29 is an output terminal for the information code.

The operation of the encoding/decoding processing device configured as described above will be explained below. First, during encoding, when an information code is input to the input terminal 21, the encoding circuit 22 performs a matrix product operation of the information code and the generation matrix (G-Matrix) stored in the ROM 23, and the check code is is generated and output from the output line 24, and the selector 25 is switched by the control circuit 27,
Following the information code, a check code is output from the output terminal 26 as an encoded code. On the other hand, when an encoded code is input to the input terminal 21 during decoding, the syndrome calculation circuit 22
A matrix product operation of the check matrix (H-Matrix) stored in 3 and the encoded code is performed, a syndrome is generated, and the information code is sent to the output terminal by the correction circuit 28 controlled by the control circuit 27. 2
It is designed to be output from 9.

As described above, the encoding and syndrome calculation circuit 22 performs matrix product operations, and FIG. 2 shows a schematic configuration of an example in which four symbols of test codes or syndromes are generated. That is, the second
As shown in the figure, an information code or an encoded code is input to the input terminal 31, and a generation matrix (G-
When each element of the check matrix (H-Matrix) or check matrix (H-Matrix) is input to the input terminal 32, the multiplication circuit 33
The product is outputted to the product term output line 34 by . In addition, the latches 37 to 40 sequentially store the calculation results up to that point every four symbols, and add the next product term whose output passes through the selector 41 and is output to the output line 34 by the adder circuit 35. Then, the symbols are sequentially outputted to the output line 36, the results are sequentially stored again in the latches 37 to 40, and the test code or syndrome is outputted to the output terminal 42 to perform the matrix product operation. .

Effects of the Invention As is clear from the above explanation, the present invention has a table of generation matrices and check matrices in ROM, and enables encoding and decoding by performing encoding and syndrome calculation in the same circuit. Since the conversion processing is combined into one circuit,
This has the effect of significantly reducing the circuit scale.

[Brief explanation of drawings]

FIG. 1 is a schematic circuit configuration diagram of an embodiment using the encoding/decoding processing method according to the present invention, FIG. 2 is a schematic diagram of the main part of the encoding and syndrome calculation circuit, and FIG. FIG. 2 is a schematic circuit configuration diagram of an encoding/decoding processing device. 21... Input terminal for information code or encoded code, 22... Encoding and syndrome calculation circuit, 23... Generation matrix and check matrix table
ROM, 24...Test code and syndrome output line, 25...Selector, 26...Encoded code output terminal, 27...Control circuit, 28...Correction circuit, 29...Information code output terminal, 31...Information Code or encoded code input terminal, 32... Generation matrix and parity check matrix element input terminal, 33... Multiplication circuit, 34... Output line, 35... Addition circuit, 36
...Sequential symbol output line, 37-40...Latch, 41...Selector, 42...Test code or syndrome output terminal.

Claims (1)

[Claims] 1. An input means for selectively inputting an information code or an encoded code, and a product operation of the information code or encoded code inputted from this input means and a generation matrix or a check matrix, and a test code or syndrome an arithmetic means for performing calculations, a storage means for storing the generation matrix and the check matrix, and a switching means for switching between the information code and the check code output from the arithmetic circuit;
An encoding/decoding processing device comprising: a correction means for correcting the encoded code based on the syndrome output from the arithmetic circuit.