JPH0214821B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a decoding device that decodes an original multi-value time-series signal from a coded signal obtained by compression-encoding a sampled multi-value time-series signal whose frequency of occurrence is biased.

Multi-value time-series signals obtained by sampling image signals and audio signals generally have a bias in the frequency of occurrence of each multi-value signal. PCM (pulse code modulation) obtained by A/D conversion of analog image and audio signals
Although the deviation in occurrence frequency of signals is not so large, for example, a multilevel signal obtained by converting a PCM signal to a DPCM (differential pulse code modulation) signal generally exhibits a zero-concentrated frequency distribution. That is, signals with a difference value close to 0 occur frequently, and signals with a large difference value occur less frequently. Signals with uneven occurrence frequency can be compressed and encoded by unequal length coding in which short codes are given to signals with high occurrence frequency and long codes are given to signals with low occurrence frequency.

The problem with unequal length encoding is that the decoding circuit becomes complex. In particular, the sampling frequency of sampled multivalued time series signals such as television signals is
At a high speed of 10 MHz, the decoding circuit for unequal length codes has a limit to its operating speed, so serial arithmetic processing cannot be applied, making it even more complex.

In other words, conventionally, as a method to avoid the speed limit of decoding operation, when a compressed code is received from the transmission path, it is immediately decoded into a feature code, and the result is temporarily stored in a large-capacity buffer memory and used for subsequent processing. The method was used. Since this method stores decoded data in the buffer memory, it requires several times to several tens of times more memory than the case where compressed data before decoding is stored in the buffer memory as in the present invention. In addition, it is necessary to separately install a monitoring mechanism for the amount of buffer memory accumulated.
The circuit was quite complex, requiring a mechanism to guarantee the decoding speed for the minimum compression ratio.

An object of the present invention is to provide a decoding circuit that is capable of high-speed operation and has a simple circuit configuration.

According to the present invention, compressed data is read out as parallel l-bit data, a synchronization code is directly detected from this parallel data series, and unequal-length codes individually separated from parallel l-bit data are array-converted as parallel data. Therefore, high-speed operation is possible,
Moreover, since the unequal length code array inversion circuit is specially devised, code inversion can be realized with a simple circuit. In addition, even when multiple time series data are restored from codes that are multiplexed and compressed, the unequal length code array inversion circuit can be used in common for these multiple compressed data. The entire circuit configuration is simplified. Furthermore, any code that can be distinguished from other compression codes can be used as the synchronization code that indicates the delimitation of blocks, so it is highly flexible.

Next, the present invention will be explained in detail with reference to the drawings.

1 and 2 are a block diagram and a timing chart showing an encoding device used in the present invention.

Although the device of the present invention can be applied to sampled time-series signals such as image signals and audio signals, a television signal will be explained here as an example. First, the television signal supplied to input terminal 1 is a multi-level time series signal (second
In step S4) in the figure, the DPCM encoder 2 converts the signal and outputs it to the signal line 100. At this time, a synchronization timing signal (S3 in FIG. 2) and a sampling clock pulse (S1 in FIG. 2) are simultaneously output to signal lines 103 and 102. This synchronization timing signal S3 is information representing the division of blocks for dividing time series data into blocks of a certain length and compressing and encoding them.

Now, the encoding device shown in FIG. 1 includes a timing control circuit 3, a first code allocation circuit 5 that allocates a first code (hereinafter referred to as R code), and a second code (hereinafter referred to as V code). a second code allocation circuit 4 that allocates the first and second codes, a multiplexing circuit 6 that multiplexes these first and second codes, and an unequal length code that rearranges the unequal length codes in the order of occurrence and converts them into parallel l-bit data. It is composed of a code array conversion circuit 7. Note that reference numeral 8 is a memory that stores data converted by this encoding device. When using the encoding device by incorporating it into a communication device through a line,
The memory 8 is used as a buffer memory for speed smoothing, and the contents of the memory are read out in parallel at a speed of 1/l of the line speed, converted into serial codes, and output to the line. Further, when this encoding device is used as a part of input means for a data file included in a computer device or the like, the memory 8 is used as a computer memory or an interface memory. Here, the first code R is a code representing the run length of the most frequently occurring value in time series, and the second code V is a code representing the value (level) of the multilevel signal. Further, each of the R code and the V code includes at least one transition code. These are respectively referred to as a first transition code (hereinafter referred to as R ^* code) and a second transition code (hereinafter referred to as V ^* code). The R ^* code is a code that indicates a transition from the R code to the V code, and the V code is sent out after the R ^* code in time series. Further, the V ^* code is a code indicating a transition from the V code to the R code, and the R code is sent out after the V ^* code. For codes other than transition codes, the R code is followed by the R code, and the V code is followed by the V code.

FIG. 3 shows an example of the code V for signal levels 0 to 5 of the multilevel signal. Signal level 0, i.e.
For the most frequently occurring value, in addition to the transition code V ^* ₀ , a non-transition code V ₀ is given.

The V code is assumed to be an unequal length code with a code length of 2 to 4 as shown in the figure. An unequal length code is a code that has the characteristic that if the beginning of the code is known, the length of the code or the end of the code can be determined from the time series of the code. In Figure 3,
For example, a code that starts with 1 is the code V ^* ₀
There are only two codes, "11" of code _V1 and "10" of code V1, both of which have a code length of 2. Further, the _only code that continues with "011" is code V2 with a code length of 3. The code is “00…”
Or, if it becomes "010...", the code length will be 4.

FIG. 4 shows an example of the R code for the run length of the most frequently occurring signal value. Here, the R code is also assigned an unequal length code with a code length of 2 to 4. The codes representing run lengths from 0 to 7 are respectively
R ^* ₀ to R ^* ₇ and these are transition codes. The code R8 whose run length represents ₈ is not a transition code. In the present invention, it is also possible to define all run-length codes as transition codes, but generally, as the run length increases, the number of types of codes that represent it increases, and the code generation circuit becomes complex. For this reason,
In the present invention, as shown in FIG. 4, a non-transition code and a transition code are used to encode a large run length. For example, using the non-transition code R ₈ , run length 8 can be expressed as R ₈ + R ^* ₀ , run length 10 can be expressed as R ₈ + R ^* ₂ ,
In the example of FIG. 4, run lengths from 0 to 15 can be represented by nine types of codes.

Note that a larger run length can be expressed by increasing the number of non-transition codes as necessary.

The method of determining unequal length codes as shown in FIGS. 3 and 4 is actually to obtain statistics of the frequency of occurrence of each signal level and each run length for the target image signal, For example, Huffman codes are assigned to these probability distributions. Thereby, the overall amount of compressed codes can be minimized.

Next, the configuration and operation of each part 3 to 7 of the present invention will be explained in order. For ease of explanation, the input multi-level time series signal 100 is expressed in six levels from 0 to 5. The most frequently occurring signal value is assumed to be 0 level. In other words, the signal line 100 is composed of 3-bit parallel data lines, and has 0 to 5 bits.
It is assumed that the signal levels up to are expressed in binary numbers 000, 001, . . . , respectively.

FIG. 5 is a diagram showing a specific circuit of the timing control circuit 3. In the figure, an OR gate 31 determines whether or not the level of a multi-level time series signal having levels from 0 to 5 is 0, which is input through a signal line 100, and a delay adjustment register 34 performs delay adjustment to signal the signal. It is output as the most frequently occurring signal to line 101 (S5 in FIG. 2). In Fig. 2, it is assumed for simplicity that there is no input signal to be encoded at times t ₀ and t ₁₄ , where there is a synchronization timing (such encoding is often not performed during the blanking period of television signals). ) At this time, the most frequently occurring signal is set to 1 (high level). The output of the OR gate 31 is delayed by one clock by a one clock delay register 32 and then applied to the OR gate 35. The OR gate 35 performs an OR operation on this signal and the undelayed original signal (S6 in FIG. 2), and supplies this signal through a signal line 203 to a timing pulse generator 33 consisting of a register and a gate. The timing pulse generator 33 is
A timing pulse for code generation (S6 in FIG. 2) using the signal on the signal line 203 and the clock pulse;
Timing pulse for transition code V ^* generation (Fig. 2 S
7) Generate an R code generation timing pulse (S8 in FIG. 2) and a transition code R ^* generation timing pulse (S9 in FIG. 2) on signal lines 104 to 107. Here, S7 is 1 just before the falling edge of S6.
Clock minutes (however, omitted after t1S), S8 is S6
S9 corresponds to two clocks immediately before the rise of S6, and S9 corresponds to one clock immediately before the rise of S6. In addition, the multilevel time series signal S4 and the synchronized timing signal S3
Also, the delay is adjusted by the delay adjustment register 34 and output to the signal lines 110 and 113, respectively. The delay adjustment register 34 is used to compensate for delays caused by waveform processing in the timing pulse generator 33. In addition, the second
Timing pulses S6, S7, S8 and S in the figure
9 shows the state after each delay adjustment, and the relative time relationships of the signals S1 to S9 are described so as to be correct when viewed from the output of the timing control circuit 3.

That is, the waveforms of S3, S4, and S5 are the waveforms of signal lines 113, 110, and 101, respectively. Multi-level time series signal 110 and V code generation timing pulse S6 generated by timing control circuit 3
and the transition code V ^* generation timing pulse S7 are supplied to the second code generator 4 of FIG. Second
The code generator 4 generates a V code on its output signal line 120 in response to the timing pulse, and generates a V code on its output signal line 120.
A binary code indicating the code length of the V code is generated at 21. Further, the most frequently occurring signal R code generation timing pulse S8 and the transition code R ^* generation timing pulse S9 from the timing control circuit 3 are supplied to the first code assignment circuit 5. The first code assignment circuit generates an R code on its output signal line 130 in response to a timing pulse by changing the number of connected 0's in the most frequently occurring signal S5.
A binary code indicating the code length of the R code is generated at 1.
The V code and the R code are controlled by timing pulses S6 and S8 so that they do not occur at the same time.

The V code and R code generated on the signal line 120 and the signal line 130 are time-division multiplexed by the multiplexing circuit 6.
Similarly, binary codes indicating the code length generated on the signal line 121 and the signal line 131 are also time-division multiplexed by the multiplexing circuit 6. The multiplexing circuit 6 further includes a signal line 113.
An unequal length code M (S10 in FIG. 2) obtained by time-division multiplexing the synchronization code S into R and V codes in accordance with the synchronization timing pulse supplied through the signal line 140.
Output to. Similarly, for the binary code indicating the code length, a code length signal N (S1 in FIG.
1) is output to the signal line 141.

In S10 of FIG. 2, the symbol X indicates an arbitrary code, and the fact that the number of effective codes in S11 of FIG. 2 is 0 indicates that there is no meaningful unequal length code at that time.

Here, the combination of the V code and the R code in S10 in FIG. 2 will be explained. This example works according to the following rules:

(1) Give a code V _k (k=1 to 5) that does not transition if the multilevel time series signal has a value other than the most frequently occurring value.

(2) For the first most frequent value where the multi-level time series signal changes from a value other than the most frequent value to the most frequent value, (a) when the second signal is the most frequent value, the transition code V ^* ₀ is set. give,
(b) When the second signal is not the most frequently occurring value, give a code V ₀ that does not transition.

(3) For two or more consecutive most frequently appearing values, the run length excluding the first most frequently appearing value is expressed by an R code.

(4) R code is R ^* ₁ ~ when the run length is 1 to 7.
It is represented only by a transition code of R ^* ₇ , and when the run length is 8 to 15, it is represented by a combination of a non-transition code _R8 and a transition code of R ^* ₀ to ^R* ₇ .

(5) The beginning of the block shall be a V code.

This rule is called Rule 1.

In FIG. 2, at times t ₁ , t ₂ , t ₃ , t ₈ and t ₁₀
Since the value is other than the most frequent value, Rule 1
(1) gives the V _k code as shown in S10 of FIG. At times t ₄ and t ₁₁ , the transition code V ^* ₀ is given by rule 1 (2) (a), and the time
At t ₉ , non-transition code V ₀ is given by (b) of (2). The most frequently occurring value signal from time t ₅ to _{t 7} is Rule 1 (3)
and (4), R ^* ₃ where the run length is 3
This code is output at time _t7 as shown in S10 of FIG. The same applies to times _t12 to _t13 . Although not shown in this figure,
When the run length is 8 or more, a transition code is output at the time of the last most frequently occurring value signal, and a non-transition code is output one clock before that. Times t ₁ and t ₁₅ correspond to the beginning of the block, and according to Rule 1 (5), they are given a V code. At this time, time t ₁₅
When the top of the block is the most frequently occurring value, as in the case where the most frequently appearing value is at time _t16 , a V ^* ₀ code is given, and if it is not the most frequently occurring value, a _V0 code is given.

FIG. 6 is a diagram showing a specific circuit of the code assignment circuit of FIG. 2. In the figure, the multilevel time series signal S
4 is the address input terminal A ₂ of the read-only memory (ROM) 41 and 42 through the signal line 110.
A ₀ is supplied. Furthermore, the transition code generation timing pulse S7 is sent to the ROM 41 via the signal line 105.
and 42 address input terminal _A3 .

The timing pulse for V code generation is the signal line 104.
It is supplied to the output control terminals of the ROMs 41 and 42 through the ROMs 41 and 42. Here, all outputs of the ROMs 41 and 42 become 0 when the output control terminal is turned off, and only when the timing pulse is on, the content specified by the address line is transmitted to the output signal lines 120 and 12.
1 is output.

The contents of ROMs 41 and 42 can be easily created from FIG. That is, A ₀ is 2 ⁰ , A ₁ is 2 ¹ ,...
Assuming that the address line is represented by , code patterns corresponding to codes V ₀ to V ₅ are written in addresses 0 to 5 of the ROM 41, and corresponding code lengths expressed in binary numbers are written in the ROM 42. Also, at address 8 of ROM41 and 42,
V ^* ₀ code pattern and _a binary code representing code length 2, i.e. ₀ , ₀ ,
Write 1 and 0. In addition, the code pattern is
Write so that, for example, the terminal ₀₄ side of the output terminal of the ROM 41 always has the code of the first bit.

For example, if the number of codes is 2 bits, the remaining 2 bits may be 0 or 1. If this is represented by the symbol X, for example, the V ^* ₀ code pattern written at address 8 is output as "11xx" in the order of output terminals _O4 to _O1 .

FIG. 7 is a diagram showing a specific circuit of the first code assignment circuit. The most frequently occurring signal supplied through the signal line 101 is applied to the clear terminal of the counter 51. The clock pulses supplied through signal line 102 are applied to the clock input terminal of counter 51, and the number of clock pulses during the period in which the most frequently occurring signal is 0 is counted. When the most frequently occurring signal becomes 1, the counter is cleared.

The output of counter 51 is supplied to address input terminals A ₃ -A ₀ of ROMs 52 and 53.

As in the case of the second code assignment circuit, the transition code output timing pulse is sent from the signal line 107 to the ROM
52 and 53, and the R code output timing pulse is input to the signal line 106.
It is applied to the output control terminals of ROMs 52 and 53 through. Each of the ROMs 52 and 53 outputs an R code corresponding to the run length and its code length when the output control terminal is on, and all outputs are 0 when the output control terminal is off.
The contents of the ROMs 52 and 53 can be determined from FIG. 4 in the same manner as the second code assignment circuit, so a description thereof will be omitted.

FIG. 8 shows an example of the configuration of the multiplexing circuit 6. The V code and R code supplied through the signal lines 120 and 130 are time-division multiplexed by an OR gate 61, and a synchronization code S is multiplexed by a multiplexer 63 to output an unequal length code M to an output terminal 140.

The code generator 65 generates a synchronization code S, and in this example, the synchronization code S is a 5-bit code represented by "00001". That is, since the synchronization code S is a code to indicate the start of a block, it is necessary to set it to a code pattern that does not occur from the combination of the V code and R code shown in FIGS. 3 and 4.

In this embodiment, the code "00001" is a pattern that does not occur as long as the above-mentioned V code and R code are switched and used. The multiplexer 63 is connected to the signal line 113
The two input signals are switched in response to a synchronization timing pulse supplied via the synchronization timing pulse, and when the synchronization timing pulse is 0, a synchronization code S is output. Similar multiplexing is performed on a code length signal indicating the code length. That is, reference number 62 is an OR gate,
Reference numeral 64 is a multiplexer, signal line 141
A time-division multiplexed code length signal N is output.
In the pattern generator 66, the code length of the synchronization code S is 5.
Therefore, a code pattern of "101" is generated.

Next, the unequal length code array conversion circuit 7 will be explained. The unequal length code array conversion circuit 7 extracts valid unequal length codes from the unequal length codes including invalid codes,
This is a circuit that converts arrays.

FIG. 9 shows a specific circuit diagram of the unequal length code array conversion circuit, and FIG. 10 shows waveforms of each part thereof. The input signal to the conversion circuit 7 includes a 5-bit signal line 1.
unequal length code M (10th
S13) in the figure, a code length signal N indicating the length of the unequal length code supplied via the 3-bit signal line 141 (S14 in FIG. 10), and a sampling signal supplied via the signal line 102. There is a clock pulse.

The code lengths of the unequal length codes are 2, 3, 4, and 5, as is clear from FIGS. 3 and 4. Furthermore, if there is no significant unequal length code, the code length is given as 0. Therefore, signal line 1
The 5-bit code given by 40 includes a mixture of valid codes and invalid codes. For example, in an unequal length code given with a code length of 2, only the upper 2 bits of the code on the signal line 140 are valid, and the remaining 3 bits are invalid. Therefore, it is sufficient to remove the invalid code X from the unequal length code M and extract the valid unequal length code. Such array conversion of unequal length codes is difficult when the operating sampling frequency is as low as several 10 to several 100 KHz.
It is convenient to perform parallel/serial conversion of the unequal length code to convert it into a 1-bit signal sequence, but if the sampling frequency is as high as 10MHz, the operating speed of the serial operation will be around 100MHz. It becomes difficult. The unequal length code array conversion circuit shown in FIG. 9 is a parallel operation type circuit that overcomes these drawbacks and operates at high speed. That is, this circuit removes the invalid code from the unequal length code M including the invalid code, repacks the bits, and then outputs the data to the output line 150 as parallel 4-bit data. If this circuit is called a parallel operation unequal length code array conversion circuit, the parallel operation unequal length code array conversion circuit generally converts unequal length codes including invalid codes given by m-bit parallel signal lines. It can be extended to a circuit that removes invalid codes and converts it into 1-bit parallel data.

Next, the operation of the circuit shown in FIG. 9 will be explained. Note that this circuit is an example in which m and l in the above description are set to m=5 and l=4, respectively.

The 5-bit unequal length code provided on signal line 140 is applied to first shifter 71 and second shifter 72. A shifter is a type of multiplexer that switches input lines and output lines. Assuming that the input terminals I ₁ to I ₃ and the output terminals of the first shifter 71 are 0 ₁ to 0 ₃ , the connection of the input and output terminals is determined as follows depending on the number of shifts (the signal that determines the number of shifts is are given by signal lines 141a to 141c).

When the shift number is 0, I ₁ and 0 ₁ , I ₂ and 0 ₂ , and I ₃ and 0 ₃ are connected, and when the shift number is 1, I ₂ and 0 ₁ ,
I ₃ and 0 ₂ , I ₄ and 0 ₃ are connected, and generally when the shift number is n, I _1+o and 0 ₁ , I _2+o and 0 ₂ , and I _3+o and 0 ₃ are connected. The second shifter 72 has four output terminals 0 ₁ to 0 ₄
However, the input/output connection operation is similar to that of the shifter 71.

The output terminals 0 ₁ to 0 ₃ of the first shifter 71 are connected to the input terminals of the register 74, and the output of the register 74 is connected to the input terminals I ₁ to I ₃ of the first shifter 71 and the input terminal I of the second shifter. Connected to ₇ ~ _I5 .
A 4-bit parallel code from which invalid codes have been removed is output to the output terminals 0 ₄ to 0 ₁ of the second shifter 72 , but the remainder code generated when dividing the unequal length code into 4-bit units is output to the register 74 . is temporarily stored. The number of remainder signs is calculated by modulo arithmetic circuit 73 and register 75.

The modulo arithmetic circuit has signal lines 141a to 141
Binary data indicating the sign of the unequal length code given by c and binary data indicating the remainder given by signal lines 175a and 175b are added, and the remainder obtained by dividing this by l is sent to signal lines 173b and 173c. In addition to supplying the signal to the register 75 via the signal line 173, if the addition result is l or more,
a to the AND gate 76. In this example, since l=4, a normal binary adder can be used as the modulo arithmetic circuit, and the AND gate 76 creates a write pulse to write the output data to the memory when the carry signal is output. do.

The operation of the conversion circuit will be explained using FIG.
For simplicity, the output (remainder number) of the register 75 at time t ₀ is assumed to be 0. The remainder number is indicated by a signal S15 in FIG. 10, and the result of addition of the code length S14 of the unequal length code and the remainder number S15 is indicated by a signal S16.
At time _t0 , the unequal length code is 5 bits, indicated by "00001", as shown in signal S13. Since this code has more than 4 bits, the terminal 0 of the shifter 72
The 4 bits before ₄ to 0 ₁ , ie, "0000" are output. The modulo arithmetic circuit 73 adds the remainder number 0 and the code length 5. At this time, since the addition result is 5, a carry signal 1 is given to the signal line 173a, and the remainder 1 (binary 01) is sent to the signal line 173b and 1.
73c. Therefore, at time t ₀ the signal S17
A write pulse is generated as shown in , and the signal S1
As shown in 8, the output data of the shifter 72 is “0000”.
is written to memory. The remaining 1-bit code at time t ₀ is taken into the register 74 which is output from the input terminal I ₃ of the shifter 71 to the output terminal 0 ₃ .
At time _t1 , the unequal length code is 2 bits of "10" and the previous remainder code is 1 bit, so the 4-bit data to be written into the memory cannot yet be prepared.
The previous remainder bit "1" is fed back from register 74 to input terminal _I3 of shifter 71. Further, each bit "1" and "0" of the 2-bit asymmetric code is applied to input terminals I ₄ and I ₅ of the shifter 71. At this time, since the number of shifts is 2,
Each bit “1”, “1” and “0” of these terminals I ₃ to I ₅ are output terminals 0 _{1 and 0} of the shifter 71, respectively.
It is output to 0 ₂ and 0 ₃ and taken into the register 74. The data “110” taken into the register 74 is input to the input terminals I ₇ , I ₆ , and the shifter 72 at time t ₂ .
Output to _I5 . Furthermore, at time _t2 , 4-bit data "0011" is sent to the shifter 71 through the signal line 140.
is input. At this time, the shift number of the shifter 72 has a remainder of 3 (the result of addition of the remainder 1 at time t ₁ and the code length 2 at time t ₂ ), so the output terminals of the input terminals I ₇ to I ₄ of the shifter 72 Connected to ₀₄ to ₀₁ . Therefore, the data written to the memory at time _t2 is the code "110" of the remainder at time _t1 and the code "0" of the previous 1 bit of the 4-bit data input at time _t2 . 1100". The remaining 3-bit code "011" out of the 4-bit data is taken into the register 74 via the shifter 71. In this way, the unequal length codes are rearranged and written into the memory every 4 bits.

Generally, if the maximum number of input parallel bits is m bits and the maximum number of parallel bits to be output is l bits, then the first shifter has a shifter whose number of input signals is (m+l-1).
bit, number of shifts is m, number of output signals is (l-1)
Bits are required. In addition, the second shifter has an input signal number of (2l-1) bits, a shift number of (l-1),
The output signal requires l bits.

These shifters have (l-
1) If we add a bit register, an accumulator for counting the remaining bits, and a modulo arithmetic circuit, we get
When unequal length codes of 0 to m bits including invalid codes are inputted in any combination, it is possible to convert the array into l-bit parallel data excluding invalid codes. In this unequal length code conversion circuit, if the number of parallel bits l is set so that surplus bits do not accumulate and overflow (if codes with the maximum code length m occur consecutively, set l = m), It is possible to generate unequal-length codes rearranged in parallel at the same sampling speed as the input data.
For example, if m=12, l=12, and the sampling rate is 10 MHz, unequal length encoding of up to 120 Mb/s can be realized, which is extremely effective for high-speed processing. Note that a shifter is basically a gate circuit that connects an input line and an output line under specified conditions; the circuit elements are not specifically limited.

Strictly speaking, since a synchronization signal (5 bits) is inserted, care must be taken to prevent register overflow at the beginning and end of one block. A general television signal has a blanking period during which no signal is generated, so there is no problem because there is time to insert a synchronization signal during this period. However, if there is not enough blanking period, it is necessary to take measures such as forcibly shortening the code lengths at the beginning and end of the block in order to avoid overflow due to synchronization code insertion.

In the example described above, the number of target multi-level time series signals is one, but this can be extended to a plurality of time series signals. For example, two time-series signals, a television signal and an audio signal, are often multiplexed and transmitted, or necessary mode information and information indicating the block number are multiplexed and transmitted for each block. One feature of the present invention is that this information is time-division multiplexed onto parallel m-bit data lines by a multiplexing circuit before performing array conversion of unequal length codes. However, if multiple time-series signals occur simultaneously in time,
Some effort is required to time-division multiplex these time-series signals.

FIG. 8A shows a specific circuit of a multiplexing circuit that multiplexes a plurality of time-series data generated simultaneously.

FIG. 8A is a modification of the multiplexing circuit shown in FIG.
These code length signals are input through 131 and 131, respectively. It is assumed that the data to be multiplexed is 4-bit audio data generated at time _t1 in FIG. Therefore, since the _V1 code generation time and the audio data generation time overlap, simple multiplexing is not possible.

In FIG. 2, since there is no valid data at times t ₅ , t ₆ and t ₁₂ , audio data can be multiplexed by using these time slots. If the audio data is to be inserted immediately after the synchronization code S in order to easily identify the insertion position of the audio data, it is sufficient to temporarily store the unequal length code in a memory and read it out after closing the time when the code length becomes 0. That is, in FIG. 8A, the unequal length codes and their code length signals multiplexed by OR gates 61 and 62 are once written into memory 600. Gate circuit 603 receives the code length signal and sampling clock pulse 102 and generates a write pulse for memory 600 on output line 133 except when the code length is O. In addition, the gate circuit 60
3 supplies the write pulse of the memory 600 to the write address counter 601 to control the write address of the memory 600. Gating circuit 604 generates read clock pulse 136. This gate circuit 604 is connected to the sampling clock pulse 10.
2 and the synchronous timing signal 113 through the timing shaping circuit 606 and the address match signal 135 output from the address comparator 605.

The read clock pulse is supplied to memory 600 and read address counter 602.
is supplied to control the read address.

Multiplexing control is performed as follows. first,
At times t ₀ and t ₁ , the unequal length code is not read from the memory 600 because the synchronous code and audio data are output. During this period, the multiplexer 631 controls the synchronization code generator 65 and the audio data generator 611.
The code generated from the signal is output to the output line 140.

Furthermore, the synchronization and audio data code length signals output from the synchronization code length generator 66 and the audio data length generator 612 are outputted to the output line 141 by the multiplexer 641 in synchronization with the multiplexer 631 described above.

An unequal length code V ₁ is written into the memory 600 during the read suspension period.

The address comparison compares the read address and the write address, and informs the gate circuit 604 whether or not there is data to be read in the memory 600. At time _t2 , the read stop gate is turned off, and since there is data to be read in the memory 600, the unequal length code _V1 is read. By repeating this operation in order, the time axis can be closed using the time when the code length is 0. Further, if such a multiplexing circuit is used, time-division multiplexing of code data becomes possible even when an unequal-length code of an image is generated at time _t0 (no blanking) in FIG. 2.

It goes without saying that a memory circuit is not required if there is sufficient blanking time and audio data can be multiplexed during the blanking period.

Next, a decoding apparatus of the present invention that decodes an original multilevel time series signal from a compression-encoded encoded signal will be described.

FIG. 11 is a block diagram showing an embodiment of the present invention for decoding an original television signal from a code compressed and encoded by the encoding apparatus shown in FIG. The compression code is sent via a transmission line or directly to memory 1.
8. When passing through a transmission path, the memory 18 serves as a buffer memory, which temporarily stores incoming codes and sequentially reads them out as they are decoded. Since the data input from the transmission path is usually 1 bit, it is converted into serial and parallel data and written into the memory. A parallel 4-bit compressed code is read out from the memory 18 by a read clock pulse 209.

Note that this number of parallel bits does not have to match the number of parallel bits written into memory during encoding. The parallel 4-bit compressed code is divided into unequal-length codes by the unequal-length code array inverse converter (the part surrounded by the broken line in the figure), and is sent to the first code converter 14 through the signal line 210 to convert the original code. Converted to a multilevel time series signal. Note that, in order to make correspondence with FIG. 1, the DPCM decoder 12 is used in FIG.
That is, the DPCM decoder 12 provides a sampling clock pulse to the decoding device via the signal line 202, and receives the original multilevel time series signal (difference signal) synchronized with this from the first code converter 14. , the original television signal is taken out to the output terminal 11. Here, the DPCM decoder 12 does not impose any limitations on the present invention. Note that the sampling clock pulse can also be generated within the decoding device.

In FIG. 11, the unequal length codes outputted to the signal line 210 are controlled so that the most significant bit of the signal line 210 becomes the first bit of each unequal length code. This array inversion is accomplished by passing the 4-bit compressed data read from memory through register 20 and shifter 17. The second code converter 15 monitors the 4-bit code output to the shifter 17 and determines the code length of the unequal length code. This code length information is stored in the shifter 17
The signal is applied to a shift number determining circuit composed of an adder 21, a comparison operation circuit 16, and a register 22 for determining the next shift number. The synchronization bit position detection circuit 19 detects the synchronization code S and decodes its leading bit position. In addition, the control circuit 13
monitors whether the compression code is a V code, an R code or a transition code, and sends the first and second code converter 1
4 and 15.

Next, the operation of the decoding device of the present invention will be explained in detail with reference to FIG. Here, it is assumed that the compression code is encoded according to Rule 1 as shown in S18 of FIG. S21 in FIG. 12 represents the time, and S29 in FIG. 12 represents the read clock pulse of the memory 18. Further, in S22 of FIG. 12, the codes applied to the input terminals I ₁ to I ₈ of the shifter 17 are shown as 1 and 0 in order from the top. The 4-bit parallel code read out from the memory 18 is applied to the input terminals I ₅ to I ₈ of the shifter 17, so that S22 in FIG.
The code of the lower 4 bits indicates the code read from the memory 18. Further, the upper four bits of S22 are the output of the register 20. The upper 4 bits are a code obtained by sampling the lower 4 bits by the read clock pulse indicated by the signal S29.
In other words, it indicates data read out from memory 18 one clock ago. It is assumed that the code "0000" is read out from the memory 18 at time t _-1 and the code "1100" is read out at time t ₀ . The 8-bit code of the signal S22 is supplied to the synchronization bit position detection circuit 19, which detects the synchronization code S, that is, the bit pattern "00001" from this code, and generates the synchronization bit position signal S as shown in FIG. Output _p . That is, when the synchronization code S is included, when the synchronization head bit is located at the most significant bit of the 8-bit code ( _I1 terminal of the input terminal of the shifter 17), the synchronization bit position signal S _p is set to 0. , when it is located at the second bit, S _p = 1, when it is located at the third bit
S _p =2, and in the fourth case, S _p =3. Since the synchronization code S is represented by 5 bits, the positions of the synchronization bits when the synchronization code exists are these four types. When the synchronization code S is not included in the 8 bits, S _p =15. Therefore, by looking at _Sp , it is possible to know the position of the synchronization bit and whether or not it exists. At time t ₀ , a synchronization code S exists,
The first bit position is the first bit of 8 bits, so S _p
=0.

In FIG. 11, the S _p signal is input to the comparison calculation circuit 16 via a signal line 220. The comparison calculation circuit 16 receives a signal (r+n) (described later) indicating the next code bit position supplied from the adder 21 and S _p
When S _p ≠ 15, the output (S _p +
Generates the remainder when dividing 5) by 4 and a carry signal.
Further, when S _p =15, the remainder of (r+n) divided by 4 is output, and when (r+n)≧4, a carry signal is generated. Therefore, since S _p =0 at time t ₀ , the remainder is 1 and a carry signal is generated. The carry signal is provided via signal line 221 to NAND gate 23 which gates the sampling clock pulse from signal line 202 and produces a read clock pulse at its output. Further, the sign indicating the remainder is delayed by one sampling clock in the register 22, and is supplied to the shifter 17 as a shift number designation signal at the next time _t1 . Therefore, if synchronization is detected by the synchronization bit position detection circuit 19, S _p ≠15
Therefore, the comparison arithmetic circuit 16 specifies the next shift position regardless of the number of past surplus bits, and the initial state following synchronization is set. 12th
FIG. S24 shows the shift number r of the shifter 17. When the shift number is 0, the shifter 17 has input terminals I ₁ and 0 ₁ ,
When I ₂ and 0 ₂ , I ₃ and 0 ₃ , I ₄ and 0 ₄ are connected, and the shift number is r, the input terminals are connected as I _1+r and 0 ₁ , I _2+r and 0 ₂ , etc. be done. At time _t1 , new data is read from the memory 18, so the code applied to the input terminals _I1 to _I8 of the shifter 17 becomes "11000110" as shown in S22 of FIG. 12.

Among these, the code “1” of the first bit is at time t ₀
This is the code of the fifth bit of the synchronization code "00001" detected in . Therefore, the code of the first bit is a code that has already been used, in other words, it is a code that has been decoded, and the new code is the code starting from the second bit. The shift number r supplied to shifter 17 always represents the starting position of a new code bit. That is, if the first bit is the start position, the shift number is 0, and if the second bit is the start position, the shift number is 1. Incidentally, if the number of undecoded bits stored in the register 20 is the remainder bit, the relationship between the number of shifts r and the number p of the remainder bits is p=4-r. At time t ₁ , the shift number r is 1, so
Output terminals 0 ₁ to 0 ₄ of shifter 17 have the code “1000”
is output. The second code converter 15 has terminal 0 ₁
The code length n of this unequal length code is decoded from the unequal length code of ~ ₀₄ , converted to a binary number, and added to the adder 21.
Output to. The code length n of the unequal length code can be easily determined from the type of input code (V code or R code) and the code tables shown in FIGS. 3 and 4.

The V code and R code are connected from the control circuit 13 to the signal line 2.
RV signal supplied via 05 (Fig. 12 S2
7). A synchronization detection signal is sent to the control circuit 13 via the signal line 203 to the comparison judgment circuit 1.
Supplied from 6. Upon receiving this signal, the control circuit 13 outputs (initializes) a signal indicating that the code at time _t1 is the V code according to Rule 1 (5). In FIG. 3, since only the _V1 code has a code pattern of "10" among the V codes, the code length of the input code is determined to be 2. Therefore, the second code converter 15 has a code length n(1)(6)
=2 is output. The adder 21 adds the code length n=2 and the shift number r=1, and the addition result is r+n=3.
is applied to the comparison/judgment circuit 16. At time _t1 , the synchronization code S is not detected, so S _p =15 is output. Therefore, since the relationship between S _p and (r+n) is 15>3, the remainder 3 when 3 is divided by 4 passes through the register 22 and becomes the shift number at the next time t ₂ . Further, since no carry signal is output at time _t1 , no read clock pulse is generated. That is, the time
The code used at _t1 is a 2-bit code applied to the _I2 and _I3 terminals of the shifter 17, and the remaining 5-bit code has not been decoded yet. Since the maximum code length of an unequal length code is 4 bits, there is no need to read new data from the memory 18 if the undecoded code is 4 bits or more.

At time _t2 , a signal ``0011'', which is a 3-bit shifted signal of the input signal ``11000110'', is output to the output terminals ₀₁ to ₀₄ of the shifter 17.
It can be seen that it is the V ₄ code of .

In S23 of FIG. 12, the code length n of the unequal length code is
The shift number r is set in S24, and (n+r) is set in S25.
, and the decoded code is shown in symbol in S26. Further, the code surrounded by a thick solid line in S22 represents the unequal length code decoded at that time. What should be noted in this circuit operation is that the first bit of a new unequal length code is always output to the output terminal ₀₁ of the shifter 17. Therefore, the first code converter 14 converts the 4-bit codes of the output terminals 0 ₁ to 0 ₄ of the shifter 17 into the original multilevel signal based on the RV signal and the table shown in FIG.
Output to 0. Note that the output level for the R code is, of course, 0, which is the most frequently occurring value.

As shown in FIG. 12, since the V ^* ₀ code is decoded at time _t4 , the R code is decoded at the next time _t5 . In this case, time t ₅ is an R ^* ₃ code.

If we find the R ^* ₃ code, we can see that there are three consecutive level 0 signals, so at times t ₆ and t ₇
Then, there is no need to decode the next code length, and the decoding operation is temporarily suspended. This pause operation is controlled by the control circuit 13. In other words, the control circuit is shown in FIG. 12, S27.
In addition to generating the RV signal shown in S28 of the same figure,
A gate signal as shown in FIG. 1 is supplied to the second code converter 15 via a signal line 206. This gate signal indicates a decoding pause period, and when the gate signal becomes LOW level, the second code converter 15
Force the code length n to 0. In this way, the unequal length codes are sequentially decoded, and at time _t14 , the synchronous code is detected again, and the circuit operation returns to its initial state.

The first code converter and the second code converter in FIG. 11 can be easily implemented using a read-only memory (ROM).

FIG. 14 is a diagram showing a specific circuit of the control circuit 13. The output of the shifter 17 is input to the address input terminal of the ROM 25 via a signal line 210.
When the ROM25 finds the V ^* ₀ code, it sends it to the signal line 212.
Outputs V ^* ₀ detection signal. Furthermore, in the case of the R code, a binary code representing the run length is output to the signal line 211. The V ^* ₀ detection signal is applied to the load terminal of the presettable counter 26 through a timing circuit 27 including a flip-flop and a one clock delay circuit 26A to load the run length into the counter. Since the counter 26 performs a countdown operation by 1 per clock, a carry signal is sent to the timing circuit 27 via the signal line 213 when the loaded run length has elapsed. The timing circuit 27 creates an RV signal from the V ^* ₀ detection signal and outputs it to the signal line 205.
A flip-flop with a signal inside is used to invert the signal using a carry signal. In addition, in the figure,
Signal line 202 represents the sampling clock pulse and signal line 203 represents the synchronization timing pulse. Synchronous timing pulses are applied to timing circuit 27 and are used to define the initial state of the RV signal.

The unequal length code array inverse conversion circuit 30 has the function of converting the compressed unequal length code array as described above and outputting the unequal length codes separated one by one to the output signal line 210. There is. That is, the output line 21
The first bit of the unequal length code is always output as the most significant bit of 0. Although the control circuit 13 has the function of instructing the type of code according to the code conversion rule and the function of controlling the decoding time, no special restrictions are placed on the unequal length code array inversion circuit 30.
For example, if the unequal length code is composed of only V codes, the control circuit 13 is not necessary. The unequal length code array inversion circuit 30 shown here is a circuit specially devised to transform the array of compressed unequal length codes input in parallel and separate them into individual unequal length codes. It has the characteristic of being capable of high-speed operation. Assuming that the maximum code length of the unequal length code is m and the number of parallel bits is l, its configuration can be generalized as follows. The register 20 temporarily stores at least (l-1) bits of data, and the shifter 17 has at least (m+l-1) input signals, m output signals, and at least (l-1) shift numbers. It becomes necessary. In addition, in order to control the number of shifts of the shifter, an arithmetic circuit that decodes the code length of the unequal length code and outputs the remainder and carry of dividing the sum with the current number of shifts by l, and outputs the remainder through a register. A circuit is required to input the shift number to the shifter, and a circuit to issue a memory read request in accordance with the carry signal. Furthermore, in order to set the initial state for decoding an unequal length code, a circuit is required that compares a signal indicating the presence or absence of a synchronization code and the position of the synchronization bit with the bit position during decoding.

The number of parallel bits is 12, and the clock frequency is 10MHz.
If so, it is possible to decode unequal length codes of up to 120 Mb/s. In addition, as mentioned above, by adding a control circuit that controls the type of unequal length code and the decoding time to this unequal length code array inversion circuit, it is possible to create a It becomes possible to decode unequal length codes.

Although the solid decoding device described above uses one type of multilevel time series signal, it can be expanded to the case where a plurality of multilevel time series signals are multiplexed within one block and compressed and encoded. An example of the configuration of the decoding device in this case is shown in FIG. This example corresponds to the case where compression encoding is performed on two time-series signals, a television signal and an audio signal, as shown in FIG. 8A. The configuration in FIG. 15 is basically the same as the configuration in FIG. 11, but in order to adjust the playback times of the television signal and audio signal,
It has an added function to the control circuit shown in the figure.
In FIG. 15, from the memory 18 to the signal line 209
A parallel l-bit compressed code is read out by a read clock pulse given from A code whose arrangement is converted so that the first bit of the long code is located is output. Synchronous bit position detection circuit 1
9 is connected to an unequal length code array inversion circuit 30. The operations of each of these components 18, 19, and 30 are the same as those in FIG. signal line 21
0 is connected to the first control circuit 703, the audio decoder 706 and the memory 700. The first control circuit decodes the code output to the signal line 210, generates the RV signal 205, and generates the memory 70.
0 data write pulse 232 and audio data timing pulse 231 are generated. Since the audio data is inserted after the synchronization code, it can be easily generated from the synchronization timing pulse 203.
The data write pulse 232 to the memory is also supplied to a write address counter 701 to control the write address. Since the audio data is removed and only image-related data is written to the memory 700, the data written to the memory 700 is sequentially read out under the control of the second control circuit 704.
The first code converter 14 converts the unequal length code into the original multilevel time series data, and supplies the data to the DPCM decoder 12 to reproduce the original television signal. Second
When the run-length code is input, the control circuit temporarily suspends the memory read pulse 233 for the duration of the most frequently occurring value, and also outputs the RV signal 20.
7 is given to the first code converter, and the reproduced time series data for this period is set to the most frequently occurring value. The memory read clock pulse 233 is also provided to a read address counter 702 to control the read address. The read address and write address of the memory are compared by a comparator 705, and when the memory is full, a decoding pause signal is sent to the unequal length code array inversion circuit 30 and the first control circuit 703 via the signal line 206.

In the configuration shown in FIG. 15, since the data representing the television signal is stored separately in the memory 700, the original multilevel time series data related to the television signal is stored independently of the presence of other multiplexed information. can be decrypted. All the multiplexed codes are separated and output on the signal line 210, but data is not written to the memory 700 while codes other than the image signal are being decoded. The data written previously will be digested. Therefore, its capacity only needs to be approximately the same as the number of multiplexed data other than images.

In this way, it is possible to easily decode codes obtained by multiplexing and compression-encoding a plurality of multi-level time series signals such as audio signals, mode signals, and other signals in addition to image signals.

Listing the features of the decoding device of the present invention as described above, (1) Array inverse transformation of unequal-length codes converts compressed data read in parallel l bits into parallel m'-bit separated unequal-length codes. , high-speed operation is possible and the circuit configuration is simple.

(2) The synchronization code detection for setting the initial state of the above array inversion operation is performed on the read parallel data, and the starting bit position of the synchronization code is detected, so there are no restrictions on the synchronization code to be used. , highly flexible.

(3) Since the unequal length code array inversion circuit can be used commonly for multiple multiplexed multilevel time series signals,
The entire circuit configuration can be simplified.

Due to the above features, even if the allocation of unequal length codes necessary to improve compression efficiency becomes somewhat complicated,
A decoding circuit that easily decodes the compressed code can be realized.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of an encoding device used in the present invention, FIG. 2 is a schematic diagram showing control timing, and FIGS. 3 and 4 are respectively a first code and a second code of the present invention. A schematic diagram showing an example of a code,
FIG. 5 is a block diagram showing an example of a timing control circuit, FIGS. 7 and 6 are block diagrams showing an example of the configuration of the first and second code assignment circuits, respectively, and FIG. 8 is a block diagram of a multiplexing circuit. FIG. 9 is a block diagram showing an example of the configuration of an unequal length code array conversion circuit, FIG. 10 is a schematic diagram showing the timing of unequal length code conversion, and FIG. 8A is a multiplexing circuit. FIG. 2 is a block diagram showing another example. FIG. 11 is a block diagram showing an example of the configuration of the decoding device of the present invention, FIG. 12 is a schematic diagram showing the control timing of code inversion, FIG. 13 is a schematic diagram explaining the synchronization bit position, and FIG. 14 is a control diagram. A block diagram showing one example of the circuit 13 and FIG. 15 are block diagrams showing another example of the decoding device. In the figures, reference numbers indicate the following: 2... DPCM encoder, 3... Timing control circuit, 4... Second code assignment circuit, 5... First code assignment circuit, 6... Multiplexing circuit, 7... Unequal length code array conversion circuit, 8...Memory, 31, 35...
...OR gate, 32...Register, 33...Timing pulse generator, 34...Register, 41,
42,52,53...ROM, 51...Counter, 61,62...OR gate, 63,64...
Multiplexer, 65, 66... Code generator, 7
1, 72...Shifter, 74, 75...Register,
73...adder, 76...AND gate, 26...
...Counter, 27...Timing circuit, 30...
Unequal length code array inverse conversion circuit, 601, 602...
Counter, 603, 604... Gate circuit, 60
6...timing shaping circuit, 605...comparator,
600...Memory, 631, 641...Multiplexer, 611...Speech code generator, 612...
...Code generator, 18...Memory, 20, 22...
Register, 19...Synchronization bit position detector, 17
...Shifter, 14...First code converter, 15...
2nd code converter, 13...control circuit, 21...adder, 16...comparison calculation circuit, 23...NAND
Gate, 12...DPCM decoder, 30...Unequal length code array inverse conversion circuit, 26...Counter, 27
...Timing circuit, 25...ROM, 701,
702... Counter, 703... First control circuit,
704...Second control circuit, 705...Comparator, 7
00...Memory, 706...Audio decoder.

Claims (1)

[Claims] 1. A multi-level time series signal expressed in binary with uneven occurrence frequency is divided into blocks in time series, and a synchronization code with a code length of m bits or less is generated for each block division. , a first unequal length code having a maximum code length of m bits, which is generated to represent the continuation length of the most frequent signal value of the multilevel time series signal; a second unequal length code having a maximum code length of m bits, which is generated to represent each signal value except for the maximum frequency signal; and a shifting code which is generated to represent the maximum frequency signal value. The maximum code length consisting of the non-displaced code is m
and a third unequal length code of bits onto a parallel m-bit data line, and outputs each code arranged on the parallel m-bit data line onto a parallel l-bit data line. A decoding device for decoding the parallel l-bit code into the multilevel time series code includes a memory for temporarily storing the parallel l-bit code, and a register for decoding the l-bit code from the memory in parallel ( m+l-1) bits are read on the data line, it is detected whether or not the synchronization code indicating the division of each block is present on the parallel (m+l-1) bit data line, and the most significant bit of this synchronization code is a parallel synchronous bit position detection circuit that generates a synchronous code position signal indicating where the bit is located among the (m+l-1) bits; and a parallel synchronous bit position detection circuit that shifts the parallel (m+l-1) bit data according to the number of shifts. a shifter that outputs an m-bit unequal-length code; and determining which of the first, second, and third unequal-length codes the m-bit unequal-length code output from the shifter is; code type signal generating means for generating a code type signal; detecting the code length of the m-bit unequal length code from the shifter based on the m-bit unequal length code from the shifter and the code type signal; code length detection means for generating a signal; a shift number calculation circuit for calculating the shift number of the shifter based on the code length signal and the synchronization code position signal; 1. A decoding device comprising an m-bit unequal length code decoding circuit for converting an input signal into a multi-level time series signal.