JPH02901B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a code conversion device that compresses and codes a sampled multi-level time series signal whose frequency of occurrence is biased.

Multi-value time-series signals obtained by sampling image signals and audio signals generally have a bias in the frequency of occurrence of each multi-value signal. PCM (pulse code modulation) obtained by A/D conversion of analog image signals and warm voice signals
Although the deviation in occurrence frequency of signals is not so large, for example, a multilevel signal obtained by converting a PCM signal to a DPCM (differential pulse code modulation) signal generally exhibits a zero-concentrated frequency distribution. That is, signals with a difference value close to 0 occur frequently, and signals with a large difference value occur less frequently. Signals with uneven occurrence frequency can be compressed and encoded by unequal length coding in which short codes are given to signals with high occurrence frequency and long codes are given to signals with low occurrence frequency. Such unequal length encoding is a method of giving a predetermined unequal length code to the sampled multi-level difference time series signal at each sampling time according to the difference signal at that time. . In this case, a code of at least 1 bit is required even for the most frequently occurring difference value. However, in interframe DPCM encoding for image signals such as television, the probability of occurrence of a signal with a difference value of 0 is low.
It is usually more than 90%, and it is inefficient to give a 1-bit sign to a signal with a difference of 0.
Therefore, for signals with large deviations in frequency of occurrence, the time-series signal is grouped into blocks of, for example, 8 sample values, and all 8 signal values included in each block are determined to have the highest frequency of occurrence. Attempts have been made to improve compression efficiency by giving a special block code to indicate a signal value (hereinafter referred to as the most frequently occurring signal value), but the complexity of the device configuration However, the disadvantage is that the compression efficiency does not improve.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks and to provide a code conversion device that efficiently encodes a multivalued time-series signal with uneven frequency of occurrence using a simple circuit.

According to the present invention, the most frequently occurring signal value in a multivalued time series signal is encoded with a code representing its duration, so it is possible to reduce the number of code bits per sample value to 1 bit or less. Furthermore, since each of the two types of codes includes a code indicating a transition, even if the most frequently occurring signal value and other signal values are mixed in the time series, they can be easily compressed and encoded while distinguishing them. Therefore, the compression efficiency is high and the circuit configuration is simple.

Next, the present invention will be explained in detail with reference to the drawings.

FIGS. 1 and 2 are a block diagram and timing chart showing an embodiment of the code conversion apparatus of the present invention.

Although the device of the present invention can be applied to sampled time-series signals such as image signals and audio signals, a television signal will be explained here as an example. First, the television signal supplied to the input terminal 1 is converted by the DPCM encoder 2 into a multi-level time series signal (S4 in FIG. 2) with a biased frequency of occurrence suitable for the conversion device of the present invention. Output to 100. At this time, the synchronization timing signal (S3 in Figure 2) and the sampling clock pulse (S1 in Figure 2) are connected to the signal line.
Output to 103 and 102 simultaneously. Although this synchronization timing signal S3 is not an indispensable signal in the present invention, it is used as information representing the division of blocks in order to divide the time series data into blocks of a certain length and compress and encode them.
Now, the conversion device of the present invention shown in FIG. a second code generator 4 that generates the first and second codes; a multiplexer 6 that integrates the first and second codes; It consists of a long code array conversion circuit 7. Note that reference numeral 8 is a memory that stores data converted by this code conversion device. When the device of the present invention is incorporated into a communication device through a line, the memory 8 is used as a buffer memory for speed smoothing, and the device of the present invention is used as an input means to a data file possessed by a computer device or the like. When used as part of a computer, memory 8 is used as computer memory or interface memory. Here, the first code R is a code representing the duration (run length) of the most frequently occurring value in time series, and the second code V is the value (level) of the multilevel signal.
This is a code representing. Further, each of the R code and the V code includes at least one transition code. These are respectively called the first transition code (hereinafter referred to as R ^* code) and the second transition code (hereinafter referred to as V ^* code).
(symbol). The R ^* code is a code that indicates a transition from the R code to the V code, and the V code is sent out after the R ^* code in time series. Further, the V ^* code is a code indicating a transition from the V code to the R code, and the R code is sent out after the V ^* code. R for codes other than transition codes
The R code follows the code, and the V code follows the V code.

FIG. 3 shows an example of a V code for signal levels 0 to 5 of a multilevel signal. Signal level 0, i.e.
For the most frequently occurring value, a non-transition code V ₀ is given in addition to the transition code V ₀ ^* . The V code is assumed to be an unequal length code with a code length of 2 to 4 as shown in the figure. An unequal length code is a code that has the characteristic that if the beginning of the code is known, the length of the code or the end of the code can be determined from the time series of the code. In FIG. 3, for example, there are only two codes starting with 1: the code V ₀ ^* , "11", and the code V ₁ , "10", both of which have a code length of 2. Further, the _only code that continues with "011" is code V2 with a code length of 3. The code length for which the code is "00..." or "010..." is 4.

FIG. 4 shows an example of the R code for the run length of the most frequently occurring signal value. Here, the R code is also assigned an unequal length code with a code length of 2 to 4. The codes representing run lengths from 0 to 7 are respectively
R ₀ ^* to R ₇ ^* these are transition codes. The code R8 whose run length represents ₈ is not a transition code.
In the present invention, it is also possible to define all run-length codes as transition codes, but generally, as the run length increases, the number of types of codes that represent it increases, and the code generation circuit becomes complex. Therefore, in the present invention, as shown in FIG. 4, by using both non-transition codes and transition codes, large run lengths are encoded. For example, if a non-transition code R ₈ is used, run length 8 can be expressed as R ₈ + R ₀ ^* run length 10 can be expressed as R ₈ + R ₂ ^* , and in the example in Figure 4, nine types of codes are used to represent 0 to 15. can represent the run length of Note that a larger run length can be expressed by increasing the number of non-transition codes as necessary.

The method of determining unequal length codes as shown in FIGS. 3 and 4 is actually to obtain statistics of the frequency of occurrence of each signal level and each run length for the target image signal, For example, Huffman codes are assigned to these probability distributions. This allows the overall amount of compressed codes to be minimized.

Next, the configuration and operation of each part 3 to 7 of the present invention will be explained in order. For ease of explanation, the input multi-level time series signal 100 is expressed in six levels from 0 to 5. The most frequently occurring signal value is assumed to be 0 level. That is, it is assumed that the signal line 100 is composed of 3-bit parallel data lines, and the signal levels from 0 to 5 are respectively expressed as binary numbers 000, 001, . . . .

FIG. 5 is a diagram showing a specific circuit of the timing control circuit 3. In the figure, an OR circuit 31 determines whether the level of a multi-level time series signal having levels from 0 to 5 is 0 or not, which is input through a signal line 100, and a delay adjustment register 34 performs delay adjustment to signal the signal. It is output as the most frequently occurring signal to line 101 (S5 in FIG. 2). (In Figure 2, for simplicity, it is assumed that there is no input signal to be encoded at times t ₀ and t ₁₄ , where there is a synchronization timing. (There are cases where such encoding is often not performed during the blanking period of television signals. ) At this time, the most frequently occurring signal is set to 1 (High level)) The output of the OR gate 31 is set to 1 by the register 32 for one clock delay.
The clock is delayed and applied to OR gate 35.
The OR gate 35 performs an OR operation on this signal and the undelayed original signal (S6 in FIG. 2), and supplies this signal through a signal line 203 to a timing pulse generator 33 consisting of a register and a gate. The timing pulse generator 33 uses the signal on the signal line 203 and the clock pulse to generate a timing pulse for V code generation (S6 in FIG. 2), a timing pulse for transition code V ^* generation (S7 in FIG. 2), and a timing pulse for R code generation. The pulse (S8 in Figure 2) and the transition code R ^* generation timing pulse (S9 in Figure 2) are connected to the signal line 104~
Occurs in 107. Further, the multilevel time series signal S4 and the synchronized timing signal S3 are also delayed and adjusted by the delay adjustment register 34, and outputted to the signal lines 110 and 113, respectively. The delay adjustment register 34 is
It is used to compensate for delays caused by waveform processing in the timing pulse generation circuit 33. Note that the timing pulses S6 and S in FIG.
7, S8, and S9 indicate the states after delay adjustment, and the relative time relationships of the signals S1 to S9 are described so as to be correct when viewed from the output of the timing control circuit 3. That is, S
The waveforms of 3, S4, and S5 are the signal lines 113 and 113, respectively.
110 and 101 waveforms. A multilevel time series signal 100 generated in the timing control circuit 3,
V code generation timing pulse S6 and transition code
The V ^* generation timing pulse S7 is supplied to the second code generator 4 of FIG. second code generator 4
outputs its output signal line 1 in response to a timing pulse.
A V code is generated on the signal line 120, and a binary code indicating the code length of the V code is generated on the signal line 121. Further, the most frequently occurring signal S5, the R code generation timing pulse S8, and the transition code R ^* generation timing pulse S9 from the timing control circuit 3 are supplied to the first code generator 5. In the first code generator, the most frequent signal value S
It counts the number of consecutive 5's and 0's and generates an R code on its output signal line 130 and a binary code indicating the code length of the R code on its signal line 131 in response to a timing pulse. The V code and the R code are controlled by timing pulses S6 and S8 so that they do not occur at the same time.

The V code and R code generated on the signal line 120 and the signal line 130 are time-division multiplexed by the multiplexer 6. Similarly, the binary code indicating the code length generated on the signal line 121 and the signal line 131 is also output to the multiplexer 6.
time-division multiplexed. The multiplexer 6 further outputs to the signal line 140 an unequal length code M (S10 in FIG. 2) obtained by time-division multiplexing the synchronization code S into the R and V codes in accordance with the synchronization timing pulse supplied through the signal line 113. Similarly, for the binary code indicating the code length, a code length signal N (S11 in FIG. 2) obtained by time-division multiplexing of each code length of the R and V codes and the synchronization code S is output to the signal line 141. In FIG. 2 S10, the symbol X indicates an arbitrary code, and the second
The fact that the number of effective codes in FIG. S11 is 0 indicates that there is no meaningful unequal length code at that time.

Here, the combination of the V code and the R code in FIG. 2 S10 will be explained. This example works according to the following rules:

(1) Give a code Vk (k=1 to 5) that does not transition if the multilevel time series signal has a value other than the most frequently occurring value.

(2) For the first most frequent value where the multi-level time series signal changes from a value other than the most frequent value to the most frequent value, (a) when the second signal is the most frequent value, the transition code V ₀ ^* is given. give,
(b) When the second signal is not the most frequently occurring value, give a code V ₀ that does not transition.

(3) For two or more consecutive most frequently appearing values, the run length excluding the first most frequently appearing value is expressed by an R code.

(4) R code is R ₁ ^* ~ when the run length is 1 to 7.
It is represented only by the transition code of R ₇ ^* , and when it is 8 to 15, it is represented by a combination of the non-transition code R ₈ and the transition code of R ₀ ^* to _{R 7} ^* .

(5) The beginning of the block shall be a V code.

This rule is called Rule 1.

In FIG. 2, times t ₁ , t ₂ , t ₃ , t ₈ and t ₁₀
is a value other than the most frequently occurring value, so according to Rule 1 (1), a Vk code is given as shown in FIG. 2, S10. At times t ₄ and t ₁₁ , Rule 1(2)(a)
A transition code V ₀ ^* is given by , and at time t ₉ , a non-transition code V ₀ is given by (b) of (2).
According to Rule 1 (3) and (4), the most frequently occurring signal from time t ₅ to _{t 7} has a run length of 3. It is represented by R ₃ ^* code, and this code is output at time t ₇ as shown in FIG. 2 S10. The same applies to times _t12 to _t13 .
Although not shown in this figure, when the run length is 8 or more, a transition code is output at the time of the last most frequently occurring value signal, and a non-transition code is output one clock before that. Times t ₁ and t ₁₅ correspond to the beginning of the block, and according to Rule 1 (5), they are given a V code. At this time, if the beginning of the block is the most frequently occurring value, such as at time _t15 , if time _t16 is the most frequently occurring value, a V ₀ ^* code is given, and if it is not the most frequently occurring value, a V ₀ code is given.

FIG. 6 is a diagram showing a specific circuit of the second code generator. In the figure, a multilevel time series signal S1 is passed through a signal line 110 to address input terminals _A2 to read-only memories (ROM) 41 and 42.
A ₀ is supplied. Furthermore, the transition code generation timing pulse S7 is sent to the ROM 41 via the signal line 105.
and 42 address input terminal _A3 .
The timing pulse passes through the signal line 104,
Output control terminals of ROM41 and 42 (e.g. chip
select). Here, all outputs of the ROMs 41 and 42 become 0 when the output control terminal is turned off, and the contents specified by the address lines are output to the output signal lines 120 and 121 only when the timing pulse is on. ROM41 and 42
The contents of can be easily created from FIG. That is, if A ₀ is an address line represented by 2 ⁰ , A ₁ is an address line represented by 2 ¹ , etc., code patterns corresponding to codes V 0 to V 5 are written in addresses 0 to 5 of the ROM41, and code patterns corresponding to codes V ₀ to V ₅ are written in the ROM42. Express the corresponding code length in binary and write it. In addition, at addresses 8 of ROM41 and ROM42, a V ₀ ^* code pattern and a binary code representing code length 2, that is, an output terminal
Write 0, 1, and 0 in the order of O ₃ , O ₂ , and O ₁ .
Note that the code pattern is written so that the output terminal of the ROM 41, for example, on the _O4 side, always has the code of the first bit. For example, if the number of codes is 2 bits, the remaining 2 bits may be 0 or 1. This is the symbol X
For example, the V ₀ ^* code pattern written at address 8 is output as "11XX" from the output terminals O ₄ to O ₁ in this order.

FIG. 7 is a diagram showing a specific circuit of the first code generator. The most frequently occurring signal supplied through the signal line 101 is applied to the clear terminal of the counter 51. The clock pulses supplied through signal line 102 are applied to the clock input terminal of counter 51, and the number of clock pulses during the period in which the most frequently occurring signal is 0 is counted. When the most frequently occurring signal becomes 1, the counter is cleared. The output of the counter 51 is
Address input terminals _A3 to _A0 of ROM51 and 52
supplied to

As in the case of the second code generator, the transition code output timing pulse is sent from the signal line 107 to the ROM5.
2 and 53 address line A ₄ , and
The R code output timing pulse is applied to the output control terminals of the ROMs 51 and 52 through the signal line 106. ROM51 and 52 are respectively,
When the output control terminal is on, the R code corresponding to the run length and its code length are output, and when the output control terminal is off, all outputs are 0.
The contents of the ROMs 51 and 52 can be determined from FIG. 4 in the same manner as the second code generator, so a description thereof will be omitted.

FIG. 8 shows an example of the configuration of the multiplexing circuit 6. The V code and R code supplied through signal lines 120 and 121 are time-division multiplexed by an OR gate 61, and a synchronization code S is multiplexed by a multiplexer 63, and an unequal length code M is outputted to an output terminal 140. The code generator 65 generates a synchronization code S, and in this example, the synchronization code S is a 5-bit code represented by "00001". That is, since the synchronization code S is a code to indicate the start of a block, it is necessary to set it to a code pattern that does not occur from the combination of the V code and R code shown in FIGS. 3 and 4. In this embodiment, the code "00001" is a pattern that does not occur as long as the above-mentioned V code and R code are switched. The multiplexer 63 switches between two input signals in response to a synchronization timing pulse supplied via a signal line 113, and when the synchronization timing pulse is 0, the synchronization code S
Output. Similar multiplexing is performed on a code length signal indicating the code length. That is, reference numeral 62 is an OR gate, reference numeral 64 is a multiplexer, and a time-division multiplexed code length signal N is output to the signal line 141. Since the code length of the synchronization code S is 5, the pattern generator 66 generates a code pattern of "101".

Next, the unequal length code array conversion circuit 7 will be explained. The unequal-length code array conversion circuit 7 is a circuit that extracts a valid unequal-length code designated by n from unequal-length codes including invalid codes and performs array conversion.

FIG. 9 shows a specific circuit diagram of the unequal length code array conversion circuit, and FIG. 10 shows waveforms of each part thereof. The input signal to the conversion circuit 7 includes a 5-bit signal line 1.
unequal length code M (10th
S13) in FIG. 10), a code length signal N indicating the length of the unequal length code supplied via the 3-bit signal line 141 (S14 in FIG. 10), and a sampling clock pulse supplied via the signal line 102. There is. As is clear from FIGS. 3 and 4, the code lengths of the unequal length codes are 2, 3, 4, and 5. Furthermore, if there is no significant unequal length code, the code length is given as 0. Therefore, the 5-bit code provided on signal line 140 includes a mixture of valid and invalid codes. For example, in an unequal-length code given with a code length of 2, only the upper 2 bits of the code on the signal line 140 are valid, and the remaining 3 bits are invalid. Therefore, it is sufficient to remove the invalid code X from the unequal length code M and extract the valid unequal length code. When the operating sampling frequency is as low as several 10 to several 100 KHz, such array conversion of unequal length codes should be performed after parallel/serial conversion of the unequal length code to convert it into a 1-bit signal sequence. is convenient, but the sampling frequency is
If it is as high as 10MHz, the operating speed of serial calculation will be
This will be difficult as it will be around 100MHz. The unequal length code array conversion circuit shown in FIG. 9 is a parallel operation type circuit that overcomes these drawbacks and operates at high speed.
That is, this circuit removes the invalid code from the unequal length code M including the invalid code, repacks the bits, and then outputs the data to the output line 150 as parallel 4-bit data. If this circuit is called a parallel operation unequal length code array conversion circuit, the parallel operation unequal length code array conversion circuit generally converts unequal length codes including invalid codes given by m-bit parallel signal lines. It can be extended to a circuit that removes invalid codes and converts it into 1-bit parallel data.

Next, the operation of the circuit shown in FIG. 9 will be explained. Note that this circuit is an example in which m and l in the above description are set to m=5 and l=4, respectively. The 5-bit unequal length code provided on signal line 140 is applied to first shifter 71 and second shifter 72. A shifter is a type of multiplexer that switches input lines and output lines, and uses, for example, a circuit element such as Am25S10 manufactured by Advanced Micro Devices. 1st
The input terminals of the shifter 71 are I ₁ to I ₈ , and the output terminals are O ₁
~ _O3 , the connection of the input terminals is determined by the number of shifts as follows (signals determining the number of shifts are given by signal lines 141a to 141c).
When the shift number is 0, I ₁ and O ₁ , I ₂ and O ₂ , and I ₃ and O ₃ are connected, and when the shift number is 1, I ₂ and O ₁ , I ₃ and
O ₂ , I ₄ and O ₃ are connected, and generally when the shift number is n, I _1+o and O ₁ , I _2+o and O ₂ , and I _3+o and O ₃ are connected.
The second shifter 72 has four output terminals O ₁ to O ₄ , but the input/output connection operation is similar to that of the shifter 71 .
The output terminals O ₁ to _{O 3} of the first shifter 71 are connected to the input terminals of the register 74, and the output of the register 74 is connected to the input terminals I ₁ to I ₃ of the first shifter 71 and the second
are connected to the input terminals I ₇ to _{I 5} of the shifter. A 4-bit parallel code from which invalid codes have been removed is output to the output terminals O ₄ to O ₁ of the second shifter 72, but the remainder code generated when dividing the unequal length code into 4-bit units is output to the register 74. is temporarily stored.
The number of remainder signs is calculated by modulo arithmetic circuit 73 and register 75. The modulo arithmetic circuit adds binary data indicating the code length of the unequal length code given by the signal lines 141a to 141c and binary data indicating the remainder given by the signal lines 175a and 175b, and divides this by l. Signal line 173
b and 173c to the register 75, and when the addition result is l or more, a carry signal is sent to the AND gate 7 via the signal line 173a.
Give to 6. In this example, since l=4, a normal binary adder can be used as the modulo arithmetic circuit. AND gate 76 creates a write pulse for writing output data into memory when the carry signal is output.

The operation of the conversion circuit will be explained using FIG.
For simplicity, the output (remainder number) of the register 75 at time t ₀ is assumed to be 0. The remainder number is indicated by a signal S15 in FIG. 10, and the result of addition of the code length S14 of the unequal length code and the remainder number S15 is indicated by a signal S16.
At time _t0 , the unequal length code is 5 bits, indicated by "00001", as shown in signal S13. Since this code has more than 4 bits, the terminal O ₄ of the shifter 72 ~
The previous 4 bits, ie, "0000" are output to _O1 . The modulo arithmetic circuit 43 adds the remainder number 0 and the code length 5. At this time, since the addition result is 5, a carry signal 1 is given to the signal line 173a, and the remainder 1 (binary 01) is given to the signal lines 173b and 173c.
Output to. Therefore, at time _t0 , a write pulse is generated as shown by signal S17, and the output data "0000" of shifter 72 is written into the memory as shown by signal S18. The remaining 1-bit code at time t ₀ is output from the input terminal I ₈ of the shifter 71 to the output terminal O ₃ and taken into the register 74 . At time _t1 , the unequal length code is ``10'', which is 2 bits, and the previous remainder code is 1 bit, so the 4-bit data to be written into the memory cannot yet be prepared. The previous remainder bit “1” is transferred from the register 74 to the input terminal of the shifter 71.
Feedback is provided to <sub>I3</sub> . Further, each bit "1" and "0" of the 2-bit unequal length code is applied to input terminals I <sub>4</sub> and I <sub>5</sub> of the shifter 71. At this time, since the number of shifts is 2, these terminals I <sub>3</sub> ~
Bits "1", "1" and "0" of I <sub>5</sub> are output to output terminals O <sub>1</sub> , O <sub>2</sub> and O <sub>3</sub> of shifter 71, respectively, and taken into register 74. register 7
The data "110" taken into the shifter 72 is outputted to the input terminals I <sub>7</sub> , I <sub>6</sub> , and I <sub>5</sub> of the shifter 72 at time t <sub>2</sub> . Also,
At time <sub>t2</sub> , 4-bit data "0011" is on signal line 1.
The signal is input to the shifter 71 through 40. At this time,
Since the shift number of the shifter 72 has a remainder of 3 (the result of addition of the remainder 1 at time t <sub>1</sub> and the code length 2 at time t <sub>2</sub> ), the input terminals I <sub>7</sub> to I <sub>4</sub> of the shifter 72 are connected to the output terminals O <sub>4</sub> to Connected to O <sub>1</sub> . Therefore, time t <sub>2</sub>
The data written to the memory at time <sub>t1</sub> becomes a code ``1100'', which is a combination of the remainder code ``110'' at time t1 and the code ``0'' of the first bit of the 4-bit data input at time _t2 . The remaining 3-bit code "011" out of the 4-bit data is taken into the register 74 via the shifter 71. In this way, the unequal length codes are rearranged and written into the memory every 4 bits.

Generally, if the maximum number of input parallel bits is m bits and the maximum number of parallel bits to be output is l bits, then the first shifter has at least the number of input signals (m+l).
-1) Bit, number of shifts is m, number of output signals is (l
-1) Bits are required. In addition, the second shifter has an input signal number of (2l-1) and a bit shift number of (l-1).
1) The number of output signals required is l bit. If we add an (l-1) bit register for storing surplus bits, an accumulator for counting surplus bits, and a modulo l operation circuit to these shifters, any combination of unequal length codes of 0 to m bits including invalid codes can be created. When input as , it can be array-converted into 1-bit parallel data with invalid codes removed. In this unequal length code conversion circuit, if the number of parallel bits l is set so that surplus bits do not accumulate and overflow (if codes with the maximum code length m occur consecutively, set l = m), It is possible to generate unequal-length codes rearranged in parallel at the same sampling speed as the input data. For example m=
12, l=12, and the sampling rate is 10MHz, the maximum
It can achieve unequal length encoding of 120 Mb/S and is extremely effective for high-speed processing. Note that the shifter is basically a gate circuit that connects an input line and an output line under specified conditions, and is not limited to the circuit element Am25S10 described above.

In addition to the above-mentioned method, various methods can be considered for combining the V code and the R code. for example,
Rules such as the following can be set. This is Rule 2.

(1) Two types of codes, transition code V ^* and non-transition signal V, are assigned to signals other than the most frequently occurring value of the multilevel time series signal, and if the next signal is the most frequently occurring value, it is given the V ^* code,
If the next signal is a signal other than the most frequently occurring value, a V code is given.

(2) For the most frequently occurring signal, its run length is encoded, and the R code is set according to the same rule as in Rule 1 (4).

When encoding according to such a rule, approximately twice the number of V codes is required compared to rule 1, but depending on the statistical properties of the target multilevel time series signal, information compression efficiency may be improved. can. In this case, of course, it is assumed that the unequal length codes to be assigned to each code are optimized.

As another modification to Rule 1, there is a method in which when one block consists of one block from the sync code to the sync code, and there is a run-length code at the end of the block, the last run-length code is not sent.
This scheme is applicable to both Rules 1 and 2 above.

As described above, according to the code conversion and inverse conversion apparatus of the present invention, (1) run-length coding is applied to the most frequently occurring signal value, so compression efficiency is high.

(2) Since unequal length codes based on information theory can be assigned as V and R codes, compression efficiency can be further improved.

(3) Since the V code and R code have both signal level information and code transition information, there is no need for a special code that represents only the transition.

(4) The number of V or R codes that occur at one time in the time series can be reduced to one or less, and since they do not overlap in the time series, the V code and R code can be reduced to one or less.
Time division multiplexing of codes is easy.

(a) The circuit for generating codes with high compression efficiency becomes simple.

(b) Since the R code and the V code can be compressed and encoded using a common unequal length code array conversion circuit, the apparatus is simplified.

Effects such as this can be obtained.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention;
FIG. 2 S1 to S11 are waveform diagrams showing control timing; FIGS. 3 and 4 are diagrams showing examples of the first code and second code of the present invention, respectively; and FIG. 5 is a diagram showing an example of the timing control circuit. The block diagrams shown in FIGS. 7 and 6 are block diagrams showing an example of the configuration of the first and second code generators, respectively.
The figure is a block diagram showing an example of the configuration of a multiplexer, FIG. 9 is a block diagram showing an example of the configuration of an unequal length code array conversion circuit, and FIG. 10 is a block diagram showing an example of the configuration of an unequal length code array conversion circuit.
8 is a waveform diagram illustrating the operation of the unequal length code conversion circuit. In the figures, reference numbers indicate the following: 2... DPCM encoder, 3... Timing control circuit, 4... Second code generator, 5... First code generator, 6... Multiplexer, 7... Unequal length code array conversion circuit, 8... ...Memory, 31, 35...
OR gate, 32...Register, 33...Timing pulse generator, 34...Register, 4
1,42,52,53...ROM, 51...Counter, 61,62...OR gate, 63,64
... multiplexer, 65, 66 ... code generator, 71, 72 ... shifter, 74, 75 ... register, 73 ... adder, 76 ... AND gate.

Claims (1)

[Scope of Claims] 1. An input terminal for receiving a multivalued time series signal expressed in binary with biased occurrence frequency, and detecting a maximum frequency signal value of the multivalued time series signal and determining the maximum frequency. a first code generating means for generating a first unequal length code representing the duration of a signal value; and a second unequal length code representing each signal value of the multivalued time series signal except for the maximum frequency signal. a second code generating means for generating a third unequal length code representing the long code and the maximum frequency signal value and consisting of a transitional code and a non-transitional code; A second unequal-length code representing the signal value is output after the first unequal-length code representing the continuation length in time series of the respective codes, and a second unequal-length code representing the signal value is outputted. Thereafter, code combining means outputs the second unequal length code, and outputs an unequal length code that transitions among the third unequal length codes when two or more of the maximum frequency signal values are consecutive. A code conversion device comprising: