JPH0215143B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] Regarding a digital signal phase control circuit that uses a high-speed clock to generate a clock that has a predetermined phase relationship with an input data signal, the delay time of the switching signal is reduced by reducing the number of delay elements in the switching circuit. The purpose of the present invention is to provide a digital signal phase control circuit which is reduced in size and simplified. a flip-flop circuit that holds a clock output from a clock and outputs the switching signal; and a conversion point detection circuit that generates the conversion point detection signal using the switching signal as a reference. control circuit.

[Industrial application field]

The present invention relates to a digital signal phase control circuit that uses a high-speed clock to generate a clock having a predetermined phase relationship with an input data signal.

In the PCM transmission method that sends and receives data between a PCM terminal station and a data terminal, the digital signal phase control circuit used in the interface between the PCM terminal station equipment and the data terminal is the main transmitter of the PCM terminal equipment. Based on the data terminal, it generates a transmission measure and a clock that is in phase with the input data transmitted from the data terminal.

Therefore, 0 with a frequency n times that of the input data
A clock is generated by inputting either the phase clock or the π-phase clock to a 1/n frequency divider circuit, and at the conversion point (usually the rising point) of the input data, it is switched to the other clock and the phase is changed by 1/2n. If it is determined by phase comparison that the phase of the generated clock is ahead of the input data, the input clock is inhibited by one pulse and the phase is
The clock is delayed by 2n to generate a clock that is in phase with the input data.

Therefore, the output of the 1/n frequency divider circuit is quickly pulled within the range of ±1/2n with respect to the input data, but if there is a delay in the switching signal, the output of the 0 phase and π
As the phase clock becomes faster, the 0 before and after the conversion point
The phase and π-phase clocks cannot be separated by the 1/n frequency divider circuit.

Therefore, there is a need for a simple digital signal phase control circuit that can handle higher speeds.

[Conventional technology]

FIG. 1 shows a conventional digital signal phase control circuit. The conventional digital signal phase control circuit shown in FIG.
A phase control circuit is constituted by DFF) 1, 2, 4, four AND circuits 3, 5, 7, 9, an OR circuit 6, an AND circuit 10 with negative input, and a shift register 11. The shift register 11 and the inverter 12 constitute a frequency divider.

A clock BC synchronized with the clock component in the input data is taken out from the output terminal _Q2 of the shift register 11, and a clock nBC (0 phase) with a frequency n times that of the clock BC and a 0 phase is taken out to the AND circuit 5.
is transmitted to the AND circuit 7.
A π-phase clock nBC (π-phase) with twice the frequency is transmitted.

First, if "1" is output from the Q terminal of DFF4, AND circuit 5 is turned on, and clock nBC (0 phase) is input from OR circuit 6, as shown in Figure 2A. , the AND circuit 10 is turned on and the clock output from the OR circuit 6 is turned on.
nBC (0 phase) is generated on line 109 via AND circuit 10, and a clock pulse as shown in FIG. 2C is applied to shift register 11.

Now, at time _T1 in FIG. 2, when the input data shown in FIG. 2 D is transmitted to the D terminal of DFF1, the clock nBC transmitted to the T terminal thereafter
(0 phase), DFF1 outputs “1” to its output terminal Q.
Output. DFF2 outputs "1" to the terminal when the input of the D terminal is "0", so the above
At time _T2 when "1" is generated at the Q terminal of DFF1, the AND circuit 3 outputs a logic "1".
The output of the AND circuit 3 at this time T ₂ is “1”
Since "1" is applied to the Q terminal of DFF4, "1" is generated at the Q terminal of DFF4, and "0" is generated at the Q terminal. Thus, the AND circuit 7 is turned on, and at time _T3 , the clock nBC(π
phase) is output from the OR circuit 6. This clock nBC (π phase) is then passed through inverter 8.
The voltage is applied to the T terminals of DFF1 and DFF2, and the output of the Q terminal of DFF2 becomes "0", so the AND circuit 3
The output, ie, the conversion point detection signal, is as shown in FIG. 2(E). The output of the Q1 terminal of the shift register 11 whose phase is compared with this conversion point detection signal is the time
When applied to the AND circuit 9 after T ₃ , the other input terminals of the AND circuit 9 are no longer at "0".
is applied, and the AND circuit 9 outputs "0" after all, so the AND circuit 10 with negative input outputs the time
It remains on even after T ₃ , and at time T ₃ , clock nBC (π phase) is output to shift register 1.
1.

In other words, the _clock nBC(0
phase) is transmitted to the shift register 11, and if input data as shown in _FIG .
is transmitted to the shift register 11, but since the input data has been transmitted, the clock nBC (π phase) is transmitted to the shift register 11 at time _T3 , which is 1/2 earlier than time _T4 , and thereafter this clock nBC( π
phase) will be transmitted to the shift register 11. This clock nBC (π phase) is frequency-divided by the shift register 11 and becomes the output BC of the phase control circuit. Therefore, this output BC becomes a clock controlled to advance by a half phase of nBC after the input data exchange point _T1 as described above, and follows the input data by this amount. By repeating this process, the output of the shift register and the input data become synchronized in phase.

Moreover, as the synchronization state progresses further, the phase of the output of the shift register will conversely advance. In this example, as shown in FIG. 2b and f, the _Q1 terminal voltage output from the shift register 11 is transmitted at time _T3 ',
As shown in Figure 2b and d, the conversion point of the input data occurs at time T2', and as shown in Figure _2b and e, the conversion point detection signal rises at time _T3 '. is configured to determine that the phase of the output is leading. In such a case, the following control is performed. The input data is transmitted to DFF1, and "1" is generated at its Q terminal at time T ₃ '.
When "1" is generated from the AND circuit 3, the other input terminal of the AND circuit 9 is connected to the shift register 11.
“1” is applied from _Q1 terminal. Therefore, from the AND circuit 9, "1" is output as shown in FIG.
is output, and the AND circuit 10 with negative input is therefore turned off. Therefore, the clock nBC to be applied to the shift register 11 at time T ₄ '
(0 phase) clock pulse is generated by the above AND circuit 10.
clock nBC at time T ₆ ′.
(0 phase) is applied to the shift register 11, and thereafter the shift register is controlled by this clock nBC (0 phase), and the output BC of the phase control circuit is generated from the _Q1 terminal. At this time, the pulse that should normally be transmitted to the shift register 11 at time T ₄ ' is transmitted to the shift register 11 at time T ₆ ' as described above, and based on this, the pulse is transmitted to the shift register 11 at time T 4 '.
Since BC is generated, the control is performed so that it is delayed by a half phase of nBC. At the next conversion point, the phase of the clock output from the shift register is delayed, so the control as shown in FIG. 2a is performed, and then the control as shown in FIG. 2b is performed. In other words, it moves within a range of ±1/2n relative to the phase of the input data.
If this n is large, it can be considered that they are substantially synchronized.

In FIG. 1, a switching circuit (clock switching circuit) K is connected to a flip-flop circuit (FF circuit) 1,
2 constitutes a conversion point detection circuit S, the FF circuit 4 constitutes a control signal generation circuit, and the AND circuit 9 constitutes a phase comparison means.

Further, the AND circuit 10 with negative input is shown in principle, but is actually realized by an OR circuit, and when the output of the AND circuit 9 is "1", the switching period P in FIG. 3C is "1". As a result, the high level of the 0-phase and π-phase clocks around the switching point 13 continues, and as a result, one clock input immediately after switching is prohibited.

As described above, in the conventional digital signal phase control circuit, the conversion point detection circuit S detects the conversion point of input data, generates a conversion point detection signal for phase comparison, and sends this conversion point detection signal to the FF circuit 4. A switching signal is generated by dividing the frequency by , and the phase of the clock generated from the shift register 11 is controlled by ±1/2n for each input data by phase comparison.

[Problem to be solved by the invention]

In the circuit operation described above, since the switching signal is delayed relative to the rising edge of the input data, when handling high-speed 0-phase and π-phase clocks, the pulse width P at switching point 13 (Fig. 3) becomes narrower. , the 1/n frequency dividing circuit becomes unable to follow. As a result, the frequency of input data and the frequency of output data end up being unequal, and the original purpose of phase control cannot be achieved.

The delay time of the switching signal and the clock at the switching point will be mainly explained with reference to FIG. A, B, C, and D in the same figure are enlarged versions of C, D in Figure 2. Further, a to d indicate waveforms at points a to d in FIG.

In Figures 1 and 3, waveform a is output from FF circuit 1 by 1 depending on the input data, and
Waveform b is output by FF circuit 2, and AND circuit 3
Waveform c is output. By the operation of outputting the above waveforms a, b, and c, a switching signal d for controlling the switching circuit K is outputted from the FF circuit (or also referred to as a 1/2 frequency divider circuit) 4.

A clock signal is output from the switching circuit K by this switching signal d. With respect to the rising edge of the clock, waveform a is delayed by _t1 , waveform c is delayed by _t1 + _t2 , and switching signal d is delayed by _t1 + _t2 + _t3 . When switching the switching circuit K using the switching signal d, the clock width Δt immediately before switching among the clocks output from the switching circuit K becomes t ₁ + t ₂ + t ₃ , and the time P from the switching point 13
After the time has elapsed, the clock after switching starts.

Therefore, if there is a delay in the switching time, that is, if the clock width Δt immediately before switching is larger than the clock frequency, the width P becomes narrower and the 1/n frequency dividing circuit cannot follow it. As a result, the frequency of the input data and the frequency of the output data are not equivalently equal, resulting in a disadvantage that the phases are also different.

In view of the drawbacks of the conventional digital phase control circuit, an object of the present invention is to provide a simplified digital signal phase control circuit by reducing the number of delay elements in the switching circuit and reducing the delay time of the switching signal. .

[Means to solve the problem]

In order to achieve the above object, the present invention comprises a frequency dividing circuit that divides the frequency of the input digital signal, and an output of the frequency dividing circuit that holds the clock output from the clock switching circuit. A digital signal phase control circuit comprising: a flip-flop circuit that outputs the switching signal; and a conversion point detection circuit that generates the conversion point detection signal using the switching signal as a reference.

[Effect]

Since the switching signal, which is a control signal to the switching circuit, is input to the switching circuit via only one FF circuit, the number of delay circuits is limited to that of the FF circuit. Therefore, the time required for clock switching is reduced. Therefore, the clock width immediately before switching becomes wider, and the frequency dividing means does not malfunction.

〔Example〕

The present invention will be explained below based on the embodiment shown in FIG. 4 and the time chart shown in FIG.

In Figure 4, 1, 2, 4 to 12, K are the first
The same parts with the same functions as in the figure are shown.

Note that the frequency divider circuit that divides the input digital signal is
The flip-flop that generates the switching signal is connected to the FF circuit 4, the conversion point detection circuit S' is connected to the FF circuit 1, FF circuit 2, and the EXOR circuit 15, and the control signal generation circuit is connected to the conversion point detection circuit S' and the EXOR circuit 15. Each corresponds to circuit 4.

The configuration shown in FIG. 4 corresponds to placing an FF circuit before the conversion point detection circuit S in FIG. Since the switching signal is held in the FF circuit 1 and outputted from the switching signal Q, *Q (inverted output of Q) terminal, the delay of the switching signal with respect to the clock is only the delay of the FF circuit 1, that is, _t1 .

Furthermore, since the conversion point detection signal is generated by exclusive ORing the outputs of the FF circuits 1 and 2, the delay with respect to the switching signal is extremely small.

In FIG. 4, before the input data 2 shown in FIG. 5 is input, the waveform shown in FIG. 5c is output from the Q terminal of the FF circuit 1 as explained in FIG. It is output from the switching circuit K.

Next, the input data shown in FIG. 5 is input to the D terminal of the FF circuit 4, the frequency is divided by 1/2 as shown in FIG. Then, the waveform shown in FIG. 5b is output from the Q terminal, and the waveform shown in FIG. 5c is output from the terminal. The switching circuit K is switched using these waveforms b and c, and the fifth
The 0-phase waveform clock shown in FIG. 5B and the π-phase clock shown in FIG. The frequency is divided by an n frequency divider 11. The waveform of Fig. 5d output from FF circuit 2 and
What is the waveform of Fig. 5b output from FF circuit 1?
The signal is input to the EXOR circuit 15 and outputs the conversion point detection signal shown in FIG. 5e.

Since the switching signals of waveforms b and c are delayed by _t1 time from the clock shown in FIG. 5c, the clock switching point 13 is delayed only by the delay time _t1 as shown in FIG. The delay time t ₁ + shown in the figure
The time t ₂ +t ₃ is reduced from t ₂ +t ₃ =Δt, so that the switching period P becomes longer and the 1/n frequency division does not malfunction.

With the above circuit operation, the 1/n frequency divider 11
A clock synchronized with input data can be obtained from the Q ₁ and therefore Q ₂ terminals.

〔Effect of the invention〕

As explained above, in the present invention, the input data is frequency-divided by 1/2, and the frequency-divided wave is held in the flip-flop circuit by the clock output from the clock switching circuit and used as a switching signal, so the delay time is only t ₁ . Therefore, the delay time t ₁ + of the conventional switching signal
t ₂ + t ₃ can be reduced by t ₂ + t ₃ hours.
This has the advantage that the 1/n frequency divider is less likely to malfunction due to the clock at the switching point since the input data is switched using a switching signal with a short delay time.

[Brief explanation of drawings]

Figure 1 is a conventional digital phase control circuit, Figure 2 is a diagram showing a time chart of the circuit in Figure 1, and Figure 3 is a diagram showing a time chart of the circuit in Figure 1.
The figure is an enlarged view of the time chart in FIG. 2, FIG. 4 is an embodiment of the present invention, and FIG. 5 is a diagram showing the time chart. In the figure, 1, 2, 4...FF circuit, 3, 5, 7,
9,10...AND circuit, 6...OR circuit, 8,
12...Inverter, 11...Shift register,
13...Clock switching point, 15...EXOR
Circuit, K...Clock switching circuit, S, S'...Conversion point detection circuit.

Claims (1)

[Scope of Claims] 1. A clock switching circuit that switches and outputs either a 0-phase clock or a π-phase clock having a frequency that is an integral multiple of an input digital signal according to a switching signal, and the clock switching circuit. frequency dividing means for dividing the frequency of the clock output from the clock to generate a predetermined clock; and a control for detecting a conversion point of the input digital signal and sending a switching signal to the clock switching circuit and a conversion point detection signal. a signal generating circuit; and a phase comparison means for comparing the conversion point detection signal with the output of the frequency dividing means and prohibiting input of the clock to the frequency dividing circuit when the output of the frequency dividing means is advanced. A digital signal phase control circuit that outputs a clock having a predetermined phase relationship with an input digital signal from the frequency divider circuit, the control signal generation circuit comprising: a frequency divider circuit 4 that divides the frequency of the input digital signal; The output of the frequency dividing circuit 4 is transferred to the clock switching circuit K.
a flip-flop circuit 1 which outputs the switching signals b and c held by a clock output from the converter, and a conversion point detection circuit 2 which generates the conversion point detection signal e using the switching signals b and c as a reference. A digital signal phase control circuit characterized by: