JPH0216054B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a variable delay circuit for digital data in a PCM-TDMA device or the like.

For example, in a satellite communication circuit line PCM-TDMA space diversity device, two ground stations are installed 10 to 30 km apart, and when the signal from the satellite is attenuated by rain, etc., in order to obtain a specified line efficiency. , a method of switching from an active station to a standby station is adopted. In this case, delay circuits are inserted in the reception paths of both routes in order to compensate for the propagation delay time difference (300 to 100 μs) between the two stations and the movement of the satellite itself.

The most common method for delaying such digital signals is to use flip-flops. FIG. 1 is a block diagram showing the configuration of a conventional variable delay circuit using flip-flops.

In Figure 1, 1 is a data input terminal, 2 _-1 ,
2 _-2 , 2 _-3 , . . . , 2 _-(o-1) , 2 _-o are flip-flops (FF), 3 is a multiplexer (MUX), 4 is a control signal input terminal, and 5 is a data output terminal.

When data is input from terminal 1, the data is transferred to flip-flops 2 _-1 , 2 _-2 , 2 _-3 , ..., 2 _-(o
-1) , 2 _-o are sequentially shifted in accordance with a constant clock. Now, by taking out data from an arbitrary flip-flop via the multiplexer 3 using a control signal from the control terminal 4, a delay of an arbitrary time can be given. In this way the first
With the circuit shown in the figure, an arbitrary delay time is given by a control signal given from the outside. A variable delay circuit can be configured.

However, the circuit shown in FIG. 1 requires a number of flip-flops corresponding to the amount of time to be delayed, and when the amount of delay increases, it causes difficulties in construction and is uneconomical.

To achieve this objective, the variable delay circuit of the present invention includes a counter that determines the amount of delay in 1-bit units until the input digital data is output, and a counter that determines the amount of delay in units of 1 bit until the input digital data is output. a first serial-to-parallel conversion means for converting the input data into a plurality of bits of the input data; and means for cyclically generating a read address and a write address having an address difference corresponding to the upper bits of the counter, respectively, for each plurality of bits of the input data. , a memory that reads and writes the parallel data according to the read address and write address, and provides a delay amount in units of multiple bits according to the address difference; and a parallel memory that converts the parallel data from the memory into serial data. a serial conversion means, and a second circuit that inputs the serial data and outputs a plurality of data delayed one bit at a time in parallel.
and selecting data corresponding to the lower bits of the counter from a plurality of data from the second serial-to-parallel converting means and providing a delay amount in units of 1 bit within the plurality of bits. By providing a delay/advance command to the counter, the input digital data can be output after being delayed by an arbitrary delay amount in units of one bit.

The principle and embodiments of the present invention will be explained below.

FIG. 2 is an explanatory diagram showing the basic principle of the variable delay circuit of the present invention, and FIG. 3 is a time chart showing the operation of the circuit shown in FIG.

In FIG. 2, the memory 6 is written with input data from the input terminal 7 according to the write address,
Data is read out to the output terminal 8 according to the read address. Addressing alternates between writing and reading, and the speed is twice the speed of data input. Further, the write address and the read address are configured to advance sequentially and circulate with a difference of N addresses.

Therefore, in FIG.
The data written in is read out to the output terminal 8 after N time. Therefore, the desired amount of delay can be freely changed by changing the difference N between the write address and the read address.

In FIG. 3, (a) represents addressing, (b) represents input data, and (c) represents output data. Now, if input data A is written by addressing write address (WA) #N, then data A is read out by addressing read address (RA) #N and taken out as output data. . Next, input data B written by write address #(N+1)
is read out using the read address #(N+1), and thereafter data written in the same manner is always read out with a difference of N.

However, memory is generally slower than flip-flops, which is disadvantageous when handling high-speed data. Therefore, in the present invention, a first serial/parallel converter and a parallel/serial converter are provided before and after the memory to perform a delay operation in units of multiple bits of input data, so that a low-speed memory can be used. Thereafter, using a second serial/parallel conversion means that can obtain a plurality of data delayed by one bit in parallel, such as flip-flops _2-1 to _2-o in FIG. Perform the following delay operation in 1-bit units. and,
Each delay amount is controlled by the upper and lower bits of one counter.

FIG. 4 is a block diagram showing the configuration of one embodiment of the variable delay circuit of the present invention. In the same figure, 1
1 and 12 are binary counters (BCNT), 13 is an adder (ADD), and 14 is a 2-1 selector (2-1
1SEL), 15 is serial/parallel conversion shift register (SPSR), 16 is buffer register (BR), 17
is a random access memory (RAM), 18 is a parallel/serial conversion shift register (PSSR), 19 is a serial/parallel conversion register (SPSR), 20 is a multiplexer (MUX), 21 is a data input terminal, 22 is a delay/advance command terminal, 23 is a data output terminal.

BCNT11 is a counter that counts the clock _f2 obtained by dividing the basic clock signal _f0 by four;
A read address signal for 17 is generated.

BCNT12 is a counter for determining the difference between the read address and the write address,
The amount of delay in the variable delay circuit shown in FIG. 4 is determined by the count value of BCNT 12. BCNT12
is composed of an up-down counter,
The count value is increased or decreased by a delay/advance command given from the terminal 22, and the delay amount can not only be fixedly determined but also variably controlled.

ADD13 adds the upper bits of the count value of BCNT11 excluding the lower two bits and the upper bits of the count value of BCNT12 excluding the lower two bits.
The output of ADD13 becomes a write address signal for RAM17.

The 2-1 SEL 14 alternately switches the write address of the ADD 13 and the read address of the BCNT 11 using a clock _f1 obtained by dividing the basic clock signal by two, and inputs the address signals to the address line of the RAM 17.

The SPSR 15 is a 4-bit shift register, which receives serial data from the input terminal 21, converts it into 4-bit parallel data, and outputs it.

BR16 holds the 4-bit parallel data from SPSR15 for four clock periods of clock _f0 .
Writing to BR16 is performed by clock _f2 in synchronization with writing to RAM17.

The RAM 17 consists of a memory having a 4-bit×N word structure, and data is written and read out alternately in parallel in groups of 4 bits. Therefore, the maximum amount of data delay in the circuit of FIG. 5 is 4N bits.

Next, PSSR 18 receives the 4-bit parallel data read out from RAM 17 at clock _f3 , converts it into serial data, and outputs it. The output of PSSR 18 has a delay amount determined by the difference between the write address and read address of RAM 17, and the delay amount is therefore 4-bit steps (4-bit unit).

The SPSR 19 receives serial data from the PSSR 18, converts it into 4-bit parallel data, and outputs it.

MUX 20 selects an appropriate bit from the 4-bit parallel data output of SPSR 19. MUX20
is the lower 2 of the count value of BCNT12 that determines the amount of delay
Controlled by bits. Therefore, the output terminal 23
The amount of delay in the output data of MUX20 obtained in
The bit step delay amount is obtained.

FIG. 5 is a time chart showing the operation of the circuit shown in FIG. In the figure, (a) represents the basic clock signal f ₀ , (b) represents the clock signal f ₁ obtained by dividing the basic clock signal f ₀ by 2, and (c) represents the basic clock signal f 0.
It represents the clock signal f ₂ obtained by dividing f ₀ by four. Further, (d) shows a clock signal f ₃ which has the same period as the clock signal f ₂ but has a phase different by x. (e) represents the read address signal generated by BCNT11, (f) represents the switching selection between the read address signal (RD) and write address signal (WRT) by 2-1SEL14, and (g) represents the RAM 17 generated by this. addressing. (h) is input data at input terminal 21, (i) is
Input data of the RAM 17, (j) represent output data of the RAM 17, and (k) represent output data of the PSSR 18. (l) is the output data of the MUX 20, and shows that a variable delay amount of 1 bit step can be obtained by selecting the delay amount.

In this way, the variable delay circuits shown in FIGS. 4 and 5 use memory to configure the delay circuits, so compared to conventional variable delay circuits that use only flip-flops, the data rate can be increased. It is possible to significantly reduce the amount of hardware without slowing down. Even if it is necessary to further increase the amount of delay, there is an advantage that it can be easily handled by increasing the number of words of the RAM being used and by increasing the counting period of the BCNTs 11 and 12. Furthermore, when delaying a burst signal as in TDMA communication, it is possible to change the amount of delay even during operation by controlling the amount of delay at a timing portion where no data is included. Furthermore, since the delay amount in units of multiple bits and the amount of delay in 1-bit units are set using the upper and lower bits of one counter, it is easy to set the delay amount, and when the overall delay amount is changed, Since the delay amount for each unit is automatically adjusted by the carry function inherent in the counter, the delay amount can be easily changed.

FIG. 6 is a block diagram showing the structure of another embodiment of the variable delay circuit of the present invention. In the figure, symbols 11, 12, 14, 15, 16, 17, 18,
The representations 19, 20, 21, 22, and 23 are the same as in the case of FIG. 4, and their operations are also the same. 24 is a binary counter (BCNT).

In FIG. 6, 11 is a counter that generates a read address signal for the RAM 17;
This is no different from the case in Figure 4. 24 is a counter for generating a write address, and is a counter for storing the amount of delay, similar to the case in FIG.
By adding the delay amount signal from BCNT12 to its load terminal, the delay amount can be arbitrarily set, and the count value of BCNT12 and the delay amount N can be set arbitrarily.
It is possible to generate count values that differ by only

Therefore, the read address signal of BCNT11 and
BCNT24 write address signal and 2-1SEL
By switching and selecting by 14, it is possible to operate in exactly the same way as in the case of FIG.

As explained above, according to the variable delay circuit of the present invention, by using memory, a large amount of delay can be obtained with a small amount of hardware, and the variable delay circuit can easily vary the amount of delay. Therefore, it is extremely effective for use in PCM-TDMA devices and the like.

[Brief explanation of drawings]

Figure 1 is a block diagram showing the configuration of a conventional variable delay circuit, Figure 2 is an explanatory diagram showing the basic principle of the variable delay circuit of the present invention, and Figure 3 is a time chart showing the operation of the circuit in Figure 2. , FIG. 4 is a block diagram showing the configuration of one embodiment of the variable delay circuit of the present invention, and FIG.
The figure is a time chart showing the operation of the circuit in Figure 4.
FIG. 6 is a block diagram showing the structure of another embodiment of the variable delay circuit of the present invention. 1: Data input terminal, 2 _-1 , 2 _-2 , 2 _-3 ,...
..., 2 _-(o-1) , 2 _-o : flip-flop (FF),
3: Multiplexer (MUX), 4: Control signal input terminal, 5: Data output terminal, 6: Random access memory (RAM), 7: Data input terminal,
8: Data output terminal, 11, 12: Binary counter (BCNT), 13: Adder (ADD), 14:
2-1 selector (SEL), 15: serial/parallel conversion shift register (SPSR), 16: buffer register (BR), 17: random access memory (RAM), 18: parallel/serial conversion shift register (PSSR), 19: Serial/parallel conversion shift register (SPSR), 20: Multiplexer (MUX), 2
1: Data input terminal, 22: Delay/Advance command terminal, 23: Data output terminal, 24: Binary counter (BCNT).

Claims (1)

[Claims] 1. A counter that determines the amount of delay in 1-bit units until input digital data is output; and a first series-parallel circuit that converts the input data into parallel data of multiple bits for each multiple bits. converting means; means for alternately and cyclically generating read addresses and write addresses having an address difference corresponding to the upper bits of the counter for each of a plurality of bits of the input data; a memory that reads and writes the parallel data according to the address difference and provides a delay amount in units of multiple bits according to the address difference; a parallel-to-serial converter that converts the parallel data from the memory into serial data; a second serial-to-parallel conversion means for outputting in parallel a plurality of data inputted and delayed by one bit; and a second serial-to-parallel conversion means for outputting data corresponding to the lower bits of the counter among the plurality of data from the second serial-to-parallel conversion means. and a selection means for providing a delay amount in units of 1 bit within the plurality of bits, and outputs the delayed input digital data by an arbitrary delay amount in units of 1 bit by giving a delay/advance command to the counter. A variable delay circuit characterized by being capable of