JPH0216617B2 - - Google Patents

Description

[Detailed description of the invention]

[Field of Industrial Application] This invention relates to an automatic frequency fast-forwarding circuit in a wireless communication device that combines a CPU and a hard counter to change the transmitting and receiving frequencies using clock pulses from a dial encoder. be. [Prior Art] A dial encoder (or shaft encoder) is a pulse generator that is installed on a dial or a shaft connected thereto and generates clock pulses in proportion to the rotational speed of the dial or shaft. In digitally tuned communication equipment, the clock pulses generated by the dial encoder are processed by a hard drive, such as an up/down counter.
Digital data obtained by integrating with a counter
By setting the oscillation frequency as the frequency control input of the PLL controlled oscillator, this system has the same feeling as the analog tuning method, but is characterized by much more precise and stable tuning than the analog method. In addition, in recent communication devices, the CPU (Central
Many of these devices use a processing unit (Processing Unit), and these devices utilize the available CPU functionality to process frequency settings and frequency display data using interrupt operations. Dial encoder operation is similar to analog tuning, in that the faster you turn the dial, the faster the frequency will change, and the slower you turn the dial, the slower the frequency will change. However, in devices that require fine frequency adjustment such as for SSB reception, the amount of frequency change per dial rotation is 10kHz or 1kHz.
Assuming that the bandwidth is 1MHz,
To move from one end of the band to the other, 10kHz/
It must be 100 revolutions per turn, and 1000 revolutions at 1kHz/time. In order to cope with this, some devices are equipped with a switch that changes the frequency change rate of the dial to a large or small value, but this involves the inconvenience of having to change the switch according to the amount of frequency change. Therefore, when the dial is slowly turned, the frequency can be adjusted at a fine rate of change, and when the rotation speed exceeds a certain level, the frequency can be automatically fast-forwarded at a large rate of change, and when the dial is around the automatic frequency, the dial rotation can be adjusted. A method has already been put into practical use that allows for easier tuning by slowing down the frequency to produce finer changes in the original frequency. One way to do this is when the number of cycles per unit time of the encoder's clock pulses exceeds a predetermined value, a pulse increase circuit or pulse multiplier circuit operates to increase the cumulative number of pulses of the counter and increase the rate of frequency change. . [Problems to be Solved by the Invention] The circuit configuration for changing the frequency adjustment speed described above is complex, and the increase in clock pulse frequency may exceed the processing frequency of the hard counter or CPU, or the clock pulse frequency may exceed the processing frequency of the hard counter or CPU. The production problem of being constrained in quality selection cannot be ignored. The present invention has been made in view of the above points, and
By combining the functions of a hard counter and CPU with two digital gates, the aim is to improve the rate of change in frequency during fast forwarding. [Means for solving the problem] Add the clock pulse of the dial encoder to the A input of the NAND gate through a time constant circuit and inverter, connect the appropriate digit of the output of the hard counter to the B input, and output the NAND gate. This is a circuit configuration in which the carry output of the hard counter is connected to the A and B inputs of the AND gate, and the output of the AND gate is added to or subtracted from the middle or upper digit of the CPU. [Embodiment] FIG. 1 is an automatic frequency fast forwarding circuit diagram showing an embodiment of the present invention, which will be explained with reference to the drawings. The clock pulses from the dial encoder 1 are fed to the clock input CK of the hard counter 2, and are also applied to the A input of the NAND gate 5 through the time constant circuit 3 and, if necessary, through the inverter 4. The B input selects and connects an appropriate digit from the data outputs Q ₁ to _{Q 4} of the hard counter 2, and connects the output of the NAND gate 5 and the carry output CA of the hard counter 2 to the A input of the AND gate 6 and the B input. Connect each input to the same
By having a circuit configuration in which the output of the AND gate 6 is added to or subtracted from the middle or upper digits of the frequency data of the CPU 7, the frequency is designed to increase the ratio of frequency change to the dial rotation angle as the dial rotation speed increases. It is a fast forward circuit. The middle digits output from CPU 7, the upper digits, and the lower digits output from hard counter 2 are
The frequency is set by configuring the signal to be input to the programmable counter 8a of the PLL circuit 8. Next, the operation of FIG. 1 according to the present invention will be explained in contrast with FIG. 2 which shows the operation waveforms of each part of FIG. 1. The clock pulse output from the dial encoder 1 is a negative pulse for the circuit shown in FIG. 1, but if positive pulse control is required, it may be passed through an inverter. The time constant circuit 3 located between the dial encoder ₁ and the inverter ₄ is a kind of integrating circuit. When a negative pulse is input from the dial encoder ₁ , the resistor _R2 is connected in parallel with the resistor _R1 via the diode D, and the time constant formed by the capacitor C is small. Conversely, when the negative pulse disappears, diode D is cut off, and the time constant at this time is determined by resistor _R1 and capacitor C. That is, the input of a negative pulse is a time constant for fast charging, and the time constant for discharging becomes long if there is no input of a negative pulse. Therefore, when a constant number of pulses are input per unit time, a substantially constant stored potential determined by the charging circuit and the discharging time constant can be obtained. Therefore, when a negative pulse is input to the time constant circuit 3, a negative charge is accumulated in the capacitor C and a negative potential is exhibited. When the dial encoder 1 rotates faster, the number of pulses generated increases, the amount of charge in the capacitor C increases accordingly, and the discharging time also decreases by the pulse signal, increasing the negative potential. The signal in Fig. 2 is the time constant circuit 3.
shows the output signal of Although it is different from the actual situation, for the sake of explanation, the rotation of the dial encoder 1 is assumed to be at three speeds per revolution, and each speed is set to ,.The output signal of the time constant circuit 3 has level fluctuations due to charging and discharging, but it is an average value. It is shown with the unevenness removed in consideration of this. Therefore, while comparing the number of pulses and the output signal of the time constant circuit, the number of pulses is small at the speed of the dial encoder 1 mentioned above. Therefore, since the number of times of charging is also small, the negative potential is slightly lower than the normal level. Next, when the rotation is slightly increased and the number of pulses in the section is output, the number of charging times per unit time increases, and the output signal of the time constant circuit 3 becomes a more negative potential than in the section. Furthermore, as the rotation of dial encoder 1 is increased and the number of pulses increases as shown in the section, the signal level will change to inverter 4.
becomes below the input threshold level of , and the output of inverter 4 is inverted from L level to H level. The actual pulse signal is dial encoder 1
Although the rotational speed of the inverter 4 gradually increases and decreases, the signal only needs to be below the input threshold of the inverter 4. On the other hand, pulses are also applied to the CK input of hard counter 2, providing frequency data outputs Q ₁ to _{Q 4} .
It is also input to the lower digits of the parallel inputs of the programmable counter 8a of the CPU 7 and PLL circuit 8. CPU7
The frequency data Q ₁ to Q ₄ input to is divided and
Frequency data Q ₁ is 1/2 of the input clock, frequency data Q ₂ is 1/4, frequency data Q ₃ is 1/8, and frequency data Q ₄ is 1/10 of the input clock. In other words, the signal shown in Figure 2 is output. That's it. Therefore, there is an advantage that the operating frequency of the CPU 7 can be lower than that of the counter. When the output of inverter 4 and the output of counter 2 are added to the A and B inputs of NAND gate 5, the output X becomes L only when both inputs are H according to the truth table in Table 1, and under other conditions. All H
Therefore, it becomes as shown in Figure 2.

【table】

〔Effect of the invention〕

This is done by increasing or decreasing the frequency data applied from the hard counter to the PLL circuit through the CPU using the interrupt pulse applied to the CPU through the NAND gate and the AND gate during the frequency fast forward operation according to the present invention, unlike the conventional method. Compared to the fast-forward method that increases the number of input clock pulses, the hard counter does not increase the load at all, and since it increases only the middle and upper digit pulses with a small number of operating pulses on the CPU, there are no restrictions on the upper limit frequency of operation. This has the advantage of not being subject to

[Brief explanation of drawings]

FIG. 1 is a frequency automatic fast-forwarding circuit diagram showing an embodiment of the present invention, FIG. 2 is an explanatory diagram of operation waveforms of each part in FIG. 1, and FIG. 3 is a flowchart. 1...Dial encoder, 2...Hard encoder
Counter, 3... Time constant circuit, 4... Inverter, 5... NAND gate, 6... AND gate,
7... CPU, 8... PLL circuit, 8a... programmable counter, C... capacitor, R ₁ , R ₂
...Resistance, D...Diode.

Claims (1)

[Claims] 1. Input the frequency setting clock pulse to the programmable frequency divider of the local oscillation PLL circuit as the lower digit of the BCD signal via the hard counter, and input the output signal of the hard counter.
In a wireless communication device that inputs the middle digits and upper digits of the BCD signal to the CPU and inputs them to the programmable frequency divider to set the frequency, the clock pulse is connected to the hard counter and the charging time constant. is input to a time constant circuit configured to have a short discharge time constant and a long discharge time constant, and the output of the time constant circuit is
It is charged to a negative potential according to the clock pulse input rate, and when it exceeds a certain pulse input rate, it becomes below the threshold voltage and the output side becomes H level.Connected to an inverter, and input the output of the inverter.
In addition to the A input of the NAND gate, the B input of the NAND gate is connected to select and input the output data terminal of the hard counter.
The output of the NAND gate and the carry output of the hard counter are connected to the A and B inputs of the AND gate, respectively, and the output of the AND gate is connected to the CPU.
The hard counter is configured to add to or subtract from the middle-order digit or high-order digit generated by the hard counter, and when the number of input clock pulses exceeds a certain value, the rate of frequency change is increased in accordance with the output selection of the hard counter. Frequency fast forwarding circuit featuring