JPH0217879B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory device suitable for a programmable ROM in which data can be electrically erased.

EP-ROM (Erasable Programmable-ROM)
Data can be written or erased after manufacturing, and there are two main types: ultraviolet erasable types and electrically erased types. Among these, ultraviolet-erasable EP-ROMs can be highly integrated because one memory cell can be configured with one transistor, and to date, models with 32K-bit and 64K-bit integration have been developed. has been done. However, this ultraviolet-erasable type requires a package that allows ultraviolet light to pass through, making it expensive. On the other hand, the electrically erasable type (especially E ² P-ROM (Electrically Erasable)
Since one memory cell consists of at least two transistors, it is not possible to increase the degree of integration very high, and to date,
Only those with a density of 16K bits have been announced. However, this electrically erasable type has the advantage of being able to use inexpensive plastic as a package, thereby reducing manufacturing costs.

Of these, FIG. 1 is a configuration diagram showing one memory cell portion of a conventional E ² P-ROM, which was announced at the ISSCC in February 1980, in which one memory cell is composed of two transistors. In the figure, 1 is a digit line, 2 is a selection line, and 3 is a data program line. Between the digit line 1 and the ground potential point are a MOS transistor for bit selection, a control gate and a floating gate for data storage. A double gate type MOS transistor 5 having a MOS transistor 5 is connected in series. The gate of the one MOS transistor 4 is connected to the selection line 2, and the control gate of the other MOS transistor 5 is connected to the data program line 3.

The conventional E ² P-ROM having such a configuration has the following drawbacks.

As is clear from Figure 1, since one memory cell is composed of two transistors, the number of elements is twice as high as that of the ultraviolet erasable type, and the degree of integration is half. It is disadvantageous to become

When writing and erasing data, voltages with both positive and negative polarities are required, and when mounted on a printed wiring board or the like, a power source with both positive and negative polarities is required to electrically rewrite data.

It is difficult to erase data simultaneously in word units or all bit units.

It is difficult to erase all bits of data in a short time.

It is impossible to erase data with a single 5 volt power supply.

The present invention has been made in view of the above-mentioned circumstances, and although the above-mentioned drawbacks can be eliminated,
It is an object of the present invention to provide a semiconductor memory device which can perform data erasing well and can quantitatively detect the state of data writing.

An embodiment of the present invention will be described below with reference to the drawings. FIGS. 2a to 2d show the structure of a memory cell according to a first embodiment of the present invention, and only four bits of memory cells are shown. Of these, Figure 2 a is a pattern plan view, and Figure 2 b is the same figure a.
FIG. 2c is a structural sectional view taken along the line -' in FIG. 2a, and FIG. 2d is a structural sectional view taken along the line -' in FIG.

In FIG. 2, reference numeral 11 denotes a semiconductor substrate made of P-type silicon, and on the surface of this substrate 11, gate insulating films 12a, 12b, 12c, and 12d are arranged at regular intervals in an XY matrix shape.
Further, on the surface of the substrate 11, gate insulating films 12a and 12 are formed at two locations adjacent to each other in the vertical direction in the figure.
c, 12b and 12d are paired, and a field insulating film 13 is formed between the pair of gate insulating films. Moreover, on this field insulating film 13, P
Alternatively, a first conductor layer 14 made of polysilicon containing As is formed. Further, on each of the gate insulating films 12a, 12b, 12c, and 12d, a second conductor layer 1 made of polysilicon is provided.
5a, 15b, 15c, and 15d are formed separately from each other. The right end portions of the two second conductor layers 15a and 15c located on the left side with respect to the first conductor layer 14 in the figure are connected to the It overlaps with the left end of the first conductive layer 14. Further, the left end portions of the two second conductive layers 15b and 15d located on the right side with respect to the conductive layer 14 are connected to the right end portions of the conductive layer 14 via the insulating film 16. It overlaps with Furthermore, second conductor layers 15a and 15 adjacent in the left and right direction in the figure
A third conductor layer 18A made of polysilicon and having a width set to be approximately the same as both conductor layers 15a and 15b is formed on the conductor layer 18A with an insulating film 17 interposed therebetween so as to cover this conductor layer 18A. Similarly, the second conductor layer 1 adjacent in the left and right direction in the figure
5c, 15d are covered with conductive layers 15c, 15d via the insulating film 17.
Another third conductor layer 18B made of polysilicon and having a width set to be approximately the same as that is formed. And also, 2 adjacent vertically in the figure
An N ⁺ type semiconductor layer 19A is formed in the surface region of the substrate 11 between the gate insulating films 12a and 12c at two locations, and similarly the gate insulating film 12 at two locations is formed.
In the surface area of the substrate 11 between b and 12d,
An N ⁺ type semiconductor layer 19B is formed. Furthermore, each gate insulating film 12a, 12b, 12c, 12d
In contrast, the N ⁺ type semiconductor layer 19A or 1
A continuous N ⁺ type semiconductor layer 19C is formed in the surface region of the substrate 11 on the side opposite to the side where the layer 9B is formed. Further, the third conductive layer 18A, 18
A fourth layer made of Al is placed on B with an insulating film 20 interposed therebetween.
Conductive layers 21A and 21B are formed, one of which is connected to the N + type semiconductor layer 19A through a contact hole 22A, and the other conductive layer 21B is connected to the N ⁺ type semiconductor layer 19A through a contact hole 22A. N ⁺
type semiconductor layer 19B through another contact hole 2B. and said N ⁺
The type semiconductor layer 19C is connected to a reference potential point, such as a ground potential point.

In addition, in FIG. 2a, the area surrounded by broken lines with the symbol ABCD indicates a memory cell for 1 bit of this semiconductor memory device, and as is clear from FIG. 2b, this memory cell is The second conductor layer 15 is a floating gate, the third conductor layer 18 is a control gate, and the first conductor layer 14 is an erase gate. , N ⁺ type semiconductor layer 1
It is composed of a MOS transistor with 9A as the drain and N ⁺ type semiconductor layer 1C as the source, and further looking at the 2 bits shown in Figure 2b, the control gate and erase gate are common, and the left and right gates are the same with respect to the erase gate. It consists of a pair of symmetrically configured MOS transistors. The control gate is provided on the semiconductor substrate 1 via an insulating film, and the floating gate and erase gate are arranged in parallel within the insulating film sandwiched between the control gate and the substrate 11. There is. Furthermore, since the erase gate is formed on the field insulating film 13, the overlapping portion of each floating gate and erase gate exists within the field region. Further, as shown in FIG. 2b, in the overlapping portion, the second conductor layer 15, ie, the floating gate, is located above the first conductor layer 14, ie, the erase gate. , the distance between the substrate 11 and the conductor layer 14 is shorter than the distance between the substrate 11 and the conductor layer 15.

FIG. 3 is an equivalent circuit diagram of the semiconductor memory device shown in FIG. 2 above. In the figure, 31 and 32 are digit lines made up of the fourth conductor layers 21A and 21B, and 33 and 34 are the first conductor layers 1.
4 is an erase line formed by being extended, and 35 and 36 are selection lines (row lines) formed by extending the third conductor layers 18A and 18B. Also M1
~M4 is a memory cell, and each memory cell has a control gate CG and a floating gate.
It consists of FG, erase gate EG, drain D and source S, the drains D of memory cells M1 and M2 are connected to one of the digit lines 31, the drains D of memory cells M3 and M4 are connected to the other digit line 32, and all The sources S of the memory cells are respectively connected to the ground potential point.

Next, the operation of the semiconductor memory device of the present invention will be explained using the equivalent circuit shown in FIG. 3 above. Now, paying attention to the memory cell M1 in FIG. 3, in the initial state, no electrons are injected into the floating gate FG of this memory cell M1, and its threshold voltage V _TH is in a low state.

When writing data to this memory cell M1, a high voltage of positive polarity, for example +20V, is applied to the selection line 35.
By applying a positive high voltage, for example, +20 volts, to the digit line 31, the voltage is connected from the source S to the drain D of the memory cell M1.
A flow of hot electrons occurs toward the floating gate FG, and these hot electrons are injected into the floating gate FG from between the source and drain, that is, from the channel region. This increases the threshold voltage V _TH of this memory cell M1. Note that during data writing, a high voltage pulse of, for example, +20 volts, a DC voltage of +5 volts or 0 volts may be applied to the erase line 33, or it may be left open.

Next, when reading data from this memory cell M1, the selection line 35 is selected and a high level signal (+5 volts) is applied to the control gate CG of the memory cell M1. When this high level signal is applied, if the threshold voltage V _TH is low,
This memory cell M1 is turned on, and a current flows from one digit line 31 through the memory cell M1 toward the ground potential point. On the other hand, if the threshold voltage V _TH is high when the high level signal is applied, this memory cell M1 is turned off and no current flows. At this time, if the state in which current flows through the memory cell M1 is set to a logic "1" level, and the state in which no current flows is set to a logic "0" level, this device can be used as a memory device. Furthermore, as mentioned above, the floating gate FG is surrounded by an insulating film and is insulated from other parts, so the electrons once injected here are not released during normal use. It cannot escape and therefore can be used as a data non-volatile storage device.

Further, when erasing data that has been written once, the selection line 35 and the digit line 31 are each set to 0 volts, and a high voltage, for example, a pulse voltage of +40 volts, is applied to the erase line 33. By applying such a voltage, the memory cell M1
floating gate FG and erase gate EG
A field emission occurs between the erase gate EG and the erase line 33, and the electrons that have been accumulated in the floating gate FG flow out through the erase gate EG and the erase line 33. As a result,
The threshold voltage V _TH of this memory cell M1 returns to a low state similar to the initial state.

In this way, in the semiconductor memory device of the above embodiment,
Since the erase gate is arranged in parallel to the floating gate of a normal double-gate type MOS transistor to form a memory cell for one bit, various effects such as those described below can be obtained.

One memory cell can be composed of one transistor, and data can be electrically erased. Therefore, electrically erasable EP
- It is possible to create a ROM with the same degree of integration as the ultraviolet erasable type. Furthermore, since inexpensive plastic can be used as the package, the cost is low.

Writing, erasing, and reading data can be performed using a single polarity power supply. In other words, for example, you only need a positive polarity power supply of +20 volts for writing, +40 volts for erasing, and +5 volts for reading, and if you obtain +20 volts and +40 volts from the +5 volt voltage with a booster circuit, the power supply You can also get away with one of the +5 volts. Therefore, data can be written, erased, and read while mounted on a printed wiring board or the like.

Since there is no transistor for bit selection, data can be erased simultaneously in units of words and units of all bits.

Since field emission is used to erase data, data can be erased in a short time.

Since only a three-layer polysilicon structure is formed and no other process is required, it can be manufactured using a normal silicon gate process.

Next, an example of a manufacturing method for manufacturing the semiconductor memory device according to the present invention shown in FIG. 2 is shown in FIG.
This will be explained using the pattern plan views shown in FIGS. First, Figure 4a and Figure 5a
As shown in FIG. 1, field insulating films 13 and 13' are formed by growing an insulating film to a thickness of 1 μm on the surface of a semiconductor substrate 11 made of P-type silicon by photolithography.
Further, P or As is diffused into the shaded area in FIG. 4a by implantation or diffusion to form an N-type semiconductor layer 19C'. After the completion of the above diffusion, the above field insulating film 1
After exposing the surface of the substrate 11 in areas other than the 3, 13' forming area, a layer of 1000 Å to
The gate insulating film 12 is formed by forming a relatively thin oxide film of 2000 Å. Next, polysilicon with a thickness of 6000 Å is grown on the entire substrate 11,
After doping this with P or As, a first conductive layer 14 is formed in the solid line area in FIG. 4b by photolithography. Here, the first conductive layer 1 is formed on the adjacent field insulating film 13'.
4 is not formed, but this may be formed if necessary. Next, after forming the first conductor layer, as shown in FIGS. 4c and 5c, an insulating film 16 with a thickness of 500 Å is grown by thermal oxidation, and then A polysilicon film with a thickness of 5000 Å was grown using the CVD method.
This is applied to a photoengraving method to form the second conductive layer 15a, 15b, 1 as a floating gate.
5c and 15d are formed. Here, in Figure 5c,
As is clear from the figure, only one end of the conductive layers 15a and 15b, which will serve as floating gates, extending over the field insulating film 13 is connected to the insulating film 16.
An example is shown in which at least a portion of the conductor layer 14 overlaps with the first conductor layer 14 via the conductor layer 14 . and conductor layer 15
The other ends of a and 15b do not overlap with the conductor layer 14. After forming the floating gate,
As shown in FIG. 4d and FIG. 5d, an insulating film 17 with a thickness of 1000 to 2000 Å is formed by thermal oxidation, polysilicon is deposited thereon, and then photolithography is applied to this. is applied to form the third conductor layers 18A, 18B which will become control gates, and at the same time, the second conductor layers 15a, 15b, 15 are formed.
c and 15d are formed by self-alignment. Next, P or
By diffusing As, N ⁺ type semiconductor layers 19A, 19B, 1
Forms 9C. Furthermore, Figures 4e and 5e
As shown in FIG.
A fourth conductor layer 21A, 21B is formed by continuously depositing an Al film and applying a photolithography method to this Al film.
and contact portions 22A, 22
This semiconductor memory device is completed by connecting each of the N ⁺ type semiconductor layers 19A and 19B with B.

6a to 6c show the configuration of a memory cell according to a second embodiment of the present invention, and FIG.
is a pattern plan view, and Fig. 6b is a -' of Fig. 6a.
A cross-sectional view of the structure along the line, Fig. 6c, is the same as that shown in Fig. 6a.
FIG.

In FIG. 6, 111 is a semiconductor substrate made of P-type silicon, and gate insulating films 112a to 112f are formed at regular intervals on the surface of this substrate 111.
They are arranged in an XY matrix. Further, on the surface of the substrate 111, gate insulating films 112a and 112d are formed at respective locations adjacent to each other in the vertical direction in the figure.
112b and 112e and 112c and 112f are paired, and field insulating films 113 and 113' are formed between the gate insulating film pairs. Further, a first conductive layer 114 made of polysilicon containing P or As is formed on the field insulating film 113 at one location. Further, on each of the gate insulating films 112a to 112f, second conductor layers 115a to 115a made of polysilicon are formed.
115f are formed separately from each other. The right end portions of the two second conductor layers 115b and 115e located on the left side with respect to the first conductor layer 114 in the figure are connected to the insulating film 1.
It overlaps with the left end portion of the first conductor layer 114 via the conductor layer 16 . In addition, the conductor layer 114
The left end portions of the two second conductor layers 115c and 115f located on the right side of the conductor layer 115 overlap the right end portion of the conductor layer 114 with the insulating film 116 interposed therebetween. . Furthermore, second conductor layers 115a and 11 adjacent in the left and right direction in the figure
5b, 115c, each of these conductive layers 115a, 1
A third conductor layer 118A made of polysilicon is set to have approximately the same width as 15b and 115c,
118B is formed, and similarly, a second conductor layer 115 adjacent in the left and right direction in the figure is formed.
d, 115e, and 115f, another third layer made of polysilicon and having a width set to be approximately the same as each of these conductive layers 115d, 115e, and 115f is placed through the insulating film 117 so as to cover this. A second conductor layer 118B is formed. Furthermore, an N ⁺ type semiconductor layer 119A is formed in the surface region of the substrate 111 between the two gate insulating films 112a and 112d that are adjacent to each other in the vertical direction in the figure.
Further, an N ⁺ type semiconductor layer 119B is formed in the surface region of the substrate 111 between the two gate insulating films 112b and 112e, and the gate insulating film 119B is similarly formed in the two gate insulating films 112b and 112e.
In the surface area of the substrate 111 between c and 112e,
An N ⁺ type semiconductor layer 119C is formed. Further, for each gate insulating film 112a to 112e,
The above N ⁺ type semiconductor layers 119A, 119B, 119
In the surface area of the substrate 11 on the side opposite to the C forming side,
A continuous N ⁺ type semiconductor layer 119D is formed. Further, the third conductive layer 118A, 11
8B, wiring layers 121A, 121B, 121C, 121D made of Al are disposed via an insulating film 120.
are formed, one of which is a wiring layer 121.
A and the N ⁺ type semiconductor layer 119A are connected through a contact hole 122A, and the wiring layer 121
B and the N ⁺ type semiconductor layer 119B are connected by a contact hole 122B, the wiring layer 121C and the first conductive layer 114 are connected by a contact hole 122C, and the wiring layer 12
1D and the N ⁺ type semiconductor layer 119C are connected through a contact hole 122D. The N ⁺ type semiconductor layer 119D is connected to a reference potential point, for example, a ground potential point.

In addition, in FIG. 6a, the area surrounded by a broken line with signal ABCD indicates a memory cell for one bit of this semiconductor memory device, and this memory cell flows through the second conductor layer 115. floating gate, third conductor layer 1
18 is a control gate (control gate), the first
The third conductive layer 114 is used as an erase gate, the N ⁺ type semiconductor layer 119B is used as a drain, and the ^N + type semiconductor layer 119B is used as a drain.
Furthermore, when looking at the two bits shown in FIG. 6b, the control gate and the erase gate are common, and a pair of MOS transistors having the type semiconductor layer 119D as a source are formed symmetrically with respect to the erase gate. MOS
Consists of transistors. The control gate is connected to the semiconductor substrate 1 through an insulating film.
The floating gate and erase gate are arranged in parallel in an insulating film sandwiched between the control gate and the substrate 111. Further, since the erase gate is formed on the field insulating film 113, the overlapping portion of each floating gate and erase gate exists within the field region. Further, as shown in FIG. 6b, in the overlapping portion, the second conductor layer 115, that is, the floating gate
The conductor layer 114 is located above the erase gate, and the distance between the substrate 111 and the conductor layer 114 is shorter than the distance between the substrate 111 and the conductor layer 15. Further, as is clear from FIG. 6a, the first conductor layer 114 is provided at only one location for a 4-bit memory cell, and each conductor layer 114 at one location provides one contact. The wiring layer 121C in the hole 122C
is connected to.

The equivalent circuit diagram of the semiconductor memory device shown in FIG. 6 is the same as that shown in FIG. 3, and its operation is also the same, so a description thereof will be omitted.

Further, in addition to the effects of the semiconductor memory device of the embodiment described above, the following effects can also be obtained.

Erase gate (first conductor layer) 11
Since the wiring layer 121C made of Al is used to form the erase line instead of using the polysilicon that constitutes 4, the thickness of the insulating film between the erase line and the substrate is can be made relatively thick, so even if a high voltage is applied to the erase line, leakage will not occur.

Since one contact hole connecting the erase gate and the wiring layer 121C needs to be provided for each four bits of the memory cell, the number of contacts per one bit is 1/4, and high integration is possible.

Since hot electron injection is used when writing data and field emission is used when erasing data, a relatively thick insulating film can be used around the floating gate, resulting in good non-volatile characteristics, that is, data retention characteristics.

Next, an example of a manufacturing method for manufacturing the semiconductor memory device according to the present invention shown in FIG. 6 is shown in FIG. 7a.
This will be explained using the pattern plan views shown in FIGS. First, Figure 7a and Figure 8a
As shown in FIG. 2, field insulating films 113 and 113' are formed by growing an insulating film to a thickness of 1 μm on the surface of a semiconductor substrate 111 made of P-type silicon by photolithography. Note that at this time, the field insulating film 11
A thin insulating film 123 is formed between 3 and 113'. Next, polysilicon is grown to a thickness of 6000 Å on the entire surface of the substrate 111, and after doping it with P or As, the field insulation is formed in the above one place as shown by the solid line in FIG. A first conductor layer 114 is formed on the film 113. Here, adjacent field insulating films 11
Although an example is shown in which the conductor layer 114 is not formed on the conductor layer 3', it may be formed if necessary. Next, after forming the first conductor layer 114,
As shown in FIGS. 7c and 8c, an oxide film with a thickness of 500 Å is grown by a thermal oxidation method to form the gate insulating films 112a to 112f and the insulating film 1.
16 is formed, and then polysilicon is grown to a thickness of 5000 Å using the CVD method, and then a second conductor layer 115a to 115f is formed as a floating gate by applying a photolithography method. form. As is clear from the figure, FIG. 8c shows a conductor layer 11 which becomes a floating gate.
An example has been shown in which only one end portion of each of the first conductor layer 114 extending over the field insulating film 113 at least partially overlaps with the first conductive layer 114 via the insulating film 116. and conductor layer 115b,
The other end of 115c does not overlap with conductor layer 114. After forming the floating gate, an insulating film 11 with a thickness of 1000 Å to 2000 Å is formed by thermal oxidation as shown in FIGS.
7 is formed, polysilicon is deposited thereon, and a photolithography method is applied to this to form a third conductor layer 118A, 118B which becomes a control gate.
At the same time as forming the second conductor layer 115a
~115f is formed by self-alignment. Next, P or
N ⁺ type semiconductor layer 11 that diffuses As and becomes a drain
9A, 119B, 119C and source
N ⁺ type semiconductor layers 119D are respectively formed. Furthermore, as shown in FIGS. 7e and 8e, the substrate 1
An insulating film 120 and an Al film are successively deposited over the entire surface of the substrate 11, and a photolithography method is applied to this Al film to form wiring layers 121A, 121B, 121C, and 121D. At this time, contact hole 1 is
22A, 122B, 122C, 122D are opened and contact holes 122A, 122B,
N ⁺ type semiconductor layer 119 by each of 122D
A, 119B, 119C and wiring layers 121A, 12
1B and 121D respectively, contact hole 1
This semiconductor memory device is completed by connecting the first conductive layer 114 and the wiring layer 121C with 22C.

FIG. 9 shows an embodiment of the present invention, in which an i.times.j bit semiconductor memory device is constructed using the semiconductor memory device shown in FIG. 2 or FIG. 6. In FIG. In the figure, M ₁₁ ,...M _j1 ,...M _1j ,...
M _ij is a memory cell of 1 bit each arranged in a matrix of j pieces in the column direction and i pieces in the row direction, and the drains of the memory cells arranged in the same column among these memory cells are as follows. It is commonly connected to each of the digit lines D-1 to D-j, and the source of each memory cell is grounded. Further, the control gates of memory cells arranged in the same row are commonly connected to row lines R ₁ to R _j , respectively. In the figure, 41 indicates that a column address is input, and when reading or writing data, one output terminal is selected according to the column address, and a high level signal, for example, +5 or +20 volts, is output from only that selected output terminal. , a column decoder that outputs a low level signal, e.g. 0 volts, from all unselected outputs. 42, when reading data or writing data when a row address is input, one output terminal is selected according to the row address, and a high level signal is output only from this selected output terminal, and all unselected output terminals are output. This is a row decoder that outputs low-level signals from the . Digit line D-1~D
-j are connected to output terminals CD ₁ -CD _j of the column decoder 41 via MOS transistors T _c1 - T _cj , and erase lines E-1 - E-j are connected via resistors R _E - ₁ - _{R E} - _j . The erase lines E-1 to E-j are connected to the terminal E _r for erasing data, and the erase lines E-1 to E-j are connected to the MOS transistors T _RE1 to _{T REj.}
is grounded through the output terminal CD ₁ of the column decoder 41
~CD _j is the transistor through the inverter I ₁ ~ _{I j}
Connected to the gates of T _RE1 to T _REj , the transistors
T _c1 to T _cj are commonly connected to terminal CV _prpg . Further, the row lines R ₁ to _{R i} are connected to the output terminals RD ₁ to _{RD i} of the decoder 42 via MOS transistors _TR1 to T _Ri , and the gates of the transistors T _R1 to T _Ri are connected to the terminal CV _prpg.
are commonly connected. Also, the row lines R ₁ to R _j are MOS
The transistors T _RP1 to T _RPi are connected to one end, and the other ends of the transistors T _RP1 to _{T RPi} are grounded via the MOS transistors Q ₁ to _{Q i} , and the resistors RR ₁ to
Connected to terminal E _r through RR _i , the transistor
The gates of T _RP1 to T _RPi are commonly connected to a terminal _prpg which has a signal inversion relationship with the terminal CV _prpg , and the gates of transistors Q ₁ to _{Q i} are connected to terminals RD ₁ to _{RD i} . A data erase voltage, for example, +40V, is applied to the terminal E _r when data is erased.

As described above, the operation of a semiconductor memory device in which data can be written by selecting each bit in a memory cell, and data can be erased by selecting each bit in a memory cell will be explained. First, during writing, the terminal CV _prpg is at a high level and the terminal CV _prpg is at a low level. Therefore, the outputs of the row decoder 42 and the column decoder 41 are such that the transistors _TR1 to T _Ri are turned on (conducting), the transistors T _c1 to T cj are turned on, and the transistors T _RP1 to T _cj are turned on, respectively.
T _RPi turns off (non-conducting) and transistor T _RE1 ~
Since T _REi is turned off, the output of the row decoder 42 enters the row lines R ₁ to R _i and the output of the column decoder 41 enters the digit lines D-1 to D-j. Therefore, for example, when a memory cell M _ij is selected, the row line R _i goes to a high level, the digit line D-j goes to a high level, and when the program voltage is applied to the memory cell M _ij , electrons are transferred to the floating gate of this M _ij . is injected,
The threshold voltage increases and writing is completed.

Next, a case will be described in which data is erased only from a memory cell, for example, M _ij . When erasing, the terminal CV _prpg
becomes low level, and terminal CV _prpg becomes high level. Therefore, the transistors T _R1 -T _Ri are turned off, and the output of the row decoder 42 does not directly enter the row lines R ₁ -R _i . Also, transistors T _RP1 to T _RPi are turned on,
The high voltage from erase terminal E _r is decoded by row decoder 42 . That is, since memory cell M _ij has been selected, the output of the row decoder 42 is
Among RD ₁ to _{RD i,} only RD _i is at a high level, and the other RD ₁ to RD _i - _j are at a low level. Therefore, among the transistors Q ₁ to Q _i , only Q _i is turned on, and the row line
Among the outputs applied to R ₁ to _{R i} , only R _i is at a low level, that is, 0 volts, and the outputs from R ₁ to _{R i} - _j are at a high level, that is, the voltage of the erase terminal E _r is output. Here, it is desirable that the high level of the terminal CV _prpg is higher than the voltage level of the erase terminal E _r (for example, +45 V). That is, during erasing, the row lines are at low level and the unselected row lines are at high level.

Next, the operation on the column decoder 41 side will be described. As mentioned above, since the terminal CV _prpg is at a low level, the transistors T _c1 to T _cj are turned off, and the output from the column decoder 41 is passed through the inverters I ₁ to I _j to the transistor T _RE1.
~T Enter the _REj gate. Here memory cell M _j
is selected, the output of the column decoder 41 is
Only CD _j is at high level, and the high level of terminal E _r is applied only to erase line Ej. Therefore, a high level voltage is applied to the erase gates of memory cells M _1j to M _ij . However, since a high level voltage is applied to the control gates R ₁ to _{R i-1} of the memory cells M _1j to M _(i-1)j , the floating gate of the memory cell is connected to the floating gate and control gate. By increasing the capacitance, the potential of the floating gate becomes higher. On the other hand, since the control gate potential of the memory cell M _ij is at a low level, that is, 0 volts, the floating gate potential is close to 0 volts even if the coupling capacitance between the control gate and the floating gate is large, and the erase line E-j A high level voltage applied to the memory cell M ij is directly applied between the floating gate and the erase gate E-j, and only the electrons of the memory cell M _ij are extracted from the floating gate by field emission.

FIG. 10 shows another embodiment of the present invention, in which parts corresponding to those in the previous embodiment are given the same reference numerals, explanation thereof is omitted, and only the characteristic points will be extracted and explained.
In this embodiment, when reading or writing, the terminal
CV _prpg is at high level, terminal _prpg is at low level, and during erasing, CV _prpg is at low level and _prpg is at high level. On the other hand, the E _r terminal is a MOS transistor
The output terminals CD ₁ -CD _j of the decoder 41 are connected to the erase lines E-1 - E-j via T E1 - T Ej, and the output terminals CD ₁ - CD _j of the decoder 41 are connected to the gates of the transistors T _E1 - T _Ej via booster circuits 51 ₁ - 51 _j . connected to. The MOS transistor Q _R whose gate is connected to the terminal _prpg has one end grounded,
The other end is connected to one end of transistors Q ₁ to Q _i .

FIG. 11 specifically shows one of the booster circuits 51 ₁ to 51 _j shown in FIG. 10, and this circuit is a booster circuit using a bootstrap. In this circuit, if, for example, +5V is obtained at the input IN,
+45V is output to the output Out. Therefore, when erasing data, for example, when column decoder output terminal CD _j in FIG. 10 is selected, the gate input of transistor T _Ej becomes +45V, and +40V of erase terminal E _r becomes erase line E-
It is output as is only to j. On the other hand, when erasing the data, transistor Q _R is on and transistors T _R1 to T _Ri are off. For example, if only row decoder terminal R _i is selected, only Q _i of transistors Q ₁ to Q _i is selected. is on and the others are off, so the row line R _i has a low level, or 0 volts, through the transistors Q _R and Q _i , and the other row lines have a high level, or +40 V, from the erase terminal E _r . In this case, Data in the memory cell M _ij is erased.

FIG. 12 shows still another embodiment of the present invention, in which parts corresponding to those in the previous embodiment are given the same reference numerals, explanations thereof are omitted, and only characteristic points will be extracted and explained. In this embodiment, when reading or writing,
The terminal CV _prpg is at a high level and the terminal _prpg is at a low level, and during erasing, CV _prpg is at a low level and _prpg is at a high level. It is desirable that the high level of the terminal _prpg be higher than the high level of the terminal E _r . 61 ₁ to 6 in the figure
1 _i is a booster circuit using a bootstrap (boosting to prevent the voltage drop of transistors Q ₁₂ and Q ₁₃ ), and Q ₂₁ to _{Q 2i} are booster circuits 61 ₁ to 61 that are turned off during reading to increase the data read speed. This is a transistor that separates _i . In this circuit, when erasing, for example, when memory cell M _ij is selected, transistor Q ₁₄ of booster circuits 61 ₁ to 61 _i
Since only the booster circuit 61 _i is turned on,
Only the row line R _i becomes low level through the transistors Q ₁₄ and Q _2i , and high level voltage is obtained from the terminal E _r on the other row lines R ₁ to _{R ij} .

In each of the memory cells mentioned above, if the high-level voltage applied to the control gate, for example +40V, has a large coupling capacitance with the floating gate, the floating gate becomes +30V, and the potential difference between the erase gate and the floating gate is 10V, and the floating gate becomes Electrons will not be field-emitted from the gate.

Now, the capacitance between the floating gate and the erase gate is C _FE ,
C FC is the capacitance between the floating gate and the control gate, and C _FC is the capacitance between the floating gate and the source, substrate, and drain.
C _FB , the floating gate potential is V _F , the erase gate potential is V _E , the control gate potential is V _C , and the substrate potential is V _B
(V _B =0 volt). At this time, if the amount of charge stored in the floating gate in advance is −Q _F , then
This −Q _F is given by the following equation.

−Q _F =C _FB (+V _F )+C _FE (V _F −V _E )+C _FC (V _F −
V _C ) = (C _FB + C _FE + C _FC ) V _F −C _FE V _E −C _FC V _C …(1) The floating gate potential is determined from the above formula (1) as follows.

V _F = −Q _F +C _FE V _E +C _FC V _C /C _FB +C _FE +C _FC ……(2) Next, the potential difference between the floating gate and the erase gate.
Calculating V _EF is as follows.

V _EF = V _E −V _F = (C _FB + C _FC ) V _E −Q _F −C _FC V _C /C _T ……(3) However, C _T = C _FB + C _FE + C _FC Set V _C to 0 volts to erase the voltage. At this time, the potential difference V _EF1 between the floating gate and the erase gate is given by the following equation.

V _EF1 = V _E − V _F = (C _FB + C _FC ) V _E − Q _F /C _T …(4) Also, in order to prevent erasure from being performed on other memory cells, V _C is set to V _E . The potential difference V _EF2 between the floating gate and the erase gate at this time is given by the following equation.

V _EF2 = V _E −V _F = C _FB V _E −Q _F /C _T ……(5) Next, find the ratio of the potential difference between the above equations (4) and (5), and it will be as follows. .

V _EF1 /V _EF2 = (C _FB + C _FC ) V _E −Q _F /C _FB V _E −Q _F …(6) If we assume that |C _FB V _E |＞Q _F , the above equation (6) becomes It can be rewritten as the following formula.

V _EF1 /V _EF2 ≒ C _FB + C _FC / C _FB = 1 + C _FC / C _FB ... (7) Here, memory cells can be efficiently selected bit by bit, and when a voltage is applied to the control gate and an erase input is made, In order to prevent data in memory cells that are not selected from being erased, the above formula (7) must be at least 3
It needs to be more than doubled. As a result, C _FC ≧2 _FB may be satisfied.

Furthermore, the amount of charge of electrons injected and stored in the floating gate of the memory cell can be quantitatively detected using the terminal E _r for erasing data. now,
The amount of accumulated charge on the floating gate after writing data is −
If Q _F , then the threshold voltage of the memory cell V _TH
The change in ΔV _TH becomes Q _F /C _FC . On the other hand, when a certain potential V _E is applied to the terminal E _r , ΔV _TH is expressed by the following equation.

ΔV _TH = Q _F −C _FE V _E /C _FC ……(8) Apparently, the amount of charge −Q _F accumulated in the floating gate can be decreased by V _E or conversely increased. Therefore, by changing V _E , the value of −Q _F can be detected quantitatively.

Next, conditions for detecting the above value of -Q _F without erasing data are determined. First, the following equation is found from equation (2) above.

0=1/C _T (C _FE ∂V _E +C _FC ∂V _C ) ...(9) Therefore, ∂V _E /∂V _C = −C _FC /C _FE ......(10) and C If _FC /C _FE ≦5, data will not be erased. As a result, C _FC ≦5C _FE may be satisfied.
Furthermore, by combining the above conditions and the conditions for erasing data, the following conditions can be obtained.

5C _FE ≧C _FE ≧2C _FB (11) Note that the present invention is not limited to each embodiment, and various applications are possible. For example, in FIG. 2 or FIG. 6, the second conductor layer 15
The case has been described in which each left end portion or only each left end portion of the conductor layer 115 overlaps at least a part of the first conductor layer 14 or 114; Both ends may overlap the conductor layer 14 or 114.

As described above, according to the present invention, it is possible to provide a semiconductor memory device which eliminates the above-mentioned conventional problems and has advantages such as being able to erase data well.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of one memory cell portion of a conventional E ² P-ROM, FIGS. 2 a to d show the configuration of a memory cell according to an embodiment of the present invention, and FIG. 2b is a structural cross-sectional view taken along line -' in figure a, Figure 2c is a structural cross-sectional view taken along line -' in figure a, and figure 2d is a structural cross-sectional view taken along line -' in figure a. FIG. 3 is an equivalent circuit diagram of the device shown in FIG. 2, and FIGS. This is for explaining an example of the method, and FIGS. 4a to 4e are pattern plan views, and FIGS. 5a to 5e are pattern plan views.
Cross-sectional views taken along lines -' of Figures 6a to 6c.
6 shows the structure of a memory cell according to an embodiment of the present invention, FIG. 6a is a pattern plan view, FIG.
Figure c is a cross-sectional view of the structure taken along line -' in figure a, and Figures 7a to 8e and 8a to 8e each illustrate an example of a manufacturing method for manufacturing the device shown in Figure 6 above. Figures 7a to 8e are pattern plan views, and Figures 8a to 8e are pattern plan views.
Figures a to e along line -', No. 9
10 is a circuit diagram of another embodiment of the present invention, FIG. 11 is a circuit diagram showing a part of the same circuit, and FIG. 12 is a circuit diagram of an embodiment of the invention. FIG. 7 is a circuit configuration diagram of still another embodiment of the present invention. 11,111... Semiconductor substrate, 12,112... Gate insulating film, 13,113... Field insulating film,
14,114...First conductor layer (erase gate), 15,115...Second conductor layer (floating gate), 16,116,17,1
17, 20, 120, 123...Insulating film, 18, 1
18...Third conductor layer (control gate), 19,119...N ⁺ type semiconductor layer, 21...Fourth layer
Layer conductor layer, 121...wiring layer, 22, 122
...conduct hole, 31, 32... digit line, 33, 34... erasure line, 35, 36... selection line,
M1, M2, M3, M4...Memory cell, CG...
Control gate (control gate), FG...floating gate (floating gate), EG...erase gate (erase gate), D...drain, S...source,
41... Column decoder, 42... Column decoder, R ₁ to R _i
... Row line, D-1 to D-j... Digit line, E-1
~E-j...Erasure line.

Claims (1)

[Claims] 1. A control gate provided on a semiconductor substrate via an insulating film, an erase gate provided in the insulating film sandwiched between the control gate and the substrate, and an erase gate provided in the insulating film. A memory cell comprising a floating gate disposed in parallel with the erase gate and whose end portion overlaps at least a portion of the erase gate via an insulating film, and a source and a drain, the memory cell comprising: When the potential of the control gate is set to a high level and the potential of the erase gate is set to a high level, electrons cannot be extracted from the floating gate by field emission, and the potential of the control gate is set to a low level and the potential of the erase gate is set to a high level. When set to a high level, electrons can be extracted from the floating gate by field emission, and by setting the potential of the control gate to a high level and changing the potential of the erase gate, 1. A semiconductor memory device configured to quantitatively detect the amount of charge accumulated in a semiconductor memory device. 2. The memory cell is characterized in that it has a relationship of 5C _FE ≧C _FC , where C _FE is the capacitance between the floating gate and the erase gate, and C _FC is the capacitance between the floating gate and the control gate. A semiconductor memory device according to claim 1. 3 In the memory cell, the capacitance between the floating gate and the erase gate is _CFE , the capacitance between the floating gate and the control gate is _CFC , and the capacitance between the floating gate and the source, substrate, and drain is CFE. 2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device has a relationship of 5C _FE ≧C _FC ≧2C _FB when C _FB .