JPH0218504B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a processor backup system for backing up when a program runs out of control in a processor device operated by a program.

Prior Art and Problems In a system using a processor that operates according to a program, the program may run out of control due to noise or other causes while the program is running. As a backup method when a program runs out of control, a timer counter (watchdog timer) configured by hardware is provided, and the counter is cleared at fixed intervals by the program. If the program stops running, it is assumed that the program has gone out of control, and a hardware interrupt is issued to the processor by a timer count over, so that the program is restarted from the initial stage. Conventionally, if this occurs frequently, a system is used in which an alarm is issued by software and the system is stopped.

However, with such conventional backup methods, if there is a hardware failure that makes it impossible to run the program, the timer counter will be cleared and the initial start will be repeated, and an alarm will be issued even if the device is completely abnormal. This caused the problem that monitoring of the equipment was no longer possible.

Purpose of the Invention The present invention aims to solve the problems of the prior art, and its purpose is to provide a timer counter that counts up at a constant speed in a system that includes a processor that operates according to a program. , the program clears the counter at fixed time intervals, initializes the program when the timer counts over, and furthermore, if such restarts occur frequently, the software issues an alarm. Another object of the present invention is to provide a processor backup method that can issue an alarm even when a program cannot run, in a method for stopping the system.

Embodiment of the Invention The figure shows the configuration of an embodiment of the processor backup system of the present invention. In the figure, 1 is a processor, 2 is a timer counter provided in the processor 1, and 3 is a backup circuit according to the method of the present invention. In the backup circuit 3, 11 is a low-pass filter and a buffer;
12 is an AND gate, 13 is a counter, 14 is a timer, 15 is an AND gate, 16 is an inverter,
17 is a NAND gate, 18 is an OR gate, and 19 is a manual reset switch.

The processor 1 clears the timer counter 2 at regular intervals according to a program. The timer counter 2 is always incremented by a clock having a constant cycle, and when the program runs out of control and is not cleared by the processor 1 and times out, it generates a runaway alarm signal. The alarm signal is input to the backup circuit 3, noise removed and amplified by a low-pass filter and buffer 11, and then input to the up-count terminal UC of the counter 13 via the gate 12. The counter 13 is usually down-counted by inputting a signal generated at regular intervals from the timer 14 to its down-count terminal DC, and unless the runaway alarm signal generated from the timer counter 2 occurs frequently, The count value has become 0.

When a runaway condition occurs, the alarm signal causes the counter 13 to count up, but the count-over signal is not generated until a specific count value x is reached.Therefore, the alarm signal is sent out as the clear signal CLR via the NAND gate 17, as shown in the figure. It is given to processor 1 via a processor bus that is not processed. The processor 1 clears the timer counter 2 using the clear signal CLR, temporarily turns off the alarm signal, and initializes the software.

Now that runaway situations are occurring frequently,
As the up count of the timer 13 due to the alarm signal exceeds the down count due to the timer signal, the count value of the timer 13 gradually increases. When the count value of the timer 13 reaches the value x, a count over signal is generated from the count over terminal CO, which closes the gate 17 and no longer outputs the clear signal CLR. Therefore, the timer counter 2 is not cleared and remains at the initial state. It doesn't start either. Therefore, the alarm signal continues to be output, so that the runaway state of the program can be continuously output to the outside.

In the figure, the manual switch 19 is used to arbitrarily clear the clear terminal CL of the counter 13 by grounding it, thereby setting the initial state of the counter 13. Further, the AND gate 12 is provided to continue generating the count-over signal by closing when the counter 13 reaches a specific value x. The AND gate 15 closes when the count over signal of the counter 13 is generated, prevents the counter 13 from down-counting, continues to generate the count over signal, and opens only when the count value of the counter 13 is 0 or more. The function is to prevent 13 from being counted down to 0 or less.

Effects of the Invention As explained above, the processor backup method of the present invention includes a timer counter that counts at a constant speed and is cleared at regular intervals according to a program, and when the timer counter times out, In a processor device that performs the initial start of a program, when a timer counter timeout occurs more than a certain number of times at a time rate greater than a certain time, this is detected and an output is generated. Since the initial start is stopped, it is possible to issue an alarm even in the event of a failure that prevents the program from running, making it possible to reliably know if there is an abnormality in the device, as well as to stop the system and prevent the program from running out of control. This makes it possible to prevent the effects of

[Brief explanation of drawings]

The figure is a block diagram showing the configuration of an embodiment of the processor backup system of the present invention. 1...Processor, 2...Timer counter, 3
... Backup circuit, 11 ... Low pass filter and buffer, 12 ... AND gate, 13
... Counter, 14 ... Timer, 15 ... AND gate, 16 ... Inverter, 17 ... NAND gate, 18 ... OR gate, 19 ... Manual reset switch.

Claims (1)

[Claims] 1. In a processor device that is equipped with a timer counter that counts at a constant speed and is cleared at regular intervals by a program, and that initializes the program when the timer counter times out, The present invention is characterized by comprising a timer means for detecting this and generating an output when it occurs at a rate of a certain number of times or more, and in response to generation of the output from the timer means, an alarm is issued and the initial start of the program is stopped. Processor backup method.