JPH0218622B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a signal input device for inputting the states of a plurality of distributed switches to a central processing unit via a transmission path.

Conventionally, there has been a device of this type as shown in FIG. The contact signals representing the on or off state of the switches 1a, 1b, 1c (generally there are a large number of switches, but to simplify the explanation, a case of three is shown here) are transmitted by cables 2a, 2b, 2c. is input to station 3 via. station 3
In this case, the level conversion circuit 4 converts the logic level of the input contact signal into, for example, a logic level of a normal integrated circuit element.
It is converted to 5V and supplied to the controller 5.
The controller 5 sequentially sends the output signal of the level conversion circuit 4, that is, the contact signal, to the bus 6a in response to an access request input from the central processing unit 6 via the bus 6a, which is a transmission path. The contact signal sent to 6a is read, and a predetermined process processing program is executed using this as data.

However, according to the configuration of such a conventional device,
When there are a large number of contact signals, the amount of cables required to transmit them becomes enormous, and the cost of the cables and the cost of wiring them become enormous.

In order to solve this problem, a conventional device as shown in FIG. 2 has been developed. In this case, switch 1
A station 8 is provided near a, 1b, 1c,
This includes a level conversion circuit 8a for converting the logic level of the contact signal, and a controller 8b for converting the output signal of the level conversion circuit 8a into a serial signal format and transmitting the serial signal format to the cable 8a. A station 9 is connected to the other end of the cable 8C, which includes a controller 9a that receives signals from the controller 8b via the cable 8C, and a controller 9a that receives signals from the controller 8b via the cable 8C.
A two-port memory 9b is provided to sequentially write the signals received at point a. The data in the memory 9b is sequentially read out by the controller 9a in response to an access request from the central processing unit 6, and is transferred to the central processing unit 6 via the bus 6a.

According to such a configuration, the switches 1a, 1
Cables 2a, 2b, 2c connected to b, 1c
Since the length of the cable is shortened and the contact signals are time-division multiplexed and transmitted between station 8 and station 9, the amount of cable is reduced. However, since the cable 8c connecting stations 8 and 9 is often laid in places with poor electrical environment conditions, as the transmission signal increases in multiplicity and speed, noise increases. The impact will be greater.

This invention was made in order to eliminate the drawbacks of the conventional ones as described above, and it provides a signal input that is not affected by electrical noise, can increase reliability, and can reduce cable costs. The purpose is to provide equipment.

The signal input device according to the present invention includes an optical transceiver that is provided corresponding to each group of switches and that sends out an output pulse that corresponds to the on or off state of each switch depending on the presence or absence of an optical signal in response to an input pulse. , consisting of an optical fiber that guides these input pulses and output pulses, and a transmission line that connects the optical transceivers in common, and an optical fiber that is connected to one end of this transmission line and sends the input pulses to the transmission line and outputs them from the transmission line. and a transmission device that receives and stores the pulses and transmits data of the stored output pulses in response to an access request signal from the central processing unit.

The length of the transmission path connecting each optical transceiver is adjusted, for example, so that the receiving end of the transmission device sequentially receives output pulses sent from each receiver at predetermined time intervals.

The transmission device is configured to sequentially sample and input the presence or absence of output pulses received via the transmission path at predetermined time intervals and to store the data.

An embodiment of the present invention will be described below with reference to the drawings. In FIG. 3, parts with the same reference numerals as in FIGS. 1 and 2 indicate the same or equivalent parts. Optical transmission section 10
For example, it has the configuration described in Japanese Patent Application Laid-Open No. 56-149841, and has the function of multiplexing optical signals introduced from each port or demultiplexing optical signals into these, and mutually connects optical fibers. Coupler 12, 13, 14, 15 connected in series via bus 11 consisting of
and are branch-connected to couplers 13, 14, and 15 via bus 11, each receiving a pulse of an optical signal of wavelength W1, and depending on the on or off state of each group (16 switches) not shown. It has reflective or non-reflective optical transceivers 16, 17, and 18. Katsupura 12 is a bus 12 made of optical fiber.
It is connected to the controller 9a of the station 9 through the terminals a and 12b.

Each switch of each optical transceiver 16, 17, 18 has a propagation time difference τ ₁ , τ ₂ ,...τ ₁₆ with respect to the bus 11.
Each optical transceiver 1 is connected with a distance of
The bus 11 between 6, 17, and 18 has a propagation time difference T ₁ ,
It has a distance of T ₂ .

FIG. 4 is a timing diagram showing the operation of the optical transmission section 10. When the controller 9a sends out a pulse as shown in FIG. 4a to the bus 12a and all switches are on, the above configuration allows the controller 9b to receive a time difference τ as shown in FIG. 4b via the bus 12b. ₁ , τ ₂ ... τ ₁₆ (τ ₁ = τ ₂ ... = τ ₃₂ ) is returned from the optical transceiver 16, and after time ₁ , a pulse train with time differences τ ₁₇ , τ ₁₈ ... τ ₃₂ is sent back to the optical transceiver 16. It will be returned from 17. Furthermore, the pulse train from the optical transceiver 18 continues after time _T2 .

FIG. 5 is a block diagram showing the configuration of the controller 9a shown in FIG. 3. Since the oscillation circuit 19 supplies a clock signal to the hexadecimal counter 20,
The clock signal frequency-divided to 1/16 by the counter 20 is supplied to a 20-decimal counter 21. The count result of the counter 21 is supplied to the decoder 22 at 5:20 and decoded. The decoder 22 has signals T0 to T19 as decode outputs, and signals T1 to T19.
T16 is supplied to the gate circuit 23. The gate circuit 23 consists of an AND gate with 2 inputs and 16 circuits, and receives the output pulse of the bus 12b and the signal T received via the photoelectric converter 24 and the shaping rotation 25, respectively.
1 to T16, and the result is supplied to the memory 26 as write data.

The memory 26 has two ports (the number of bits in the width direction of the memory) and is cleared by the signal T0, and the signals T1 to T16 sequentially set each bit to "1" and "0" to indicate the presence or absence of a pulse on the bus 12a. Write in response to. The data in the memory 26 is transferred to the memory 9b depending on the timing of the signals T17 and T18.
will be forwarded to. Signal T19 is a hexadecimal counter 41
is input, and this is counted up. The 4-bit output representing the count result of the counter 41 becomes the write address of the memory 9b, and is also supplied to the detection circuit 27 for detecting all zeros. The output signal of the detection circuit 27 is sent to the counter 26
It becomes high when all zeros of the output are detected, and its rising edge is detected by the differentiating circuit 28,
It is output as a differential pulse. The differential pulse of the differentiating circuit 28 is converted into an optical signal by a photoelectric converter 29, and is supplied to the bus 12a as an output pulse.

As is clear from such a configuration, the signal T
0, bus 12b during the period when T17 to T19 are high.
In order to avoid inputting output pulses representative of the state of each switch via the bus 11, the length of the bus 11 is adjusted here so that the time T ₁ is equal to 4τ ₁ .

The output of the counter 20 is input to a 4:16 decoder 30 and decoded, and its 8th decoded output is input to an AND gate 31 and outputs a signal T.
18 and the AND are taken. The output of the AND gate 31 becomes a write pulse for the memory 9b. This decode output is appropriately selected to correspond to the point in time when the circuit is stabilized.

On the other hand, in order to synchronize with the central processing unit 6, the signals T17 and T18 are supplied to the inverted logic input of the AND gate 33 via the OR gate 32, and the ready signal sent from the central processing unit 6 and the The sent address signal is sent to the station 9.
An AND is performed with the address signal indicating that the address matches the address. The output of AND gate 33 is applied to the set input of flip-flop 34, and the ready signal is applied via inverter 36 to the reset input of flip-flop 34, which outputs the set output of flip-flop 34 representing the status of station 9. is sent to the central processing unit 6 via the delay circuit 37 as a response signal.

As described above, according to the present invention, the switch status signal is converted into an optical signal and then transmitted via a transmission line made of optical fiber, so that it is not affected by electrical noise during the transmission process. Therefore, the problem of insulation between devices can be easily solved, and therefore a highly reliable device can be obtained, and cable costs can also be reduced. Moreover, in addition to adjusting the transmission path length, there is also a first memory that stores the switch status signal taken in at each sampling timing, and the data in this first memory is stored in response to requests from the central processing unit. Since it is configured to include a second memory that outputs data to the central processing unit and a transfer control circuit, it is possible to reduce the size of the cable and to suppress an increase in the amount of hardware.

[Brief explanation of drawings]

1 and 2 are block diagrams of a conventional signal input device, FIG. 3 is a block diagram of a signal input device according to an embodiment of the present invention, and FIG. 4 explains the operation of the signal input device of FIG. 3. FIG. 5 is a block diagram showing details of the controller of FIG. 3. 3, 8, 9...Station, 5, 8b, 9a
...Controller, 6...Central processing unit, 9b...
...Memory, 10...Optical transmission section, 11, 12a, 1
2b...Bus, 12-15...Katsupura, 16,
17, 18... Optical transceiver. Note that the same reference numerals in the figures indicate the same parts.

Claims (1)

[Claims] 1. In a signal input device that inputs status signals of a plurality of distributed switches to a central processing unit, the signal input device is provided corresponding to a group of switches, and is configured to input the ON or OFF status of each of the switches in response to an input pulse. an optical transceiver that sends out output pulses corresponding to the presence or absence of an optical signal; a transmission line that commonly connects the optical transceiver and includes an optical fiber that guides the input pulse and the output pulse;
The output is connected to one end of the transmission line, transmits the input pulse to the transmission line, receives and stores the output pulse from the transmission line, and stores the output pulse in response to an access request signal from the central processing unit. The length of the transmission path connecting each of the above-mentioned optical transceivers is such that the output pulses sent from each transceiver are sequentially received at a predetermined time interval at the receiving end of the transmission device. The optical transceiver is configured such that there is a predetermined distance difference between the elements corresponding to each switch and the transmission path, and the transmission device receives signals via the transmission path. a first memory that sequentially samples and stores the presence or absence of an output pulse at predetermined time intervals; a transmitting circuit that sends an input pulse to the transmission path in synchronization with the timing of the sampling input; a second memory that stores the data of the first memory;
and a transfer control circuit that transfers data in the second memory to the central processing unit in response to an access request signal from the central processing unit connected to the second memory. Device.