JPH0218782B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a clock synchronization circuit for a modem used in digital communications.

1. Configuration of conventional example and its problems FIG. 1 shows an example of a digital communication receiver using a conventional clock synchronization circuit.

The operation of this conventional example will be explained below with reference to FIG. A digital modulated signal inputted from one antenna is converted into a baseband signal by the radio receiver 2 and sent to the signal processing section 10 and the differentiating circuit 3. A differentiating circuit 3 differentiates the waveform change point of the received baseband signal, and a phase comparator circuit 4 compares the phase of the received clock signal with the received recovered clock signal outputted from the frequency dividing circuit 9 as a received clock component. When the reproduced clock signal lags behind the received clock component in phase, the up-down counter 5 is operated in up-count mode. When the up-down counter 5 counts up to a certain value, the variable frequency divider circuit 8, which normally operates as a 1/4 frequency divider, divides the frequency by 1/3 to advance the phase of the reproduced clock. The reproduced clock is obtained by dividing the output of the variable frequency divider circuit 8 into quarters by a frequency divider circuit 9. The input clock of the variable frequency divider circuit 8 is input to the oscillation frequency divider circuit 7.
It is obtained by dividing the oscillation frequency 6 of the crystal. Note that the clock frequency of the oscillation frequency divider circuit 7 is set to 16 times that of the transmission clock.

Also, as a result of the determination by the phase comparator circuit 3, if the reproduced clock signal leads the received clock component in phase,
The up-down counter 5 operates in a down-count mode, and when the up-down counter 5 counts down to a certain value, the variable frequency divider circuit 8 divides the frequency by 1/5 and feedback is applied so that the phase of the reproduced clock is delayed. . In the signal processing unit 10, the baseband signal output from the wireless receiver 2 is processed by a frequency dividing circuit 9.
The received data is verified and decoded using the output reproduced clock signal, converted into an audio signal by D/A conversion, and outputted to the speaker 11.

The rise characteristics of the digital reception receiver explained above are based on the digital
Determined by the PLL response characteristics. However, in order to speed up the synchronization of the PLL circuit,
It is necessary to reduce the count setting of the up-down counter 5 and perform a large number of feedbacks to the variable frequency divider circuit 8. The phase jitter of the clock increases, deteriorating the data reception characteristics under normal reception conditions.

Therefore, in the conventional circuit, in order to ensure the data reception characteristics up to a certain level, there was a problem in that the response of the digital PLL had to be slowed down at the expense of the reception rise characteristics.

Another method for accelerating clock phase synchronization is to input the initial phase of the counter when the input signal is not within the phase synchronization range of the regenerated clock, as shown in Japanese Patent Application Laid-Open No. 162526/1982. It is also known to speed up phase synchronization by forcibly presetting to match the signal.

However, although this method is effective as a phase synchronization method for frequency synthesizers and the like where it is guaranteed that the input signal S/N is always good, it is
When applied to a clock synchronized circuit where the S/N ratio of the input signal is not necessarily good, the initial phase of the counter changes each time it is included in the phase noise of the input signal. There is a problem in that it increases phase jitter and lowers the data reception rate.

OBJECTS OF THE INVENTION It is an object of the present invention to provide a clock synchronization circuit which eliminates the problems of the prior art described above, speeds up the reception rise time, and does not cause deterioration of reception characteristics in normal reception conditions. be.

Structure of the Invention In order to achieve the above object, the present invention adjusts the operation count of the up-down counter of the digital PLL circuit depending on whether or not clock synchronization is established.
By changing this, it is possible to obtain the effect of improving the reception rise characteristic and the normal reception characteristic.

DESCRIPTION OF EMBODIMENTS The configuration of an embodiment of the present invention will be described below with reference to the drawings. FIG. 2 shows the configuration of parts related to synchronization, 12 is an input terminal for receiving baseband signals, 13 is a differentiation circuit, 14 is a phase comparison circuit, 1
5 is a counter control circuit, 16 is a first up-down counter, 17 is a variable frequency divider circuit, 18 is a frequency divider circuit, 19 is an oscillation circuit, 20 is a crystal oscillator, 21 is a window circuit, 22 is a gate circuit, 23 is the second up-down counter, and 24 is the output terminal of the regenerated clock.

Next, the operation will be explained. The baseband signal received from the input terminal 12 has a waveform change timing extracted by a differentiating circuit 13. This receive clock component is regenerated by a digital PLL circuit consisting of a phase comparator circuit 14, a first up-down counter 16, a variable frequency divider circuit 17, a frequency divider circuit 18, an oscillator circuit 19, and a crystal oscillator 20. ing.

Since the operation of the digital PLL circuit has been described in the explanation of FIG. 1, the explanation will be omitted here.

The window circuit 21, the gate circuit 22, and the second up-down counter 23 constitute a clock synchronization verification circuit. The operation of this determination circuit will be explained with reference to FIG. In the figure, a is the received and recovered clock, b is the output waveform of the window circuit produced from the received and recovered clock, and c is the output of the differential circuit in FIG. 2B. That is, when the reception clock is regenerated, the reception clock component output from the differentiating circuit shown in FIG. 3c becomes concentrated in the section τ ₁ of the window waveform shown in b. Conversely, if reception clock synchronization is not established, the phases of a and c are shifted, and as a result, b
The reception clock component of c is not concentrated in the interval τ ₁ of . From this, in FIG. 2, the frequency dividing circuit 18
The output of the window circuit 21 is input to the second up-down counter 2.
If the output signal of the differentiating circuit 13 is passed through the gate circuit 22 and used as the clock input of the second up-down counter 23, when the differentiating circuit output signal reaches the interval τ ₁ , the up-down setting signal When the counter exceeds a predetermined count value, it outputs a clock synchronization establishment signal to the count control circuit 15. When the second up-down counter 23 counts up to the carry output, it outputs a control signal to the gate circuit 22 to stop the clock input, so that the clock synchronization establishment signal operates stably.

The counter control circuit 15 is the digital PLL.
This is used to set the operating count value of the circuit's up-down counter. If clock synchronization has not been established, the operation count number is set to 8, for example, and after clock synchronization is established, the operation count number is set to 32, for example. This has the advantage that the clock synchronization establishment time is shortened to one-fourth compared to the case where the number of operation counts is fixed, and the normal reception characteristics do not deteriorate at all.

In addition, in FIG. 2, the clock synchronization verification circuit consisting of the window circuit 21, the gate circuit 22, and the second up-down counter 23 uses a method other than that described above, for example, in _FIG. , c for a certain period of time, and the clock synchronization is verified based on the counted number, it is clear that the same effect can be obtained.

Effects of the Invention As explained above, according to the present invention, the operating count number of the up-down counter of the digital PLL circuit used for synchronization verification is changed depending on whether or not clock synchronization is established, so that the reception rise time is This has the advantage of being faster and not deteriorating the reception characteristics. In other words, the small count number of the up-down counter of the digital PLL circuit is effective for quickly establishing clock phase synchronization even if some phase jitter is allowed, and once synchronization is established, it is effective. For example, by increasing this count, the phase jitter of the regenerated clock is reduced due to the integral effect, so a clock synchronization circuit can be constructed that can perform control adapted to the synchronization situation without affecting data reception. The effect will be obtained.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a digital communication receiver using a conventional clock synchronization circuit, Fig. 2 is a block diagram of a clock synchronization circuit according to an embodiment of the present invention, and Fig. 3 is a clock synchronization verification circuit of Fig. 2. FIG. 2 is a timing diagram showing signal timing of FIG. 12...Input terminal, 13...Differential circuit, 14...
...Phase comparison circuit, 15...Counter control circuit, 1
6...First up/down counter, 17...Variable frequency divider circuit, 18...Frequency divider circuit, 19...Oscillation circuit, 20...Crystal oscillator, 21...Window circuit, 22...Gate circuit, 23...Second up-down counter, 24...Output terminal.

Claims (1)

[Claims] 1. Take out the digital reception signal via a differentiating circuit, compare the phase with the reproduced clock signal obtained by dividing the reference oscillation frequency by a variable frequency divider, and calculate the up or down of the first up-down counter. down mode control is defined, the output of the differentiating circuit is used as a clock input of the first up-down counter, and when the count exceeds a predetermined operation count, the frequency division number of the variable frequency divider is changed. a digital PLL circuit that performs phase synchronization of the transmission clock, and a second up-down counter that counts the output of the differentiating circuit; A clock synchronization verification circuit that determines phase synchronization based on a signal and a count number, and a clock synchronization verification circuit that determines the operation count of the first up-down counter using a phase synchronization determination output signal of the clock synchronization verification circuit when clock synchronization is not established. A clock synchronization circuit equipped with a counter control circuit that selects a small number and controls it to increase when synchronization is established.