JPH0218795B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image defect compensation device for an image sensor.

[Prior art] Figure 7 shows the Technical Report of the Television Society VOL.7.
This is a conventional image defect compensation device for an image sensor shown on pages 19 to 24 of No. 14. In the figure,
The output signal of the imaging section 1 is clamped by a clamp circuit 2. The output of the clamp circuit 2 is applied to a multiplier circuit 3 and also to a multiplier circuit 7 via a delay circuit 6. The multiplication circuit 7 is controlled by the defect compensation signal from the defect compensation signal generation circuit 8,
The multiplier circuit 3 is controlled by a signal obtained by inverting the defect compensation signal in an inverting circuit 5. Multiplier circuit 3
and the output of the multiplier circuit 7 are added together in the adder circuit 4 to produce an output signal compensated for image defects of the image sensor.

Next, the operation will be explained. FIG. 8 is a diagram for explaining the operation. The zero level of the output signal of the imaging section 1 is clamped to the potential E by the clamp circuit 2. This is shown in Figure 8b. FIG. 8a shows a filter arrangement, and the signals shown in FIG. 8b correspond to the filter arrangement shown in FIG. 8a. When the signal shown in FIG. 8b is input to the delay circuit 6, the signal shown in FIG. 8c is output. The multiplier circuit 3 operates to output the clamp potential E when the input terminal 3A is at a low level, and outputs the signal from the input terminal 3B when the input terminal 3A is at a high level.
The multiplier circuit 7 operates to output the clamp potential E when the input terminal 7A is at a low level, and to output the signal from the input terminal 7B when the input terminal 7A is at a high level. Assume now that the nth signal is a signal due to a defective pixel, as shown in FIG. 8b. Figure 8 d is
A corresponding defect compensation signal is output from the defect compensation signal generation circuit 8. Incidentally, since the inversion circuit 5 inputs the inverted defect compensation signal shown in FIG. 8d to the input terminal 3A of the multiplier circuit 3, the output becomes the signal shown in FIG. 8e. Since the defect compensation signal shown in FIG. 8d is inputted to the input terminal 7A of the multiplier circuit 7, its output becomes the signal shown in FIG. 8f. When the defect compensation signal is at a low level, the adder circuit 4 outputs the output signal of the clamp circuit 2 shown in FIG. 8b, and when the defect compensation signal is at a high level, it outputs the output signal of the delay circuit 6 shown in FIG. 8c. do. Through the above operations, the signal from the nth defective pixel is replaced with the signal from the (n-2)th pixel, as shown in FIG. 8g. The principle of this image defect compensation device is based on the principle that signals of pixels that are close to each other have approximately the same value due to the correlation of images.

Note that the defect compensation signal generation circuit includes a storage device to store the position of the defective pixel, and generates the defect compensation signal based on the position of the defective pixel.

[Problems to be Solved by the Invention] The conventional image defect compensation device is configured as described above, and compensates by replacing the signal from the defective pixel with a signal from a pixel two clocks earlier, that is, two pixels apart. Therefore, if there is a sharp change in the image in front of a defective pixel, there are problems such as a large compensation error.

The present invention was made to solve the above-mentioned problems, and an object of the present invention is to provide an image defect compensation device with small compensation errors.

[Means for Solving the Problems] The image defect compensation device for an image sensor according to the present invention has a signal from another pixel whose signal is read out at the same time as the defective pixel, and a signal that is one clock from the time when the signal from the defective pixel is read out. means for generating a compensation signal by adding or subtracting a total of three signals from two pixels read out with the previous readout clock at a predetermined ratio depending on the color of a color filter; and means for replacing the signal of the pixel.

[Operation] According to the present invention, the signal of a defective pixel is read out using a signal from another pixel whose signal is read out at the same time as the defective pixel, and a readout clock that is one clock earlier than the time when the signal from the defective pixel is read out. A total of three signals of the signals from the two pixels are added or subtracted at a predetermined ratio depending on the color of the color filter.

[Example] FIG. 9 shows an example of the arrangement of color filters of an image sensor to which the present invention is applied. In the figure, W indicates a white filter, Ye indicates a yellow filter, Cy indicates a cyan filter, and G indicates a green filter. Here, the color and arrangement of the color filter of the image sensor that is the object of the present invention is not limited to that shown in FIG. 4 Regarding the colors of the 4 color filters on the 4 pixels of 2 rows x 2 columns arbitrarily selected
Any three colors among the color filters may be used in any color and arrangement as long as they serve as mutually independent source stimuli. Here, the fact that the three colors are mutually independent source stimuli means that two of the three colors are not equalized to the remaining one color by positive or negative additive color mixing.

Furthermore, the image sensor to which the present invention is applied has four output lines corresponding to the four color filters, and simultaneously outputs signals from two rows (two pixels adjacent to each other in the column direction) in synchronization with the readout clock. configured to read.

A case will be described below in which the concept of the conventional image defect compensating device described above is applied to an image sensor having a filter arrangement as shown in FIG. 9 to which the present invention is applied. For the sake of explanation, let us now consider the case where the W signal corresponding to the nth clock is a signal from a defective pixel. In this case, the W signal corresponding to the n-2nd clock is the W signal corresponding to the nth clock.
It is possible to compensate for image defects by replacing the signal. It is also possible to compensate for image defects with respect to the Ye signal, Cy signal, and G signal in the same manner as in the case of the W signal, in which the signal due to the defective pixel is replaced with a signal two clocks before the defective pixel. However, this conventional method has a problem in that the compensation error is large as described above.

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic block diagram showing a preferred embodiment of an image defect compensating device for an image sensor according to the present invention. In FIG. 1, the imaging unit 50 is W (white).
Signal output terminal 50A, Ye (yellow) signal output terminal 50
B, Cy (cyan) signal output terminal 50C, and G
(Green) Has a signal output terminal 50D. These output terminals 50A to 50D are connected to switch circuits 51 to 6.
2, 63, 65, 67, and 69.
The outputs of the switch circuits 51 to 54 are connected to the input terminal 71A of the inversion circuit 71, and the output terminal 71B of the inversion circuit 71 is connected to the input side of the addition circuit 74. The outputs of the switch circuits 55 to 58 are output to the delay circuit 7.
The output terminal 72B of the delay circuit 72 is connected to the input side of the adder circuit 74. The outputs of the switch circuits 59 to 62 are connected to the input terminal 73A of the delay circuit 73.
The output terminal 73B of is connected to the input side of the adder circuit 74. An output terminal 74A of the adder circuit 74 is connected to switch circuits 64, 66, 68, and 70. The switch circuits 51-70 are controlled by a defect compensation control signal generating circuit 75, and are closed when the respective terminals 51A-70A are at a high level, and are opened when the respective terminals 51A-70A are at a low level. The defect compensation control signal generation circuit 75 includes a storage device therein, and stores the position of the defective pixel and the type of color filter of the defective pixel. Output terminal 8
A compensated W signal is output from 0A, a compensated Ye signal is output from output terminal 80B,
A compensated Cy signal is output from the output terminal 80C, and a compensated G signal is output from the output terminal 80D.

Next, the operation will be explained. As mentioned above, the W signal, Ye signal, Cy signal, and G signal are at the second clock with respect to the signal readout clock (hereinafter referred to as clock).
The output is as shown in Figures b to e. When all pixels have the same spectral distribution characteristics and the same amount of light is incident, the above-mentioned W signal amount (hereinafter referred to as W), Ye
The following relationship holds between the signal amount (hereinafter referred to as Ye), the Cy signal amount (hereinafter referred to as Cy), and the G signal amount (hereinafter referred to as G) depending on the spectral transmission characteristics of each filter.

W+G=Ye+Cy...(1) The reason why formula (1) holds is shown below. Letting the amount of red light be R and the amount of green light be B, then W=R+G+B Ye=R+G Cy=B+G G=G Therefore, W+G=R+G+B+G =Ye+Cy.

By transforming equation (1), the following four equations are obtained.

W=Ye+Cy-G...(2) Ye=W+G-Cy...(3) Cy=W+G-Ye...(4) G=Ye+Cy-W...(5) The nth clock shown in Figure 2a W corresponding to
Regarding the case where the signal is due to a defective pixel,
The operation will be explained below. Here, it is assumed that the amount of W signal that should originally exist corresponding to the n-th clock is W(n).
Also, the G signal corresponding to the nth clock is expressed as G(n)
and the Ye signal corresponding to the n-1th clock,
Letting the Cy signals be Ye (n-1) and Cy (n-1), respectively, the adjacent pixels have almost the same spectral distribution characteristics and almost the same amount of light entering the pixels due to the correlation of the images, so the formula ( 2), the following formula holds.

W(n)≒Ye(n-1)+Cy(n-1)-G(n)
...(6) Defect compensation is performed by replacing the signal from the defective pixel with the signal W(n) shown in equation (6). The circuit shown in FIG. 1 is a circuit that realizes equation (6). The operation will be explained below using FIGS. 2 and 3. FIG. 3 shows terminals 51A, 52A,
..., 70A is a diagram showing the voltage. The switch circuits 51, 52, . . . , 70 are closed when the voltages at the corresponding terminals 51A, 52A, . . . , 70A are high level, and are opened when the voltages are low level.
The clock shown in FIG. 3a here corresponds to the clock in FIG. 2a. Terminals 51A, 52A,
..., 70A is generated from a defect compensation control signal generation circuit 75 which includes a storage device therein and stores the position of the defective pixel and the type of color filter of the defective pixel. switch circuits 51, 52,
..., 70 are opened and closed by the voltage shown in FIG.
Assuming that the waveforms of 0C and 50D are as shown in FIG. 2 b, c, d, and e, the input terminals 71A,
72A, 73A, output terminals 71B, 72B, 73
B, 74A shows Fig. 2 f, g, h, i, j, k,
A waveform shown at l appears. Here, the inversion circuit 71
outputs the signal components after inverting the positive and negative values with reference to the zero level of the input signal, and the delay circuits 72 and 73 delay the input signal by one clock time and output it.
The adder circuit 74 is configured to add signal components of terminals 71B, 72B, and 73B and output the result. The numbers in parentheses in Figure 2 indicate each terminal.

As a result of the above operations, a defect-compensated W signal is obtained at the W signal output terminal 80A as shown in FIG. 2m. Other output terminals 80B, 80C, 80
At D, the same waveforms as shown in FIGS. 2c, d, and e appear.

Next, consider the case where the Ye signal includes a signal due to a defective pixel. Assuming that the clock corresponding to the defective pixel is the i-th clock, the following equation holds true corresponding to equation (6) using the same concept as the defect compensation in the W signal described above.

Ye(i)≒W(i-1)+G(i-1)-Cy(i)...(7) In order to realize this equation, the voltages shown in FIG. ,...,70A to open and close the switch circuits 51, 52,...,70. In this way, even if there is a signal due to a defective pixel in the Ye signal, it is possible to compensate for the defect in the same manner as in the case of the W signal.

Next, consider the case where there is a signal due to a defective pixel in the Cy signal. Assuming that the clock corresponding to the defective pixel is the j-th clock, the following equation holds true corresponding to equation (6) using the same concept as the defect compensation in the W signal described above.

Cy(j)≒W(j-1)+G(j-1)-Ye(j)...(8) In order to realize this equation, the voltages shown in FIG. ,...,70A to open and close the switch circuits 51, 52,...,70. In this way, even if there is a signal due to a defective pixel in the Cy signal, it is possible to compensate for the defect in the same way as in the case of the W signal.

Finally, consider the case where there is a signal due to a defective pixel in the G signal. Assuming that the clock corresponding to the defective pixel is the k-th clock, the following equation holds true corresponding to equation (6) using the same concept as the defect compensation in the W signal described above.

G(k)≒Ye(k-1)+Cy(k-1)-W(k)
(7) In order to realize this equation, the voltages shown in FIG. 6 b to u are applied to the terminals 51A, 52A, . In this way, even if there is a signal due to a defective pixel in the G signal, it is possible to compensate for the defect in the same manner as in the case of the W signal.

In the above embodiment, the case of using four color filters of white, yellow, cyan, and green was described, but as mentioned above, the color of the four color filters can be any three of the four colors. Any color may be used as long as these three colors serve as mutually independent primary stimuli. In other words, if any one of the four colors can be represented by additive color mixing of the other three colors by negative or positive amounts, then a defect compensation circuit as described above can be constructed using a delay circuit, an addition circuit, etc. Can be done.

[Effects of the Invention] As described above, according to the present invention, defects can be compensated for by replacing signals from defective pixels with signals from pixels that are closer to the defective pixel than in conventional devices. Therefore, even if there is a sharp change in the image before the defective pixel, the compensation error can be reduced.

[Brief explanation of drawings]

FIG. 1 is a schematic block diagram showing an image defect compensation device for an image sensor according to a preferred embodiment of the present invention, FIGS. 2 to 6 are diagrams for explaining the operation of an embodiment of the present invention, and FIG. The figure is a schematic block diagram showing a conventional image defect compensation device for an image sensor, FIG. 8 is a diagram for explaining the operation of the conventional device, and FIG. 9 is an example of the arrangement of color filters in an image sensor to which the present invention is applied. FIG. In the figure, 50 is an imaging section, 51 to 70 are switch circuits, 71 is an inversion circuit, 72 and 73 are delay circuits, 74 is an addition circuit, and 75 is a defect compensation control signal generation circuit.

Claims (1)

[Claims] 1. In an image sensor in which pixels are arranged in rows and columns and signals related to two pixels adjacent to each other in the column direction are simultaneously read out in synchronization with a readout clock, there is a defective pixel that does not output a normal signal. An image defect compensation device, if present, wherein four pixels in any two rows by two columns of pixels are associated with four different colors, and any three of the four colors are each They are source stimuli that are independent of each other, and the first signal from another pixel adjacent to the defective pixel in the column direction, which is read out simultaneously with the defective pixel, and the time at which the signal from the defective pixel is read are 1.
A compensation signal is generated by adding and subtracting a second signal and a third signal from two pixels adjacent to each other in the column direction, which are simultaneously read out by a readout clock before the clock, at a predetermined ratio according to the four colors. An image defect compensation device for an image sensor, comprising: means for replacing a signal caused by the defective pixel with the compensation signal.