JPH0219678B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image defect compensation device for an image sensor.

[Conventional technology]

Figure 12 shows the technical report of the Television Society.
This figure shows a conventional image defect compensation device for an image sensor similar to the one shown on pages 19 to 24 of Vol. 7, No. 14. In the figure, the output signal of an imaging section 1 is clamped by a clamp circuit 2. Clamp circuit 2
The output of is given to one input of the delay circuit 3 and the adder circuit 7. The output of delay circuit 3 is sent to multiplication circuit 4
It is also applied to the other input of the adder circuit 7 via the delay circuit 6. The addition output of the addition circuit 7 is given to the multiplication circuit 8. Multiplication circuit 8
is controlled by a defect compensation signal from a defect compensation signal generation circuit 10, and the multiplier circuit 4 is controlled by a signal obtained by inverting the defect compensation signal in an inverting circuit 9. The output of the multiplier circuit 4 and the output of the multiplier circuit 8 are added in an adder circuit 5 to produce an output signal compensated for image defects of the image sensor.

Next, the operation will be explained. FIG. 13 is a diagram for explaining the operation. The zero level of the output signal of the imaging section 1 is clamped to the voltage E by the clamp circuit 2. This is shown in Figure 13b. Figure 13a is
The signal shown in FIG. 13b corresponds to the filter arrangement shown in FIG. 13a. When the signal shown in FIG. 13b is input to the delay circuit 3, the signal shown in FIG. 13c is output. When the signal shown in FIG. 13c is input to the delay circuit 6, the signal shown in FIG. 13d is output. The multiplier circuit 4 operates to output the clamp potential E when the input terminal 4A is at a low level, and to output the signal from the input terminal 4B when the input terminal 4A is at a high level. The multiplier circuit 8 operates to output the clamp potential E when the input terminal 8A is at a low level, and outputs the signal from the input terminal 4B when the input terminal 8A is at a high level. Assume now that the nth signal is a signal from a defective pixel, as shown in FIG. 13b. Further, the corresponding defect compensation signal which is the output of the defect compensation signal generation circuit 10 is shown in FIG. 13f. When the output of the clamp circuit 2 shown in FIG. 13b and the output of the delay circuit 6 shown in FIG. 13d are input to the adder circuit 7, the signal shown in FIG. 13e is output.
Here, it is assumed that the adder circuit 7 outputs a value obtained by multiplying the sum of two inputs by 1/2. By the way, since the inversion circuit 9 inputs the inverted defect compensation signal shown in FIG. 13f to the input terminal 4A of the multiplier circuit 4,
The output becomes the signal shown in FIG. 13g. Since the defect compensation signal shown in FIG. 13f is inputted to the input terminal 8A of the multiplier circuit 8, the output thereof is shown in FIG. 13h.
The signal will be as shown in . The adder circuit 5 outputs the output signal of the delay circuit 3 shown in FIG. 13c when the defect compensation signal is at a low level, and outputs the output signal of the adder circuit 7 shown in FIG. 13e when the defect compensation signal is at a high level. Through the above operations, as shown in Figure 13i,
The signal due to the nth defective pixel is replaced by 1/2 of the sum of the signal due to the n-2nd pixel and the signal due to the n+2nd pixel. The principle of this image defect compensation device is based on the principle that signals of pixels that are close to each other have approximately the same value due to the correlation of images. Note that the defect compensation signal generation circuit includes a storage device to store the position of the defective pixel, and generates the defect compensation signal based on the position of the defective pixel.

[Problem that the invention seeks to solve]

The conventional image defect compensation device is configured as described above, and compensates the signal from the defective pixel using the signal from the pixel two blocks before and after, that is, two pixels apart. When there is a steep change, there are problems such as a large compensation error.

The present invention was made to solve the above-mentioned problems, and an object of the present invention is to provide an image defect compensation device with a small compensation error.

[Means for Solving the Problems] The image defect compensation device for an image sensor according to the present invention has a signal from another pixel whose signal is read out at the same time as the defective pixel, and a signal from the defective pixel that is one clock from the time when the signal from the defective pixel is read out. A means for generating a compensation signal by adding or subtracting a total of five signals of signals from four pixels read out by the front and rear readout clocks at a predetermined ratio depending on the color of a color filter; and means for replacing the signal with the compensation signal.

[Effect]

According to this invention, the signal of a defective pixel is read out using a signal from another pixel whose signal is read out at the same time as the defective pixel, and a readout clock one clock before and one clock after the time when the signal from the defective pixel is read out. 4
A total of five signals from one pixel are replaced by a compensation signal obtained by adding or subtracting a total of five signals at a predetermined ratio depending on the color of the color filter.

〔Example〕

FIG. 14 shows an example of the arrangement of color filters of an image sensor to which the present invention is applied. In the figure, W is a white filter, Ye is a yellow filter, Cy is a cyan filter,
G indicates a green filter. Here, the color and arrangement of the color filter of the image sensor that is the object of the present invention are as follows.
Although not limited to those shown in Fig. 4, 4 pixels on four randomly selected 2 rows x 2 columns of pixels of an image sensor in which pixels are arranged in the horizontal (row) direction and the vertical (column) direction Regarding the color of the color filter part 4
Any three colors among the color filters may be used in any color and arrangement as long as they serve as mutually independent source stimuli. Here, the fact that the three colors are mutually independent source stimuli means that two of the three colors are not equalized to the remaining one color by positive or negative additive color mixing. Furthermore, the image sensor to which the present invention is applied has four output lines corresponding to the four color filters, and simultaneously outputs signals from two rows (two pixels adjacent to each other in the column direction) in synchronization with the readout clock. configured to read.

A case will be described below in which the concept of the conventional image defect compensating device described above is applied to the filter array image sensor shown in FIG. 14 to which the present invention is applied. For the sake of explanation, let us now consider the case where the W signal corresponding to the nth clock is a signal from a defective pixel. In this case, image defects can be detected by replacing the W signal corresponding to the n-th clock with a signal that is 1/2 of the sum of the W signal corresponding to the n-2nd clock and the W signal corresponding to the n+2-th clock. It is possible to compensate for Image defects are compensated for the Ye signal, Cy signal, and G signal using the same method as for the W signal, in which the signal due to the defective pixel is replaced with 1/2 of the sum of the signal two clocks before and the signal two clocks later. It is possible. However, as mentioned above, this conventional method has a problem in that the compensation error is large.

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic block diagram showing an image defect compensation device for an image sensor, which is a preferred embodiment of the present invention. In FIG. 1, the imaging unit 50 is
It has a (white) signal output terminal 50A, a Ye (yellow) signal output terminal 50B, a Cy (cyan) signal output terminal 50C, and a G (green) signal output terminal 50D. Each of the output terminals 50A to 50D of the imaging unit 50 is connected to the input terminals 80A to 83A of the delay circuits 80 to 83, respectively, and also connected to the set of switch circuits 71 to 74 and the set of switch circuits 75 to 78, respectively. . Output terminal 80 of delay circuits 80 to 83
B to 83B are a set of switch circuits 51 to 54, a set of switch circuits 55 to 58, and a set of switch circuits 59 to 58;
62 sets, and switch circuits 63, 65, 6
They are connected to groups 7 and 69, respectively. Each switch circuit 51 to 78 is a defect compensation control signal generation circuit 89
and each terminal 51A to 78
Closed when A is at high level, terminals 51A to 7
It is opened when 8A is at low level. The defect compensation signal generation circuit 89 includes a storage device therein, and stores the position of a defective pixel and the type of color filter of the defective pixel.

The set of switch circuits 51-54 is connected to the input terminal 84A of the inverting circuit 84, and the switch circuits 55-54 are connected to the input terminal 84A of the inverting circuit 84.
The set of switch circuits 58 to 62 are connected to the input terminal 85A of the delay circuit 85, and the set of switch circuits 59 to 62 are connected to the input terminal 85A of the delay circuit 85.
6 input terminal 86A. Inversion circuit 84
The output terminal 84B is the input terminal 87 of the amplifier circuit 87.
A, and the output terminal 87B of the amplifier circuit 87 is connected to the input side of the adder circuit 88. Addition circuit 8
8, the output terminal 85B of the delay circuit 85 is connected to the input side of the delay circuit 85.
and output terminal 86B of delay circuit 86, and a set of switch circuits 71-74 and a set of switch circuits 75-78 are connected, respectively. The output terminal 88A of the adder circuit 88 is connected to the input terminal 102A of the amplifier circuit 102, and the output terminal 102B of the amplifier circuit 102 is connected to the switch circuits 64, 66, 6.
It is connected to pairs 8 and 70. switch circuit 6
A compensated W signal is output from the output terminal 90A connected to the switch circuit 65 and 64.
A compensated Ye signal is output from the output terminal 90B connected to the switch circuit 67 and
A compensated Cy signal is output from the output terminal 90C connected to the switch circuits 69 and 68, and a compensated G signal is output from the output terminal 90D connected to the switch circuits 69 and 70.

Next, the operation will be explained. As mentioned above, the W signal, Ye signal, Cy signal, and G signal are at the second clock with respect to the signal readout clock (hereinafter referred to as clock).
The output is as shown in Figures b to e.

When all pixels have the same spectral distribution characteristics and the same amount of light is incident, the above-mentioned W signal amount (hereinafter referred to as W), Ye signal amount (hereinafter referred to as Ye),
The following relationship holds between the Cy signal amount (hereinafter referred to as Cy) and the G signal amount (hereinafter referred to as G) depending on the spectral transmission characteristics of each filter.

W+G=Ye+Cy...(1) The reason why formula (1) holds is shown below. If the amount of red lights is R and the amount of green lights is B, then W=R+G+B Ye=R+G Cy=B+G G=G Therefore, W+G=R+G+B+G =Ye+Cy.

By transforming equation (1), the following four equations are obtained.

W=Ye+Cy-G...(2) Ye=W+G-Cy...(3) Cy=W+G-Ye...(4) G=Ye+Cy-W...(5) W corresponding to the n-th clock shown in Figure 2 a
Regarding the case where the signal is due to a defective pixel,
The operation will be explained below. Here, let W(n) be the original signal amount corresponding to the n-th clock.
Also, the G signal corresponding to the nth clock is expressed as G(n)
and the Ye signal corresponding to the n-1th clock,
Let the Cy signals be Ye(n-1) and Cy(n-1), respectively, and the Ye signal corresponding to the n+1th clock,
Let the Cy signals be Ye (n+1) and Cy (n+1), respectively. Due to the correlation between images, adjacent pixels have approximately the same spectral distribution characteristics and approximately the same amount of light, so the following two equations hold true based on equation (2).

W(n)≒Ye(n-1)+Cy(n-1) -G(n)...(6) W(n)≒Ye(n+1)+Cy(n+1) -G(n)...(7) Equation ( From 6) and (7), W(n)≒{Ye(n-1)+Cy(n-1) +Ye(n+1)+Cy(n-1) -2G(n)}/2...(8) Equation (8) Defect compensation is achieved by replacing the signal from the defective pixel with the signal W(n) shown in ). The circuit shown in FIG. 1 is a circuit diagram that realizes equation (8). Figures 2, 3, and 4 are shown below.
The operation will be explained using FIG. 4 and 5 are terminals 51A, 52A,...,
It is a figure which shows the voltage of 78A. switch circuit 5
1, 52,..., 78 are the corresponding terminals 5
It is closed when the voltages of 1A, 52A, . . . , 78A are high level, and opened when the voltages are low level. Here, the clocks shown in FIGS. 3a, 4a, and 5a correspond to the clocks shown in FIG. 2a.
The voltages at the terminals 51A, 52A, . . . , 78A are generated from a defect compensation control signal generation circuit 89 which includes a storage device therein and stores the position of the defective pixel and the type of color filter of the defective pixel.

Here, the inverting circuit 84 inverts the signal component with the zero level of the input signal as a reference and outputs it, and the delay circuits 80, 81, 82, 83, 85, and 86 delay the input signal by one clock time and output it. The adder circuit 88 adds and outputs the signal components of the terminals 87B, 85B, 86B and lines 100 and 101, the amplifier circuit 87 doubles the signal component and outputs it, and the amplifier circuit 102 doubles the signal component and outputs it. / They are each configured to double the output. The switch circuits 51, 52, . . . , 78 are opened and closed by the voltages shown in FIGS. , e, the waveforms shown in FIG. 2 f, g, h, and i appear at the output terminals 80B, 81B, 82B, and 83B, and the waveforms shown in FIG. 3 appear at the input terminals 84A, 85A, and 86A. b,
The waveforms shown in c and d appear, and the output terminals 84B, 8
Figure 3 e, f, g, h for 7B, 85B, 86B.
The waveform shown in appears, line 100, line 10
1, the waveforms shown in FIG. 3f and j appear, and the waveforms shown in FIG. 3k and l appear at the output terminals 88A and 102B. As a result of the above operations, the output terminal 90A
As shown in FIG. 2j, a defect-compensated W signal is obtained. Other output terminals 90B, 90C, 90
The same waveforms as in FIG. 2 g, h, and i appear in D.

Next, consider the case where the Ye signal includes a signal due to a defective pixel. Assuming that the clock corresponding to the defective pixel is the first clock, the following equation holds true corresponding to equation (8) using the same concept as the defect compensation in the W signal described above.

Ye(i)≒{Y(i-1)+G(i-1) +W(i+1)+G(i+1) -2Cy(i)}/2...(9) In order to realize this equation, Figure 6b ~u, 7th
The voltages shown in Figures b to i are applied to terminals 51A, 52A,
..., 78A, switch circuits 51, 52,
..., 78 opens and closes. In this way, even when there is a signal due to a defective pixel in the Ye signal,
The defect can be compensated for in the same manner as in the case of the W signal described above.

Next, consider the case where there is a signal due to a defective pixel in the Cy signal. If the clock corresponding to the defective pixel is the j-th clock, the following equation holds true corresponding to equation (8) using the same concept as the defect compensation in the W signal described above.

Cy(j)≒{W(j-1)+G(j-1) +W(j+1)+G(j+1) -2Ye(j)}/2...(10) In order to realize this equation, Fig. 8b ~u, 9th
The voltages shown in Figures b to i are applied to terminals 51A, 52A,
..., 78A, switch circuits 51, 52,
..., 78 opens and closes. In this way, even when there is a signal due to a defective pixel in the Cy signal,
The defect can be compensated for in the same manner as in the case of the W signal described above.

Finally, consider the case where there is a signal due to a defective pixel in the G signal. Assuming that the clock corresponding to the defective pixel is the k-th clock, the following equation holds true corresponding to equation (8) using the same concept as the defect compensation in the W signal described above.

G(k)≒{Ye(k-1)+Gy(k-1) +Ye(k+1)+Cy(k-1) -2W(k)}/2...(11) In order to realize this equation, the 10th The voltages shown in Figures b to u and Figure 11b to i are applied to the terminals 51A and 52.
A,...,78A, switch circuits 51,5
2,...,78 are opened and closed. In this way, even if there is a signal due to a defective pixel in the G signal, it is possible to compensate for the defect in the same manner as in the case of the W signal described above.

In the above embodiment, the case of using four color filters of white, yellow, cyan, and green was described, but as mentioned above, the colors of the four color filters can be any three of the four colors. Any color may be used as long as the three colors serve as mutually independent primary stimuli.
In other words, if any one of the four colors can be represented by additive color mixing of the other three colors by negative or positive amounts, the aforementioned defect compensation circuit can be constructed using delay circuits, adder circuits, etc.

〔Effect of the invention〕

As described above, according to the present invention, the defect is compensated for by replacing the signal from the defective pixel with the signal from the pixel that is closer to the defective pixel than in the case of conventional devices. Even when there is a sharp change in the image before and after a pixel, the compensation error can be reduced.

[Brief explanation of drawings]

FIG. 1 is a schematic block diagram showing an image defect compensation device for an image sensor, which is a preferred embodiment of the present invention.
2 to 11 are diagrams for explaining the operation of an embodiment of the present invention, FIG. 12 is a schematic block diagram showing a conventional image defect compensation device for an image sensor, and FIG. 13 is a diagram illustrating the operation of the conventional example. An explanatory diagram, FIG. 14, is a diagram showing an example of the arrangement of color filters of an image sensor to which the present invention is applied. In the figure, 50 is an imaging unit, 51 to 78 are switch circuits, 80 to 83, 85, and 86 are delay circuits,
84 is an inversion circuit, 88 is an adder circuit, and 89 is a defect compensation control signal generation circuit.

Claims (1)

[Claims] 1. In an image sensor in which pixels are arranged in rows and columns and signals related to two pixels adjacent to each other in the column direction are simultaneously read out in synchronization with a readout clock, there is a defective pixel that does not output a normal signal. An image defect compensation device, if present, wherein four pixels in any two rows by two columns of pixels are associated with four different colors, and any three of the four colors are each They are source stimuli that are independent of each other, and the first signal from another pixel adjacent to the defective pixel in the column direction, which is read out simultaneously with the defective pixel, and the time at which the signal from the defective pixel is read are 1.
A second signal and a third signal from two pixels adjacent to each other in the column direction are read out simultaneously by a readout clock before the clock, and a readout clock is read out by a readout clock one clock after the time at which the signal from the defective pixel is read out. The fourth signal and the fifth signal from two pixels adjacent to each other in the column direction are
An image defect compensation device for an image sensor, comprising: means for generating a compensation signal by adding and subtracting two colors at a predetermined ratio; and means for replacing a signal caused by the defective pixel with the compensation signal.