JPH0219665B2 - - Google Patents

Description

[Detailed description of the invention]

[Industrial Application Field] The present invention relates to a method of performing phase shift keying using a modulation signal on a carrier wave of a specific frequency when transmitting various data. [Prior art] To perform phase shift (PSK) modulation,
As is well known, a phase-shifted carrier wave is obtained by applying a specific phase shift to the original carrier wave using a phase-shifting circuit.
It has become common practice to control a switch or the like using a value modulation signal to select an original carrier wave and a phase-shifted carrier wave to obtain a PSK signal. [Problem to be solved by the invention] However, in the above-mentioned method, since the selection is performed using a switch etc., the phase change of the PSK signal becomes rapid, and accordingly, side waves are generated on both the high and low sides of the carrier wave. Bands occur over a wide area, and in order to narrow this sideband and prevent interference to others, it is necessary to use a band waver with a steep cutoff characteristic, which causes the problem of being expensive and bulky. There is. Note that when a plurality of carrier waves having different frequencies are used, a band waver is required for each carrier wave, and the problem that the entire device becomes expensive and large becomes even more significant. [Means for Solving the Problems] In order to solve the above-mentioned problems, the present invention is constituted by the following means. That is, for a microcomputer having first and second counters inside, a first clock pulse having a frequency that is an integral multiple of the frequency of the carrier wave and a frequency corresponding to the phase shift transient period of the phase shift signal. A second clock pulse having a value of A constant value is successively added to the counter, and when the modulation signal indicates the first value, the count value of the second counter is successively subtracted according to the second clock pulse until the count value becomes zero, and the modulation signal becomes the second value. When indicating, the phase shift amount and the count value of the second counter are sequentially added and subtracted according to the second clock pulse until they match, and the value obtained by adding each count value of the first and second counters is calculated as a sine. The processor of the microcomputer repeats the operation of converting to wave data and sending it out, converting the sine wave data to an analog signal and generating a PSK signal. [Operation] Therefore, the first counter repeats addition up to a certain value in response to the first clock pulse, and the count value indicates each instantaneous value of the carrier wave, while the value of the modulation signal Therefore, the second counter performs addition or subtraction in response to the second clock pulse, and its count value indicates the amount of phase shift, and if the respective count values of the first and second counters are added, Since each instantaneous value of the PSK signal is obtained, the PSK signal is obtained by converting this into sine wave data and then further converting it into an analog signal. Therefore, by repeating the above operations,
If the modulation signal is at the first value, a carrier wave with the original phase is generated, and if the modulation signal is at the second value, a carrier wave with an advanced phase is generated, and the transition period of the phase change is determined by the addition of the second counter and the carrier wave with the advanced phase. Determined by the subtraction speed, the phase change of the PSK signal will not be sudden, and wide sidebands will not occur. [Example] Hereinafter, details of the present invention will be explained with reference to figures showing examples. Figure 1 is a block diagram of the entire configuration. A microcomputer (hereinafter referred to as μCP) 1 includes a processor (hereinafter referred to as CPU) 11 and a fixed memory (hereinafter referred to as ROM).
Consists of 12, variable memory (hereinafter referred to as RAM) 12, and interfaces (hereinafter referred to as I/F) 14 to 16, CPU 11 executes instructions in ROM 12, and predetermined data is accessed from RAM 13. It has become a device that performs the operations of the CPU 11 or the RAM 1.
A first and a second counter are configured by the specific areas in 3, which are used to generate a PSK signal. Note that the data of the sine wave signal is stored in the ROM 12 or RAM 13 as a table for at least 1/2 cycle, and this is used to control the CPU.
11 is for converting into sine wave data. In addition, μCP1 has the first and second interrupt inputs.
INT ₁ and INT ₂ , which include a first clock pulse P _C1 having a frequency N·f _T that is an integer N times higher than the carrier frequency f _T of the PSK signal, and a phase change transient of the PSK signal. A second clock pulse P _C2 having a frequency f _S corresponding to the period is given to each clock pulse, and the CPU 11 performs interrupt processing in accordance with these clock pulses, and also generates a binary modulation signal S _M and a phase deviation consisting of a bits. A signal _SSV indicating the amount of movement is given as data via I/Fs 14 and 15, and a predetermined operation is repeated according to these, and sine wave data Ds is sent out from I/F 16. There is. The sine wave data Ds is converted into an analog signal by a digital-to-analog converter (hereinafter referred to as DAC) 2, but this includes quantization noise due to the digital processing of μCP1, and a low frequency converter (hereinafter referred to as DAC) 2 converts the sine wave data Ds into an analog signal. After removing this using LPF) 3, PSK
The signal S is sent out as _PS . FIG. 2 is a flowchart of steady processing by the CPU 11, in which each count value "n ₁ + n ₂ = n" 101 of the above-mentioned first and second counters is calculated, and based on "n" according to the above-mentioned table. Convert to Ds" 102 is performed, and the resulting sine wave data is sent 103 to Ds, and then steps 101 and subsequent steps are repeated. Here, if the constant value is N-1 and this is represented by, for example, a 3-digit binary number [111], then the count value n ₁ is [000] as described below.
~N-1 is repeated at a constant cycle according to the clock pulse P _C1 , and when the count value n ₂ is a 3-digit binary number [010] and [100], it is added to each count value n ₁ and n ₂ . The relationship with the value n is as shown in the following table. In other words, if the carry from the least significant digit to the fourth digit is rounded down, n ₁ is #0~#7, #8~
It changes with #15 as one cycle, and #7 and #15 have the maximum value, whereas when n ₂ a = [010], n ₁ + n ₂ a =
The maximum value of na shifts to #5 and #13, n ₂ b =
When [100], the maximum value of n ₁ + n ₂ b = nb shifts to #3 and #11, and the phase of change of n advances according to the value of n ₂ , and n is After reaching the maximum value [111], it will automatically return to the reset state of [000]. However, the required number of digits can be determined according to N-1, and an adder with the corresponding number of bits can be installed in the CPU.
11, or the CPU 11 and RAM 13, and may be applied to the step 101.

〔Effect of the invention〕

As is clear from the above explanation, according to the present invention, wide sidebands are not generated, an expensive and large band waver is not required, the device can be made safe and compact, and the amount of phase shift can be reduced. can be set freely, and remarkable effects can be obtained in PSK modulation for various applications.

[Brief explanation of drawings]

The figures show an embodiment of the present invention, in which Fig. 1 is an overall block diagram, Figs. 2 to 4 are flowcharts showing the operating status of the processor, and Fig. 5 is a timing chart showing changes in each value and data. It's a chat. 1...μCP (microcomputer), 2...
DAC (digital-to-analog converter), 11...
CPU (processor), 12...ROM (fixed memory), 13...RAM (variable memory), 14-15
...I/F (interface), INT ₁ , INT ₂ ...
...Interrupt input, P _C1 , P _C2 ...Clock pulse, S _M ...
...Modulation signal, S _SV ...Phase deviation amount signal, D _S ...Sine wave data, S _PS ...PSK (phase deviation) signal.

Claims (1)

[Claims] 1 A microcomputer equipped with first and second counters is provided with a first clock pulse having a frequency that is an integral multiple of the frequency of the carrier wave and a frequency corresponding to the phase change transition period of the phase shift signal. applying a second clock pulse having a value to the first and second interrupt inputs, respectively; and
providing a value modulation signal and a signal indicating a phase shift amount as data, and sequentially adding a constant value to a first counter in response to the first clock pulse;
When the modulation signal indicates a first value, the count value of the second counter is successively subtracted in response to the second clock pulse until the count value of the second counter becomes zero, and when the modulation signal indicates a second value, the phase the second counter until the deviation amount and the count value of the second counter match.
The processor of the microcomputer repeats the operations of sequentially adding and subtracting in response to the clock pulses of the first and second counters, and converting the sum of the count values of the first and second counters into sine wave data and sending it out. A phase shift modulation method characterized by converting sine wave data into an analog signal to generate a phase shift signal.